Erdeljac; John P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Erdeljac; John P..The latest application filed is for "integrated circuit with bonding layer over active circuitry".

Company Profile

0.16.2

Erdeljac; John P. - Plano TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Deep trench with self-aligned sinker Grant 9,431,286 - Pendharkar , et al. August 30, 2	2016-08-30
Integrated circuit with bonding layer over active circuitry Grant 6,683,380 - Efland , et al. January 27, 2	2004-01-27
Integrated circuit with bonding layer over active circuitry App 20030036256 - Efland, Taylor R. ; et al.	2003-02-20
LDMOS power device with oversized dwell Grant 6,424,005 - Tsai , et al. July 23, 2	2002-07-23
Metallization outside protective overcoat for improved capacitors and inductors App 20010019865 - Erdeljac, John P. ; et al.	2001-09-06
Metalization outside protective overcoat for improved capacitors and inductors Grant 6,284,617 - Erdeljac , et al. September 4, 2	2001-09-04
Transistor with increased operating voltage and method of fabrication Grant 6,153,451 - Hutter , et al. November 28, 2	2000-11-28
Integrated circuit with bonding layer over active circuitry Grant 6,144,100 - Shen , et al. November 7, 2	2000-11-07
Low voltage DMOS transistor Grant 5,825,065 - Corsi , et al. October 20, 1	1998-10-20
DMOS transistor with low on-resistance and method of fabrication Grant 5,719,421 - Hutter , et al. February 17, 1	1998-02-17
Method for making an EEPROM with thermal oxide isolated floating gate Grant 5,576,233 - Hutter , et al. November 19, 1	1996-11-19
Semiconductor device having polysilicon resistor with low temperature coefficient Grant 5,554,873 - Erdeljac , et al. September 10, 1	1996-09-10
Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient Grant 5,489,547 - Erdeljac , et al. February 6, 1	1996-02-06
Semiconductor process for manufacturing semiconductor devices with increased operating voltages Grant 5,330,922 - Erdeljac , et al. July 19, 1	1994-07-19
Vertical DMOS transistor built in an n-well MOS-based BiCMOS process Grant 5,317,180 - Hutter , et al. May 31, 1	1994-05-31
Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication Grant 5,171,699 - Hutter , et al. December 15, 1	1992-12-15
High voltage merged bipolar/CMOS technology Grant 4,994,887 - Hutter , et al. February 19, 1	1991-02-19
High voltage capacitor for integrated circuits Grant 4,805,071 - Hutter , et al. February 14, 1	1989-02-14

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