U.S. patent application number 09/817639 was filed with the patent office on 2001-09-06 for reduced leakage trench isolation.
Invention is credited to Beiley, Mark A., Breisch, James E., Connolly, Kevin M., Kakizawa, Akira, Kang, Jung S., Landau, Berni W., Li, Zong-Fu, Parks, Joseph W. JR., Weber, Cory E., Yu, Shaofeng.
Application Number | 20010019851 09/817639 |
Document ID | / |
Family ID | 46256446 |
Filed Date | 2001-09-06 |
United States Patent
Application |
20010019851 |
Kind Code |
A1 |
Connolly, Kevin M. ; et
al. |
September 6, 2001 |
Reduced leakage trench isolation
Abstract
Leakage current may be reduced in trench isolated semiconductor
devices by providing a buffer between the trench isolation and an
active area. For example, with a trench isolated photodiode, a
buffer of opposite conductivity type may be provided between the
trench and the diffusion that forms the p-n junction of the
photodiode.
Inventors: |
Connolly, Kevin M.;
(Chandler, AZ) ; Kang, Jung S.; (Chandler, AZ)
; Landau, Berni W.; (Beaverton, OR) ; Breisch,
James E.; (Chandler, AZ) ; Kakizawa, Akira;
(Phoenix, AZ) ; Parks, Joseph W. JR.; (Beaverton,
OR) ; Beiley, Mark A.; (Chandler, AZ) ; Li,
Zong-Fu; (Gilbert, AZ) ; Weber, Cory E.;
(Beaverton, OR) ; Yu, Shaofeng; (Lake Oswego,
OR) |
Correspondence
Address: |
TROP PRUNER & HU, PC
8554 KATY FREEWAY
SUITE 100
HOUSTON
TX
77024
US
|
Family ID: |
46256446 |
Appl. No.: |
09/817639 |
Filed: |
March 26, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09817639 |
Mar 26, 2001 |
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09310423 |
May 12, 1999 |
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6215165 |
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09310423 |
May 12, 1999 |
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09098881 |
Jun 17, 1998 |
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6259145 |
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Current U.S.
Class: |
438/73 ; 438/296;
438/424; 438/97 |
Current CPC
Class: |
H01L 27/1463 20130101;
H01L 31/103 20130101 |
Class at
Publication: |
438/73 ; 438/296;
438/424; 438/97 |
International
Class: |
H01L 021/00; H01L
021/336; H01L 021/76 |
Claims
What is claimed is:
1. A device comprising: a semiconductor structure having a surface;
a first region of a first conductivity type formed in the
structure; and a second region of a second conductivity type, the
second conductivity type being of a conductivity type opposite to
the first conductivity type, said second region formed between the
surface of the structure and the first region.
2. The device of claim 1 including a trench formed in said
structure, on either side of said first region.
3. The device of claim 2 including a third region of said second
conductivity type, formed between the trench and the first region
wherein said third region surrounds the first region.
4. The device of claim 1, wherein said third region is formed by a
well implant.
5. The device of claim 1, wherein said device is a photodiode.
6. The device of claim 3, wherein said first conductivity type is
n-type and said third region is a p-type epitaxial layer.
7. The device of claim 2 wherein said second region extends over
said first region spanning said trench.
8. The device of claim 7 including a contact formed to said first
region through said second region.
9. The device of claim 7 including a contact to said first region
through said trench.
10. A photosensitive device comprising: a support structure; a
first photosensitive region formed in said support structure; a
dielectric layer formed over said region; and a light transmissive
covering layer formed over said dielectric layer.
11. The device of claim 10, said region including a diffusion of a
first conductivity type surrounded by a region of opposite
conductivity type.
12. The device of claim 11, wherein said diffusion is n-type and is
formed in a p-type epitaxial layer.
13. The device of claim 10 wherein said covering layer is
polysilicon and said dielectric is a gate oxide.
14. The device of claim 11 wherein said conductive layer extends
over said region of opposite conductivity type.
15. The device of claim 14 including trench isolation regions on
either side of said photosensitive region, said conductive layer
spanning said isolation regions.
16. A method of forming a photosensitive device comprising: forming
a first region of a first conductivity type in a semiconductor
structure of a second conductivity type opposite said first
conductivity type; forming a trench in said structure; forming a
second region of said second conductivity type between said trench
and said first region; and forming a silicon region over said first
region.
17. The method of claim 16, including forming the second region as
part of a p-well.
18. The method of claim 16, including forming the second region
using a tip implant.
19. The method of claim 16 wherein forming said silicon region
includes forming a third region of conductivity type opposite to
said first conductivity type over said first region.
20. The method of claim 16 wherein forming said silicon region
includes forming a layer of polysilicon over a layer of gate oxide
over said first region.
21. A photosensitive device comprising: a semiconductor structure;
a depletion region formed in said structure; a conductive layer
formed over said depletion region; and an isolation region formed
in said structure, on either side of said depletion region, but
spaced therefrom.
22. The device of claim 21, wherein said device is a photogate.
23. The device of claim 22, including a third region between said
depletion region and said isolation region.
24. The device of claim 23, wherein said third region is formed by
a p-type region.
25. The device of claim 21 wherein said conductive layer is a gate
and said gate does not overlap said isolation region.
26. The device of claim 25 wherein said isolation region is a
trench isolation.
27. A method of forming a photosensitive device comprising: forming
a photosensitive region in a substrate; covering said region with a
dielectric layer; and protecting said layer from exposure to plasma
etch steps.
28. The method of claim 27 wherein protecting including forming a
light transmissive conductive layer over said dielectric.
29. A device comprising: a semiconductor structure; a first region
of a first conductivity type formed in the structure; a trench
isolation surrounding said first region; a second region between
said trench isolation and said first region, said second region
being of a conductivity type opposite that of said first region;
and a third region between said first and second regions, said
third region being of the same conductivity type as said second
region, but having a lower conductivity type concentration.
30. The device of claim 29 wherein said second region is a p-well
and said third region is a p-type epitaxial layer.
Description
[0001] This application is a continuation-in-part of U.S. patent
application Ser. No. 09/098,881, filed Jun. 17, 1998.
BACKGROUND
[0002] This invention relates generally to semiconductor
manufacturing processes and particularly to the use of trench
isolation in connection with semiconductor manufacturing
processes.
[0003] In a variety of semiconductor devices, trench isolation is
utilized to electrically isolate active areas from one another.
Trench isolation is used in modern semiconductor processes to
manufacture a variety of devices including transistors and
photodiodes.
[0004] Photodiodes used in an imaging array can be manufactured
using conventional complementary metal oxide semiconductor (CMOS)
processing. As a result, an imaging array can be produced on a
semiconductor structure which also contains logic circuits such as
microprocessors, memories and the like. A pixel sensor uses pixels
formed by photodiodes which receive light information from an image
and convert the light information to electrical signals that are
transferred to subsequent circuitry for further processing. The
image sensors may be active pixel sensors or passive pixel
sensors.
[0005] CMOS image sensors have advantages over the conventional
charge coupled device (CCD) image sensors because they may achieve
lower power consumption, integration of on-chip logic and lower
cost. However when the CMOS image sensors are integrated with other
logic circuits such as microprocessors, the sensors may need to be
made with processes which include silicidation and trench
isolation. Covering the photodiode with silicide would effectively
block the light that is incident on the photodiode and thereby
prevent the device from operating. However the silicide can be
prevented from covering the photodiode through the addition of one
or two masking steps.
[0006] The trenches used for trench isolation are generally dry
etched and, as a result, the trench surfaces usually have a large
number of interface states. These interface states lead to high
surface generation velocity and, as discovered by the present
inventors, a large dark current. The trench forming processes also
cause crystalline defects such as dislocations and stacking faults.
Those crystalline defects reduce carrier generation lifetime which
increases dark current. Dark current is a current which flows when
no light is incident on the camera. This is an undesirable
consequence of trench isolation. The dark current decreases
signal-to-noise ratios for the image `sensor and decreases image
quality.
[0007] Thus there is a continuing need for image sensors which can
be manufactured with advanced logic processes to enable the image
sensors and the logic devices to be integrated in a single
integrated circuit. There is also a more general need for
techniques for overcoming leakage currents in trench isolated
semiconductor devices.
SUMMARY
[0008] In accordance with one aspect, a photosensitive device
includes a semiconductor structure having a surface. A first region
of a first conductivity type is formed in the structure. A second
region of a second conductivity type, opposite to the first
conductivity type, is formed between the surface of the structure
and the first region.
[0009] In accordance with another aspect, a photosensitive device
includes a support structure, and a first photosensitive region
formed in the support structure. A dielectric layer is formed over
the region and a light transmissive covering layer is formed over
the dielectric layer.
[0010] In accordance with still another aspect, a photosensitive
device includes a semiconductor structure and a depletion region
formed in said structure. A conductive layer is formed over the
depletion region and an isolation region formed in the structure,
on either side of the depletion region, but spaced therefrom.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a greatly enlarged cross-sectional view of one
embodiment of the present invention;
[0012] FIG. 2 is a greatly enlarged cross-sectional view of another
embodiment of the present invention;
[0013] FIG. 3 is a greatly enlarged cross-sectional view of still
another embodiment of the present invention;
[0014] FIG. 4 is a greatly enlarged cross-sectional view of yet
another embodiment of the present invention.
[0015] FIG. 5 is a greatly enlarged cross-sectional view taken
along the line 6-6 of FIG. 6;
[0016] FIG. 6 is a top view of one embodiment corresponding to FIG.
5;
[0017] FIG. 7 is another top view of another embodiment
corresponding to FIG. 5;
[0018] FIG. 8 is a greatly enlarged cross-sectional view of another
embodiment of the present invention;
[0019] FIG. 9 is a greatly enlarged cross-sectional view of the
prior art;
[0020] FIG. 10 is a greatly enlarged cross-sectional view of yet
another embodiment of the invention; and
[0021] FIG. 11 is a greatly enlarged cross-sectional view of
another embodiment of the present invention;
DETAILED DESCRIPTION
[0022] A semiconductor device 11 formed in a semiconductor
structure 10, shown in FIG. 1, may include isolation trenches 18.
Isolation trenches are generally formed by a dry etching process
which can create interface states that lead to high surface
generation velocity and dark current in photosensitive devices,
such as photodiodes. The isolation trenches 18 are conventionally
filled with an oxide or other filler material.
[0023] In the illustrated embodiment, a photodiode is formed that
includes an n-type diffusion region 12a in a p-type epitaxial layer
10. Thus a depletion region is formed between the n-type region 12a
and the p-type epitaxial layer 10.
[0024] A silicide-blocking layer 16, which could be silicon
nitride, covers an active area between the trenches 18. Below the
trench 18 is a p-well 20 in the illustrative p-type structure. An
oxide layer 14, which may be called a pad oxide, may be formed
between the layer 16 and the region 12a.
[0025] While the present invention is illustrated in connection
with a photodiode in a p-type semiconductor structure, other
conventional devices that have trench isolation, such as
conventional transistors used in logic devices, could benefit from
the present invention as well. Other trench isolated photosensitive
device configurations can also be used. In addition, opposite
conductivity type devices could be used by simply inverting the
conductivity types of the diffusion 12a illustrated in FIG. 1.
[0026] The n-type region 12a does not span the trenches 18 and is
bounded on either side by p-type region 10. The p-type intervening
regions 22 between the trenches 18 and the region 12a act as buffer
regions to reduce the leakage current caused by the interface
states formed by the dry etched trench 18. This leakage current
produces a dark current in trench isolated photosensitive devices.
The width of the intervening regions 22 depends on the particular
characteristics of the device in question. The width of the regions
22 may be adjusted to sufficiently reduce the leakage current to
achieve desirable results.
[0027] Any technique may be used to define the region 12a. In one
conventional approach, the region 12a may be formed by the n-tip
implant used in forming conventional transistor lightly doped drain
structures. Thus prior to forming the layer 16, suitable masking
layers may be provided to define an opening to receive the n-tip
implant. Thereafter the implant may be activated and driven by a
high temperature anneal step or other activation techniques.
[0028] Thus the regions 22 in effect create a buffer around the
n-type diffusion region 12a of the photodiode because they are
formed between the region 12a and the trench 18. This reduces
leakage current arising from the depletion region which bounds the
p-n junction. In the case of a photosensitive device, reducing the
leakage current reduces the dark current experienced by the
resulting image sensor.
[0029] Another approach to overcoming the leakage created by the
trench isolation process, shown in FIG. 2, uses the p-well regions
20a which extend into the region 22a between the n-type region 12b
and the trench 18. Like the p-type regions 22 in the embodiment
shown in FIG. 1, the incursion of the p-well into the regions 22a
reduces leakage current between the depletion region and the
interface states created in the trench 18.
[0030] The p-well may extend into the region 22a between the trench
isolation and the diffusion 12b by suitable adjustments in the
p-well masking process and/or by increasing the drive applied to
the p-well implants. Other techniques could be used as well.
Essentially, the n-type diffusion region 12b could have spanned the
region between the trench regions 18, but instead it is masked off
so it is spaced from the trench regions 18. Through the use of the
p-well 20a, a p-type region provides the buffering described
above.
[0031] Another approach to overcoming the leakage problem, shown in
FIG. 3, is similar to the embodiments shown in FIGS. 1 and 2 but
intervening p-type tip regions 22b are formed between the n-type
diffusion 12c and the trenches 18. The diffusion 12c may be formed
the same way as a region 12a in FIG. 1. However additional masking
may be utilized to allow the p-type tip implant (also used, for
example, to form the p-minus regions of a graded junction
transistor) to be utilized to form p-minus or tip regions which
extend into the region between the diffusion 12c and the trench 18.
Again the regions 22b, like the regions 22a and 22 discussed
previously, prevent leakage current between the depletion regions
associated with the p-n junction and the trenches 18. It may also
be desirable to cause the p-wells 20b to extend closer together to
further isolate the depletion regions from the trenches 18.
[0032] The embodiments shown in FIGS. 1 through 3 are advantageous
in that they have lower leakage current since the depletion regions
are isolated from the trench. The buffer region 22 is still part of
the active diode. Thus electrons optically generated in the buffer
region diffuse into the p-n diode depletion region and contribute
to the photo current. These diodes therefore do not suffer a
reduction in quantum efficiency.
[0033] The width of the buffer region (W in the figures) is
determined independently for each diode with particular attention
being paid to the doping profiles. Thus W may be made up of the
widest depletion region of the p-type side, the trench depletion
region, the n-type lateral diffusion, the encroachment of the
trench due to processing, and an allotment for misalignment. There
is also a small depletion region around the trench due to dangling
bond and other defects in the trench boundary.
[0034] Referring now to FIG. 4, in another embodiment, the silicide
is not blocked over the p-type region 10 forming a silicide portion
28. The portion 28 does not require a significant amount of area. A
microlens (not shown) could be used to focus a light into the
center of the diode. The microlens may be formed as a deposited
layer which forms a droplet shape that acts like a lens. In this
case silicided portions 28 are formed on either side of the
blocking layer 16.
[0035] Referring to FIGS. 5 through 7, another embodiment in
accordance with the invention is similar to the previous
embodiments but includes an additional p-type region 30 between the
oxide layer 14, the n-type region 12b and the P-wells 20. The
p-type region 30 decreases dark current arising from leakage caused
by electron-hole pair generation at the depleted interface between
the oxide layer 14 and the p-wells 20.
[0036] The dark current may result from the electron-hole pair
generation at the top of the depleted surface and is dependent upon
the quality of the oxide 14 on silicon or the density of interface
states of the oxide on silicon. With this structure, the n-type
region 12b is buried within the p-type layers.
[0037] The p-type region 30 may be formed from a p-well, p-epi,
p-tip or any other p-type layer. Similarly, the layer 30 may be
used with the embodiment of FIGS. 1, 3 and 4 as well.
[0038] Referring to FIG. 6, metal contact to the n-type layer 12b
is used to apply reverse bias voltage to the n-type layer and to
collect the carriers generated by light. The metal contact 33 may
be made from the top as indicated in FIG. 6 or from the side as
indicated in FIG. 7. In each case, the metal contact 33 contacts an
n-type region 32 or 35 formed in the p-type region 30 or the
isolation region 18.
[0039] Referring now to FIG. 8, still another embodiment in
accordance with the invention is similar to the embodiment of FIG.
2 except that a thin polysilicon layer 36 is formed on top of a
gate oxide layer 38. The gate oxide layer 38 may be formed using
conventional gate oxide formation processes. The polysilicon
covered device may reduce the surface leakage, for example, by
protecting the underlying oxide from a plasma poly etch back or any
other plasma etch. The plasma etching of the oxide may cause
surface leakage. In addition, high quality gate oxide formation
processes may be used to reduce leakage.
[0040] For example, the gate oxide formation may involve forming a
sacrificial oxide layer. Oxide may be grown at a relatively low
temperature and then annealed at a higher temperature. The
polysilicon is thereafter deposited.
[0041] The silicide 40 on top of the poly layer 36 is blocked so
that the light can go through to the diode. By making the
polysilicon layer 36 sufficiently thin, the quantum efficiency of
the device may not be significantly reduced.
[0042] The devices shown in FIG. 8 may reduce leakage current which
may be occurring from the diode surface. Again the techniques
illustrated in FIG. 8 may be applied to other configurations
including those shown in FIGS. 1, 3 and 4.
[0043] A conventional photogate device 51, shown in FIG. 9,
includes a trench isolation region 50 on either side of an active
area which includes a depletion region 52. The photogate 54 is
arranged partially over the isolation region 50a and partially over
the depletion region 52. In the illustrated embodiment, the
substrate may be p-type material. A transfer gate 56 may be
positioned between the photogate 54 and one of the isolation
regions 50b and a contact 58 may be formed between the transfer
gate 56 and the isolation region 50b.
[0044] The potential well formed underneath the photogate 51
captures incident photoelectrons. However, thermally generated
carriers are also collected in the well, reducing the
signal-to-noise ratio and the dynamic range of the pixel.
[0045] The depletion region 52 in the prior art device shown in
FIG. 9 comes in contact with the isolation region 50a and the
substrate surface 59. Thus, higher carrier generation rates may be
developed increasing the number of thermally generated carriers and
decreasing the signal-to-noise ratio and dynamic range of the
pixel.
[0046] Referring now to FIG. 10, a p-type buffer region 57 may be
formed between the isolation region 50a and the depletion region
52. This p-type buffer region 57 buffers the depletion region 52
and decreases the number of thermally generated electrons. By
buffering the edges of the photogate with an additional P-type
area, the depletion region 52 does not come in contact with the
isolation 50a, thus reducing leakage current and improving
signal-to-noise ratio and dynamic range. Alternatively, the P-type
buffer region 57 may be formed using other techniques including, as
examples, forming a p-minus or p-tip buffer (see FIG. 3), or a
p-well buffer (see FIG. 2), or forming a p-plus diffusion.
[0047] Referring finally to FIG. 11, still another embodiment is
illustrated which is similar to the embodiment shown in FIG. 2
except that the p-well 20c is spaced away from the edges of the
n-type region 12b by the regions 22b which may be formed of p-type
epitaxial material. An increased impact ionization level may be
created by the juxtaposition of an n-type tip region 12b and the
p-well 20c in the embodiment shown in FIG. 2. The p-epitaxial layer
is lower in p-type concentration than the p-well. The p-epitaxial
regions 22b create a lower electric field decreasing the impact
ionization level. Also, the leakage current due to impact
ionization may be decreased. Thus, the higher electric field across
the depletion region that may lead to impact ionization and soft
breakdown under reverse bias voltages, may be decreased or
avoided.
[0048] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. For
example, it is also possible to form a buffer region by diffusing a
p-plus region into the area between the diffusion 12 and the trench
18. It is intended that the appended claims will cover all such
modifications and variations as fall within the true spirit and
scope of the present invention.
* * * * *