U.S. patent application number 09/813834 was filed with the patent office on 2001-08-30 for semiconductor device having sidewall spacers manifesting a self-aligned contact hole.
This patent application is currently assigned to LG Semicon Co. Ltd.. Invention is credited to Roh, Jae Sung, Yang, Woun S..
Application Number | 20010017423 09/813834 |
Document ID | / |
Family ID | 19491348 |
Filed Date | 2001-08-30 |
United States Patent
Application |
20010017423 |
Kind Code |
A1 |
Roh, Jae Sung ; et
al. |
August 30, 2001 |
Semiconductor device having sidewall spacers manifesting a
self-aligned contact hole
Abstract
A semiconductor device and a method for manufacturing the same
that forms a self-aligned contact hole between two gate lines. A
substrate is provided that has a first gate line formed thereon. An
insulator is formed on the first gate line and substrate. Then a
portion of the insulator and a portion of the first gate line is
selectively removed to split the first gate line into a second gate
line and a third gate line and to concurrently expose the
substrate. Thus, producing a self-aligned contact hole between the
second and third gate lines.
Inventors: |
Roh, Jae Sung; (Kyungki-do,
KR) ; Yang, Woun S.; (Chungcheongbuk-do, KR) |
Correspondence
Address: |
BIRCH STEWART KOLASCH & BIRCH
PO BOX 747
FALLS CHURCH
VA
22040-0747
US
|
Assignee: |
LG Semicon Co. Ltd.
|
Family ID: |
19491348 |
Appl. No.: |
09/813834 |
Filed: |
March 22, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09813834 |
Mar 22, 2001 |
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09459656 |
Dec 13, 1999 |
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09459656 |
Dec 13, 1999 |
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08931238 |
Sep 16, 1997 |
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6060346 |
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Current U.S.
Class: |
257/774 ;
257/E21.507; 257/E21.62 |
Current CPC
Class: |
H01L 21/76897 20130101;
H01L 21/76805 20130101; H01L 21/76831 20130101; H01L 21/823425
20130101 |
Class at
Publication: |
257/774 |
International
Class: |
H01L 023/48; H01L
023/52; H01L 029/40 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 27, 1996 |
KR |
73475/1996 |
Claims
What is claimed is:
1. A semiconductor device having a self-aligned contact hole, the
device comprising: a substrate; a first conductor structure and a
second conductor structure formed on the substrate; an insulator
structure formed on the first and second conductor structure and on
the substrate except over the substrate in a region between the
first and second conductor structures; and sidewall spacers, each
sidewall spacer being formed to abut against both a side of the
first or second conductor structures and a side of the insulator
structure, the sidewall spacers manifesting the self-aligned
contact hole in the region between the first and second conductor
structures.
2. The semiconductor device of claim 1, wherein the first and
second conductor structures are first and second gate structures,
respectively.
3. The semiconductor device of claim 1, wherein the first and
second conductor structures comprise: a gate oxide layer formed on
the substrate; a conductive layer formed on the gate oxide layer;
and a gate cap insulating layer formed on the conductive layer.
4. The semiconductor device of claim 1, further comprising: a
contact plug formed in the self-aligned contact hole.
5. An unsymmetrical semiconductor device using a self-aligned
contact hole, the device comprising: a substrate having impurity
regions formed therein; a first conductor structure and a second
conductor structure formed on the substrate except over the
substrate in a region between the first and second conductor
structures; first sidewall spacers, each first sidewall spacer
being formed to abut against both a side of the first or second
conductor structures and a side of an insulator structure, the
first sidewall spacers manifesting the self-aligned contact hole in
the region between the first and second conductor structures; and
second sidewall spacers formed on sides of the first and second
conductor structures opposite of the self-aligned contact hole.
6. The unsymmetrical semiconductor device of claim 5, wherein the
ion concentration of a first impurity region is different than the
ion concentration of a second impurity region.
7. The unsymmetrical semiconductor device of claim 5, further
comprising: a contact plug formed in the self-aligned contact hole,
the contact plug being in contact with the first sidewall spacers
and the first impurity region.
8. The unsymmetrical semiconductor device of claim 7, wherein the
contact plug is also in contact with a bit line.
9. The unsymmetrical semiconductor device of claim 7, wherein the
contact plug is not disposed directly above the first and second
conductor structures.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device and,
more particularly, to a semiconductor device having a self-aligned
contact hole and a method for manufacturing the same.
[0003] 2. Discussion of the Related Art
[0004] A general process of forming a self-aligned contact hole,
which can be easily and precisely made, does not require fitting a
mask using a location-fitting margin. Accordingly, high integration
can be achieved without utilizing a highly skilled process or
highly precise equipment to perform the process.
[0005] There are two conventional methods for forming a
self-aligned contact hole. In one method, selective etch rates are
used. In another method, which is a semi self-alignment method, a
contact hole is formed and then an oxide sidewall is formed.
[0006] A conventional method for manufacturing a semiconductor
device will be explained with reference to the accompanying
drawings.
[0007] FIGS. 1a to 1c are cross-sectional views showing a method
for manufacturing a semiconductor device according to one
conventional method and FIGS. 2a to 2c are cross-sectional views
showing a method for manufacturing a semiconductor device according
to another conventional method. FIG. 3 is a cross-sectional view
showing a structure of a semiconductor device manufactured
according to a conventional method, which illustrates problems
arising from manufacturing the semiconductor device according to a
conventional method.
[0008] Referring initially to FIG. 1a, an active region and a field
region are defined on a substrate 1 and then a field oxide layer is
formed on the field region. Next, an oxide layer, a polysilicon
layer, and a nitride layer are successively formed on the entire
surface of the substrate 1. Subsequently, a photoresist layer is
coated on the resultant surface and then selectively patterned.
With the patterned photoresist layer serving as a mask, the nitride
layer, the polysilicon layer, and the oxide layer are successively
etched to form a first and second gate structure 3a and 3b,
respectively. The first and second gate structures 3a and 3b
comprise a gate oxide layer 2, a gate electrode 3, and a gate cap
insulating layer 4. Thereafter, the remaining patterned photoresist
layer is removed.
[0009] With the first and second gate structures 3a and 3b serving
as a mask, lightly doped impurity ions are implanted into the
exposed surface of the substrate 1 thereby forming lightly doped
source and drain regions 5. Next, a nitride layer is deposited over
the substrate 1 and anisotropically etched to form sidewall spacers
6 on the sides of the first and second gate structures 3a and 3b,
respectively. With the first and second gate structures 3a and 3b
and the sidewall spacers 6 serving as a mask, heavily doped
impurity ions are implanted into the exposed surface of the
substrate 1 thereby forming a heavily doped source/drain region
7.
[0010] Referring to FIG. 1b, there is formed an interlayer
insulating layer 8 over the substrate 1. Then a photoresist layer
is formed on the interlayer insulating layer 8 and exposed and
developed to form the patterned photoresist layer 9.
[0011] Referring to FIG. 1c, with the patterned photoresist layer 9
serving as a mask, the interlayer insulating layer 8 is
anisotropically etched using a high selective etch rate of the
oxide and nitride layers until the surface of the substrate 1 is
exposed, thus forming a contact hole. The high selective etch rate
is described as the nitride or oxide layer being easily etched and
the polysilicon layer not being easily etched or vice-versa. Next,
on the entire surface of the substrate 1, there is formed a
conductive material such as polysilicon, aluminum, or tungsten that
are patterned to form a bit line 10.
[0012] Another conventional method for manufacturing a
semiconductor device will be explained with reference to FIGS.
2a-2c.
[0013] Referring initially to FIG. 2a, there are defined an active
region and a field region in the substrate 11. A field oxide layer
is formed on the field region. Then, a first oxide layer, a
polysilicon layer, and a second oxide layer are successively formed
on the entire surface of the substrate 11. Subsequently, a
photoresist layer is coated on the resultant surface and then
exposed and developed to form a patterned photoresist layer. With
the patterned photoresist layer serving as a mask, the first oxide
layer, the polysilicon layer, and the second oxide layer are
successively etched to form a first and second gate structure 13a
and 13b, respectively. The first and second gate structures 3a and
3b comprise a gate oxide layer 12, a gate electrode 13, and a gate
cap insulating layer 14 on a predetermined portion of the substrate
11. Thereafter, the remaining patterned photoresist layer is
removed.
[0014] With the first and second gate structures 13a and 13b
serving as a mask, lightly doped impurity ions are implanted into
the exposed surface of the substrate 11 thereby forming lightly
doped source and drain regions 15. Next, an oxide layer is formed
on the resultant surface and then anisotropically etched to form
sidewall spacers 16 on sides of the first and second gate
structures 13a and 13b. With the sidewall spacers 16 and first and
second gate structures 13a and 13b serving as a mask, heavily doped
impurity ions are implanted into the substrate 11 thereby forming a
heavily doped source/drain region 17.
[0015] Referring to FIG. 2b, on the resultant surface, there is
deposited an interlayer insulating layer 18 using a chemical vapor
deposition (CVD) method. Next, a photoresist layer is coated on the
resultant surface and then exposed and developed to form a
patterned photoresist layer 19.
[0016] Referring to FIG. 2c, with the patterned photoresist layer
19 serving as a mask, the interlayer insulating layer 18 is
anisotropically etched in between the first and second gate
structures 13a and 13b to expose the surface of the source/drain
region 17 thereby forming a contact hole. Then, an oxide layer is
formed on the resultant surface and then anisotropically etched to
form oxide sidewall spacers 20 on sides of the interlayer
insulating layer 8. Subsequently, a conductive material such as
polysilicon, aluminum, or tungsten is formed on the entire surface
and then patterned to form a bit line 21. In this case, the oxide
sidewall spacers 20 serve to insulate the gate electrode 13 from
the bit line 21.
[0017] Problems arising from semiconductor devices manufactured
according to the conventional methods will be explained with
reference to FIG. 3.
[0018] As shown in FIG. 3, when an alignment tolerance is beyond
the limit of a photolithography process, formation of a contact
hole is misaligned on a gate electrode 13. Consequently, a short
between the gate electrode 13 and the bit line 21 is generated even
after the oxide sidewall spacers 20 are formed.
[0019] Conventional methods for manufacturing a semiconductor
device have the following problems.
[0020] First, it is difficult to carry out an etch process over
materials such as a nitride and an oxide having a high selective
etch rate. If a selective etch rate is high, a polymer may be
generated that blocks a contact hole and stops the etch process.
Moreover, it is difficult to simplify the overall process.
[0021] Second, for a high density device, alignment tolerance
easily goes beyond the limit of a photolithography process that
causes misalignment when forming a contact hole. Because of
misalignment, a short between a gate electrode and a bit line is
generated that destroys the operability of a unit device.
SUMMARY OF THE INVENTION
[0022] Therefore, the present invention is directed to a
semiconductor device and a method for manufacturing the same that
substantially obviate one or more of problems due to limitations
and disadvantages of the related art.
[0023] An object of the present invention is to provide a
semiconductor device having a self-aligned contact hole and a
method for manufacturing the same.
[0024] Another object of the present invention is to provide a
semiconductor device having unsymmetrical source and drain regions
and a method for manufacturing the same.
[0025] To achieve these and other advantages and in accordance with
the purpose of the present invention, as embodied and broadly
described, there is provided a semiconductor device having a
self-aligned contact hole, the device comprising: a substrate; a
first conductor structure and a second conductor structure formed
on the substrate; an insulator structure formed on the first and
second conductor structure and on the substrate except over the
substrate in a region between the first and second conductor
structures; and sidewall spacers formed on a side of the first and
second conductor structures and on a side of the insulator
structure, the sidewall spacers defining the self-aligned contact
hole in the region between the first and second conductor
structures.
[0026] In another aspect of the invention, there is provided a
method for self-aligning a contact hole between two conductor
structures in a semiconductor device, the method comprising the
steps of: providing a substrate; forming a first conductor
structure on the substrate; forming an insulator structure on the
first conductor structure and substrate; and selectively removing a
portion of the insulator structure and a portion of the first
conductor structure to split the first conductor structure into a
second conductor structure and a third conductor structure and to
concurrently expose the substrate thereby producing a self-aligned
contact hole between the second and third conductor structures.
[0027] In another aspect of the present invention, there is
provided an unsymmetrical semiconductor device using a self-aligned
contact hole, the device comprising: a substrate having impurity
regions formed therein; a first conductor structure and a second
conductor structure formed on the substrate; an insulator structure
formed on the first and second conductor structures and on the
substrate except over the substrate in a region between the first
and second conductor structures; first sidewall spacers formed on a
side of the first and second conductor structures and on a side of
the insulator structure, the first sidewall spacers defining the
self-aligned contact hole in the region between the first and
second conductor structures; and second sidewall spacers formed on
sides of the first and second conductor structures opposite of the
self-aligned contact hole.
[0028] In still another aspect of the present invention, there is
provided a method for forming an unsymmetrical semiconductor device
using a precisely aligned contact hole, the method comprising the
steps of: providing a substrate; forming a first conductor
structure on the substrate; forming a first impurity region in the
semiconductor substrate at sides of the first conductor structure;
forming an insulator structure on the first conductor structure and
substrate; selectively removing a portion of the insulator
structure and a portion of the first conductor structure to split
the first conductor structure into a second and third conductor
structure and to concurrently expose the substrate thereby
producing a self-aligned contact hole between the second and third
conductor structures; and forming a second impurity region in the
self-aligned contact hole.
[0029] The invention being thus described, it will be obvious that
the same may be varied in many ways. Such variations are not to be
regarded as a departure from the spirit and scope of the invention,
and all such modifications as would be obvious to one skilled in
the art are intended to be included within the scope of the
following claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The present invention will become more fully understood from
the detailed description given hereinbelow and the accompanying
drawings which are given by way of illustration only, and thus are
not limitative of the present invention, and wherein
[0031] FIGS. 1a to 1c are cross-sectional views showing a
conventional method for manufacturing a semiconductor device;
[0032] FIGS. 2a to 2c are cross-sectional views showing another
conventional method for manufacturing a semiconductor device;
[0033] FIG. 3 is a cross-sectional view of a semiconductor device
manufactured according to a conventional method.
[0034] FIG. 4 is a plan view of a semiconductor device according to
the present invention;
[0035] FIG. 5 is a cross-sectional view across the line V-V in FIG.
4 according to the present invention; and
[0036] FIGS. 6a to 6d are cross-sectional views showing a method
for manufacturing a semiconductor device according to a preferred
embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0037] Reference will now be made in detail to the preferred
embodiments of the present invention, examples of which are
illustrated in FIGS. 4, 5, and 6a-6b.
[0038] Referring to FIGS. 4 and 5, the structure of the
semiconductor device according to the present invention will first
be described. In FIG. 4, the plan view of the semiconductor device
according to the present invention illustrates a first source/drain
region 35 and a second source/drain region 39. A gate line, which
had a width of X, is divided into a first gate line 43a and a
second gate line 43b having a width of X' and X", respectively. The
area 42 having an "X" drawn therethrough represents a contact plug
area wherein a contact plug is in contact with a second
source/drain region 39. The contact plug is also in contact with
the bit line 41.
[0039] In FIG. 5, the cross-sectional view of the semiconductor
device taken along the line V-V of FIG. 4 illustrates a field
region and an active region defined on a substrate 30 and a field
oxide layer 31 formed on the field region. A gate line 43 (see FIG.
6a) having a width of X is formed over the active region of the
substrate 30. The gate line 43, preferably, comprises a gate oxide
layer 32 formed on the substrate 30, a conductive line 33, which is
also a gate electrode, formed on the gate oxide layer 32, and a
gate cap insulator layer formed on the conductive line 33. The gate
line 43 is divided into two gate lines which are the first and
second gate lines 33a and 33b having widths of X' and X",
respectively, as shown in FIG. 5. The first gate line 43a comprises
a gate oxide layer 32 formed on the substrate 30, a conductive line
33a formed on the gate oxide layer 32, and a gate cap insulator
layer 34 formed on the conductive line 33a. The second gate line
43b has the same structure of the first gate line 43a having a
conductive line 33b instead of a conductive line 33a.
[0040] A contact hole is formed between the first and second gate
lines 43a and 43b and an interlayer insulating layer 37 is formed
on the first and second gate lines 43a and 43b and on the substrate
30.
[0041] Source and drain regions 35 are formed in the substrate 30
at outer sides of the first and second gate lines 43a and 43b. A
second source/drain region 39 is formed in the substrate 30 between
the first and second gate lines 43a and 43b. While gate insulating
sidewalls 36 are formed on the outer sides of the gate lines 43a
and 43b, oxide sidewall spacers 40 are formed on the inner sides of
the gate lines 43a and 43b and the interlayer insulating layer 37.
A contact plug 41a is formed in contact with the second
source/drain region 39. Structures on the field oxide layer 31
serve as "dummy" structures which do not serve any functional
purpose. The semiconductor devices according to the invention can
have transistors in field regions as well as active regions, and
are described in terms of structures in the field regions that
correspond to the structures in the active regions. In particular,
on the field oxide layers 31, structures corresponding to the gate
electrodes 33a and 33b, the gate cap insulators 34, the sidewall
spacers 36 and 40 and the plug 41a are formed. But because they are
formed on the field oxide layers 31, they represent inoperative
transistors. Forming these inoperative transistors in the field
regions is not necessary to practice the invention. But it has been
determined that forming the structures in the field regions as well
as in the active regions has advantages, from an
ease-of-manufacturing point of view. Thus, it is preferable but not
necessary to form the inoperative transistors in the field regions
at the same time that the corresponding transistors are formed in
the active regions.
[0042] A method for manufacturing a semiconductor device having the
aforementioned structure of FIG. 5 according to the present
invention will be explained with reference to FIGS. 6a-6d.
[0043] Referring initially to FIG. 6a, a field region and an active
region are defined in a substrate 30 and then a field oxide layer
is formed on the field region. Next, a first thin oxide layer is
formed on the entire surface of the substrate 30 using a thermal
oxidation process, and then a polysilicon layer and a second oxide
layer are successively formed on the first thin oxide layer. In
this case, a nitride layer can be deposited in place of the second
oxide layer.
[0044] Subsequently, the first oxide layer, the polysilicon layer,
and the second oxide layer are anisotropically etched to form a
gate line 43 that comprises a gate oxide layer 32, a conductive
line 33, and a gate cap insulating layer 34, which has a width of
X.
[0045] Referring to FIG. 6b, with the gate line 43 serving as a
mask, lightly doped impurity ions of either an N type or P types
are implanted into the substrate 30 thereby forming first source
and drain regions 35. Next, either of an oxide layer or a nitride
layer is formed and then anisotropically etched to form gate
insulating sidewalls 36 on the sides of the gate line 43.
[0046] Referring to FIG. 6c, an interlayer insulating layer 37 of
an oxide is formed on the entire surface of the substrate 30 using
a chemical vapor deposition (CVD) method, and then a photoresist
layer is coated on the entire surface and patterned using a contact
hole mask to form a patterned photoresist layer 38.
[0047] Subsequently, with the patterned photoresist layer 38
serving as a mask, the interlayer insulating layer 37 and the gate
line 33 are etched such that the gate line 33 is divided into two
gate lines. The two gate lines form a first gate line 43a having a
width of X' and a second gate line 43b having a width of X" (See
FIG. 4).
[0048] Referring to FIG. 6d, the remaining patterned photoresist
layer 38 is removed. Impurity ions are implanted into the exposed
surface of the substrate 30 between the first and second gate lines
43a and 43b, thus forming a second source/drain region 39. In this
case, the second source/drain region 39 has the same impurity ions
as the first source/drain regions 35. However, the concentration of
the first and second source/drain regions 35 and 39 are different.
The ions of a different concentration are implanted and a thermal
diffusion is carried out, forming an unsymmetrical device, (i.e.,
source and drain regions having different ion concentrations).
[0049] An oxide layer is then subsequently formed and
anisotropically etched to form oxide sidewall spacers 40 on inner
sides of the first and second gate lines 43a and 43b and on a side
surface of the interlayer insulating layer 37. Subsequently, a
conductive material is formed on the entire surface and then
patterned to form a contact plug 41a and a bit line 41 whereby the
bit line 41 connects with the contact plug 41a. Thus, the above
process completes the semiconductor device of the present
invention. Also, the conductive material for the bit line plug 41a
and the bit line 41 are preferably a polysilicon, aluminum, or
tungsten type material.
[0050] A method for manufacturing a semiconductor device of the
present invention has the following advantages.
[0051] First, since oxide sidewall spacers 40 are formed (after
dividing a gate line into two gate lines) on an inner side surface
between the two gate lines, a contact plug, which is in contact
with a bit line, is not formed over the gate lines avoiding a short
between the gate lines and a bit line. As a result, a device having
of good reliability can be manufactured.
[0052] Second, a mask to divide the gate line can be replaced with
a conventional mask to define a contact hole. Thus, the
manufacturing process becomes simplified, e.g., because the mask
inventory can be reduced by one mask.
[0053] Third, by splitting a single gate line structure in the
present invention, a contact hole is concurrently formed along with
the two gate lines, which permits a single masking step to replace
the separate masking steps needed to form the two gate lines and
for the contact hole.
[0054] Fourth, first source drain regions at both sides of the gate
lines and a second source/drain in between the divided gate lines
are formed, respectively, by ion implantation of different
concentrations, thereby forming an unsymmetrical device.
[0055] Fifth, a more precise contact hole is formed by dividing a
single gate line into two gate lines that avoid aligning a contact
hole between the two gate lines.
[0056] The invention being thus described, it will be obvious that
the same may be varied in many ways. Such variations are not to be
regarded as a departure from the spirit and scope of the invention,
and all such modifications as would be obvious to one skilled in
the art are intended to be included within the scope of the
following claims.
* * * * *