U.S. patent application number 09/225127 was filed with the patent office on 2001-08-16 for dual tox trench dram structures and process using v-groove.
Invention is credited to FURUKAWA, TOSHIHARU, GAMBINO, JEFFREY P., KIEWRA, EDWARD W., MANDELMAN, JACK A., RADENS, CARL J., TONTI, WILLIAM R., WEYBRIGHT, MARY E..
Application Number | 20010014481 09/225127 |
Document ID | / |
Family ID | 22843649 |
Filed Date | 2001-08-16 |
United States Patent
Application |
20010014481 |
Kind Code |
A1 |
FURUKAWA, TOSHIHARU ; et
al. |
August 16, 2001 |
DUAL TOX TRENCH DRAM STRUCTURES AND PROCESS USING V-GROOVE
Abstract
A structure and method for simultaneously forming array
structures and support structures on a substrate comprises forming
the array structures to have a V-groove, forming the support
structures to have a planar surface, and simultaneously forming a
first oxide in the V-groove and a second oxide in the planar
surface, wherein the first oxide is thicker than the second
oxide.
Inventors: |
FURUKAWA, TOSHIHARU; (ESSEX
JUNCTION, VT) ; GAMBINO, JEFFREY P.; (GAYLORDSVILLE,
CT) ; KIEWRA, EDWARD W.; (VERBANK, NY) ;
MANDELMAN, JACK A.; (STORMVILLE, NY) ; RADENS, CARL
J.; (LAGRANGEVILLE, NY) ; TONTI, WILLIAM R.;
(ESSEX JUNCTION, VT) ; WEYBRIGHT, MARY E.;
(PLEASANT VALLEY, NY) |
Correspondence
Address: |
MCGINN & GIBB, PLLC
8321 OLD COURTHOUSE ROAD
SUITE 200
VIENNA
VA
22182-3817
US
|
Family ID: |
22843649 |
Appl. No.: |
09/225127 |
Filed: |
January 4, 1999 |
Current U.S.
Class: |
438/1 ;
257/E21.655; 257/E21.66; 257/E27.091; 257/E27.092 |
Current CPC
Class: |
H01L 27/10829 20130101;
H01L 27/10876 20130101; H01L 27/10823 20130101; H01L 27/10894
20130101 |
Class at
Publication: |
438/1 |
International
Class: |
H01L 021/00 |
Claims
What is claimed is:
1. A method of simultaneously forming array structures and support
structures on a substrate, said method comprising: forming said
array structures to have a V-groove surface; forming said support
structures to have a planar surface; and simultaneously forming a
first oxide in said V-groove and a second oxide on said planar
surface, wherein said first oxide is thicker than said second
oxide.
2. The method in claim 1, wherein said V-groove has at least one
surface along a <111> crystal plane of said substrate and
said planar surface is along a <100> crystal plane of said
substrate.
3. The method in claim 1, wherein said forming of said V-groove
comprises performing a crystallographic preferential etch which
etches a <111> crystal plane of said substrate at a lower
rate than a <100> crystal plane of said substrate.
4. The method in claim 1, further comprising forming a shallow
trench isolation region for said active structures.
5. The method in claim 1, further comprising: forming a protective
layer above said substrate; patterning said protective layer to
define said active structures and storage structures; forming
conductors in said active structures and said storage structures;
and forming wordlines above said conductors, wherein said patterned
protective layer aligns said conductors and said wordlines.
6. The method in claim 5, wherein said forming of said wordlines
comprises: positioning a mask approximately over said active
structures and said storage structures; forming grooves for said
wordlines using said mask; and depositing a conductive wordline
material in said grooves, wherein said protective layer aligns at
least one side of said wordlines and said conductors.
7. The method in claim 1, further comprising: forming a protective
layer above said substrate; forming stripes in said protective
layer; and patterning said protective layer to alternately define
said active structures and storage structures along said stripes,
wherein said stripes align said active structures and said storage
structures.
8. The method in claim 1, further comprising: forming a protective
layer above said substrate; patterning said protective layer to
define said active structures and storage structures; forming
trenches for said storage structures in said substrate using said
patterned protective layer as a mask; forming storage conductors in
said trenches; forming a protective oxide layer over said storage
conductor; and 9 forming said V-groove of said active structures
using said patterned protective layer.
9. A method of simultaneously forming array structures and storage
structures on a substrate, said method comprising: forming a
protective layer above said substrate; patterning said protective
layer to define said active structures and said storage structures;
forming conductors in said active structures and said storage
structures; and forming wordlines above said conductors, wherein
said patterned protective layer aligns said conductors and said
wordlines.
10. The method in claim 9, wherein said forming of said wordlines
comprises: positioning a mask approximately over said active
structures and said storage structures; forming grooves for said
wordlines using said mask; and depositing a conductive wordline
material in said grooves, wherein said protective layer aligns at
least one side of said wordlines and said conductors.
11. The method in claim 9, further comprising: forming said array
structures to have a V-groove surface; forming support structures
to have a planar surface; and simultaneously forming a first oxide
in said V-groove and a second oxide on said planar surface, wherein
said first oxide is thicker than said second oxide.
12. The method in claim 11, wherein said V-groove has at least one
surface along a <111> crystal plane of said substrate and
said planar surface is along a <100> crystal plane of said
substrate.
13. The method in claim 11, wherein said forming of said V-groove
comprises performing a crystallographic preferential etch which
etches a <111> crystal plane of said substrate at a different
rate than a <100> crystal plane of said substrate.
14. The method in claim 11, further comprising forming a shallow
trench isolation region for said active structures.
15. The method in claim 11, further comprising: forming a
protective layer above said substrate; patterning said protective
layer to define said active structures and said storage structures;
forming trenches for said storage structures in said substrate
using said patterned protective layer as a mask; forming storage
conductors in said trenches; forming a protective oxide layer over
said storage conductor; and forming said V-groove of said active
structures using said patterned protective layer.
16. The method in claim 9, further comprising: forming a protective
layer above said substrate; forming stripes in said protective
layer; and patterning said protective layer to alternately define
said active structures and said storage structures along said
stripes, wherein said stripes align said active structures and said
storage structures.
17. A method of simultaneously forming array structures and storage
structures on a substrate, said method comprising: forming a
protective layer above said substrate; forming stripes in said
protective layer; and patterning said protective layer to
alternately define said active structures and said storage
structures along said stripes, wherein said stripes align said
active structures and said storage structures.
18. The method in claim 17, further comprising: forming conductors
in said active structures and said storage structures; and forming
wordlines above said conductors, wherein said patterned protective
layer aligns said conductors and said wordlines.
19. The method in claim 18, wherein said forming of said wordlines
comprises: positioning a mask approximately over said active
structures and said storage structures; forming grooves for said
wordlines using said mask; and depositing a conductive wordline
material in said grooves, wherein said protective layer aligns at
least one side of said wordlines and said conductors.
20. The method in claim 17, further comprising: forming said array
structures to have a V-groove surface; forming support structures
to have a planar surface; and simultaneously forming a first oxide
in said V-groove and a second oxide on said planar surface, wherein
said first oxide is thicker than said second oxide.
21. The method in claim 20, wherein said V-groove has at least one
surface along a <111> crystal plane of said substrate and
said planar surface is along a <100> crystal plane of said
substrate.
22. The method in claim 20, wherein said forming of said V-groove
comprises performing a crystallographic preferential etch which
etches a <111> crystal plane of said substrate at a lower
rate than a <100> crystal plane of said substrate.
23. The method in claim 20, further comprising forming a shallow
trench isolation region for said active structures.
24. The method in claim 20, further comprising: forming trenches
for said storage structures in said substrate using said patterned
protective layer as a mask; forming storage conductors in said
trenches; forming a protective oxide layer over said storage
conductor; and forming said V-groove of said active structures
using said patterned protective layer.
25. A semiconductor device comprising: a substrate having V-grooves
and planar surface; array structures in said V-grooves; support
structures on said planar surface; a first oxide in said V-grooves;
and a second oxide on said planar surface, wherein said first oxide
is thicker than said second oxide.
26. The semiconductor device in claim 25, wherein said V-grooves
have at least one surface along a <111> crystal plane of said
substrate and said planar surface is along a <100> crystal
plane of said substrate.
27. The semiconductor device in claim 25, further comprising a
shallow trench isolation region for said active structures.
28. The semiconductor device in claim 25, further comprising: a
protective layer above said substrate defining said active
structures and storage structures; conductors in said active
structures and said storage structures; and wordlines above said
conductors, wherein said patterned protective layer aligns said
conductors and said wordlines.
29. The semiconductor device in claim 28, wherein said protective
layer aligns at least one side of said wordlines and said
conductors.
30. The semiconductor device in claim 25, further comprising: a
protective layer above said substrate having stripes, said active
structures and storage structures alternating along said stripes,
wherein said stripes align said active structures and said storage
structures.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention generally relates metal oxide
semiconductors (MOS) and more specifically to a V-groove metal
oxide semiconductor (VMOS) structure having a shallow trench
isolation (STI) region.
[0003] 2. Description of the Related Art
[0004] Metal oxide semiconductor field effect transistors (MOSFETs)
are typically formed to have active arrays of devices such as in
dynamic random access memories (DRAM), read only memories (ROMs),
electrically programable read only memories (EPROMs) and other
similar devices. In addition, such structures will include support
MOSFETs such as drivers, decoders, I/O circuitry and other similar
devices. The array MOSFETs require a relatively thick gate oxide
when compared to the support MOSFETs.
[0005] A relatively thick gate oxide layer increases the maximum
wordline boost voltage which can be applied to the array MOSFETs.
To the contrary, the support MOSFETs exhibit significantly
increased performance as the gate oxide thickness decreases.
[0006] Therefore, decreasing the gate oxide thickness increases the
performance of the support MOSFETs but decreases charge transfer of
efficiency (and degrades the performance) of the array MOSFETs.
Therefore, the conventional structures suffer from an inherent
trade-off between the gate oxide thickness required for the array
MOSFETs and the gate oxide thickness required for the support
MOSFETs.
[0007] Conventional solutions to the foregoing trade-off problem
include a dual gate oxide process where the gate oxide for the
array MOSFETs is formed separately from the gate oxide for the
support MOSFETs. However, such processing substantially increases
the cost of producing the device and further increases the chance
for defects. Therefore, there is a need for a single process which
selectively forms the gate oxide differently for different
devices.
SUMMARY OF THE INVENTION
[0008] It is, therefore, an object of the present invention to
provide a structure and method for simultaneously forming array
structures and support structures on a substrate, the method
comprising forming the array structures to have a V-groove, forming
the support structures to have a planar surface, and simultaneously
forming a first oxide in the V-groove and a second oxide in the
planar surface, wherein the first oxide is thicker than the second
oxide.
[0009] The V-groove has at least one surface along a <111>
crystal plane of the substrate and the planar surface has a surface
along a <100> crystal plane of the substrate. The forming of
the V-groove comprises performing a crystallographic preferential
etch which etches a <111> crystal plane of the substrate at a
different rate than a <100> crystal plane of the
substrate.
[0010] The method may further comprise forming a shallow trench
isolation region for the active structures, forming a protective
layer above the substrate, patterning the protective layer to
define the active structures and storage structures, forming
conductors in the active structures and the storage structures, and
forming wordlines above the conductors, wherein the patterned
protective layer aligns the conductors and the wordlines. The
forming of the wordlines comprises positioning a mask approximately
over the active structures and the storage structures, forming
grooves for the wordlines using the mask, and depositing a
conductive wordline material in the grooves, wherein the protective
layer aligns at least one side of the wordlines and the
conductors.
[0011] The method may further comprise forming a protective layer
above the substrate, forming stripes in the protective layer, and
patterning the protective layer to alternately define the active
structures and storage structures along the stripes, wherein the
stripes align the active structures and the storage structures. The
method may further comprise forming a protective layer above the
substrate, patterning the protective layer to define the active
structures and storage structures, forming trenches for the storage
structures in the substrate using the patterned protective layer as
a mask, forming storage conductors in the trenches, forming a
protective oxide layer over the storage conductor, and forming the
V-groove of the active structures using the patterned protective
layer.
[0012] Additionally, the invention includes a semiconductor device
comprising a substrate having V-grooves and planar surfaces, array
structures in the V-grooves, support structures in the planar
surfaces, a first oxide in the V-grooves and a second oxide in the
planar surfaces, wherein the first oxide is thicker than the second
oxide.
[0013] The V-grooves have at least one surface along a <111>
crystal plane of the substrate and the planar surface has a surface
along a <100> crystal plane of the substrate. The invention
may further comprise a shallow trench isolation region for the
active structures.
[0014] Also, the invention may include a protective layer above the
substrate having a protective layer defining the active structures
and storage structures, conductors in the active structures and the
storage structures; and wordlines above the conductors, wherein the
patterned protective layer aligns the conductors and the wordlines.
The protective layer aligns at least one side of the wordlines and
the conductors.
[0015] The invention may further comprise a protective layer above
the substrate having stripes, the active structures and storage
structures alternating along the stripes, wherein the stripes align
the active structures and the storage structures.
[0016] The invention takes advantage of a selective oxide growth
ability and grows thicker gate oxides of the array MOSFETs on
surfaces in V-grooves <111>, while thinner support MOSFET
oxides are simultaneously grown on the top <100> surface.
More specifically, with the invention, the gate oxide of the array
MOSFETs are grown on <111> surfaces in V-grooves, while the
support MOSFET oxides are grown conventionally on the top
<100> surface. Therefore, the invention can selectively form
relatively thin oxide layers for the support MOSFETs and
simultaneously form thicker gate oxide layers for the array
MOSFETs, thereby increasing device performance and decreasing
defects.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The foregoing and other objects, aspects and advantages will
be better understood from the following detailed description of a
preferred embodiment of the invention with reference to the
drawings, in which:
[0018] FIG. 1 is a cross-sectional view of a semiconductor device
according to the invention;
[0019] FIG. 2 is a cross-sectional view of a semiconductor device
according to the invention;
[0020] FIG. 3 is a top view of a semiconductor device according to
the invention;
[0021] FIG. 4 is a top view of a semiconductor device according to
the invention;
[0022] FIG. 5 is a cross-sectional view of a semiconductor device
according to the invention;
[0023] FIGS. 6A-6C are a cross-sectional views of a semiconductor
device according to the invention;
[0024] FIG. 7 is a top view of a semiconductor device according to
the invention;
[0025] FIG. 8 is a cross-sectional view of a semiconductor device
according to the invention;
[0026] FIG. 9 is a top view of a semiconductor device according to
the invention;
[0027] FIGS. 10A-1OB are top views of a semiconductor device
according to the invention;
[0028] FIGS. 11A-11B are top views of a semiconductor device
according to the invention;
[0029] FIGS. 12A-12B are cross-sectional views of a semiconductor
device according to the invention;
[0030] FIGS. 13A-13E are cross-sectional views of a semiconductor
device according to the invention;
[0031] FIG. 14 is a top view of a semiconductor device according to
the invention;
[0032] FIG. 15 is a top view of a semiconductor device according to
the invention;
[0033] FIG. 16 is a top view of a semiconductor device according to
the invention;
[0034] FIG. 17 is a cross-sectional view of a semiconductor device
according to the invention;
[0035] FIG. 18 is a cross-sectional view of a semiconductor device
according to the invention; and
[0036] FIG. 19 is a perspective view of planes of a crystal.
DETAILED DESCRIPTION OF REFERRED EMBODIMENTS OF THE INVENTION
[0037] Oxides grown on silicon are approximately 50%-70% thicker on
surfaces aligned with the <111> crystal plane relative to the
<100> crystal plane depending on oxidation conditions. FIG.
19 illustrates a representative crystal and the <100>,
<110> and <111> planes.
[0038] The invention takes advantage of this selective growth
ability and grows the thicker gate oxide of the array MOSFETs on
surfaces in V-grooves <111>, while the thinner support MOSFET
oxides are simultaneously grown on the top <100> surface.
More specifically, with the invention, the gate oxide of the array
MOSFETs are grown on <111> surfaces in V-grooves, while the
support MOSFET oxides are grown conventionally on the top
<100> surface.
[0039] Therefore, the invention can selectively form relatively
thin oxide layers for the support MOSFETs and simultaneously form
thicker gate oxide layers for the array MOSFETs. For example, an
oxide having a 6 nm thickness (Tox) can be formed for the array
MOSFETs, which is suitable for gate boost voltages up to 3.3 V, and
an oxide having a 3.5 nm thickness, for the support devices, can be
formed to provide enhanced performance.
[0040] Various crystallographic preferential etches for silicon are
capable of reliably forming square based pyramidal pits having
<111> surfaces in a <100> surface of a wafer. For
example, a KOH (potassium hydroxide) etch has a <100> to
<111> etch rate ratio of 400:1 and is maskable with
Si.sub.3N.sub.4 or SiO.sub.2. EDA (Ethylene Diamine Pyrocatechol)
has a <100> to <111> etch rate ratio of 35:1 and is
more easily masked with Si.sub.3N.sub.4 or SiO.sub.2 than KOH.
[0041] Referring now to the drawings, and more particularly to FIG.
1, the invention includes a silicon wafer 10 having a customary pad
structure. The pad structure includes, for example, a thin thermal
pad oxide layer 11 (comprising, for example, silicon dioxide,
silicon oxynitride or other similar dielectric materials) and a
thick silicon nitride pad layer 12. Such structures are formed
using conventional processes well known to those ordinarily skilled
in the art such as sequential chemical vapor deposition (CVD),
sputtering, and other methods. An oxide layer 13 (such as silicon
dioxide, silicon oxynitride or other similar dielectric materials)
and a nitride layer 14 are formed over the nitride pad 12 again,
using similar well-known conventional processes. Stripes (e.g.,
openings) 15 are formed through the nitride 14, oxide 13, pad
nitride 12 and pad oxide 11 layers down to the silicon substrate 10
using conventional removal processes such as lithography, and
reactive ion etching (RIE).
[0042] As shown in FIG. 2, an oxide 20 (such as the oxides
mentioned above) is deposited in the stripes 15 between the pad
layers, again, using well-known techniques such as chemical vapor
deposition and planarization processes. FIG. 3 is a plan (e.g.,
top) view of the oxide 20 stripes between the top nitride layer
14.
[0043] FIG. 4 illustrates a photoresist 40 is deposited on the pad
layers 20. The photoresist 40 is formed to have openings 41 where
the oxide 20 is exposed (the longer sections of the oxide layers 20
are illustrated for reference only and would not otherwise appear
through the photoresist 40 from the top view shown in FIG. 4). FIG.
5 is a cross-sectional view of the structure shown in FIG. 4 along
line A-A and illustrates the opening 41 in the photoresist 40 above
the oxide stripe 20. The opening is wider than the stripe to assure
that, even with misalignment, the entire width of the oxide stripe
is exposed without the opening overlapping onto an adjacent
stripe.
[0044] Conventional reactive ion etching is used to form a deep
trench 62 in the silicon substrate 10. In the course of etching the
deep trench the photoresist (40) and nitride layer (14) are
removed. The trench 62 is lined with a storage node dielectric
layer 61. Then, the trench is partially filled with a first layer
of conductive material 60 which is preferably polysilicon, but
could also comprise other conductive materials. Similarly, the
formation of the first layer of conductive material 60 includes a
low-pressure chemical vapor deposition (LPCVD) of polysilicon,
anisotropic etching of the conductive fill 60, planarization and
recessing. The exposed portion of the dielectric 61 from the upper
portion of the trench is removed with a dry isotropic etch.
Preferably, the first layer of conductive material 60 fills
approximately 85% of the deep trench 62.
[0045] A collar oxide 63 is formed by thermal oxidation of the
exposed silicon, along the walls of the trench 62, and on the top
surface of the first layer of conductive material 60. In an
alternative embodiment, the collar oxide 63 can be formed by
deposition of a CVD oxide layer followed by a reactive ion etch
(RIE).
[0046] As shown in FIG. 6B, the collar oxide 63 is etched by, for
example an anisotropic dry reactive ion etch (RIE). Such an RIE
could use a mixture of gases which may include some portions of
C.sub.3F.sub.8, C.sub.2F.sub.6, He, CHF.sub.3, Ar, O.sub.2,
C.sub.4F.sub.8, and CO. The anisotropic dry etch, or sidewall
spacer etch, removes material in a vertical direction at a high
rate, but removes material in the horizontal direction at a
relatively low rate. Thus, the collar oxide 63 remains only on the
walls of the trench 62 as shown in FIG. 6B.
[0047] As shown in FIG. 6C, the remainder of the trench 60 is
completely filled with a second level of conductive material 64
which is planarized to the top of the oxide layers 13, 20. Again,
the second level of conductive material 64 could comprise
polysilicon, or other similar conductive material. The first
conductive material 60 may or may not be the same as the second
level of conductive material 64.
[0048] FIG. 7 shows a plan view of the deep trench 62 filled with
polysilicon 64 (where the cross-sectional view illustrated in FIG.
6C appears in FIG. 7 along line A-A), the top of the oxide stripes
20 and the top of the oxide layers 13.
[0049] As shown in FIG. 8, the oxide layers 13, 20 are removed
using an etch which is selective to oxide and which does not etch
silicon or silicon nitride. For example, such a selective etch
could comprise a wet or dry fluorine based etch. The selective etch
planarizes the top of the nitride pad 12 and removes the oxide
stripes 20 leaving the stripes 15 empty again (as shown above in
FIG. 1). Tungsten 81 is then deposited in the stripes 15 and
planarized. The tungsten 81 serves as a "placeholder" for the later
formed gate conductor material, as discussed in greater detail
below.
[0050] The upper level of the polysilicon 64 is selectively etched
down to at least the top of the collar oxide 63, using an etch
which etches polysilicon at a substantially faster rate than it
etches nitride or tungsten. For example, such an etch could include
a dry HBr (Hydrogen Bromide) etch. As discussed above, other
conductive materials may be used in place of the polysilicon 64
and, as would be known by one ordinarily skilled in the art given
this disclosure, other selective etches may be used depending upon
the conductive material deposited in the deep trench 62.
Additionally, other "placeholder" materials can be used in place of
the tungsten 81, such as Ge, Mo, which can be etched using, for
example, a H.sub.2O.sub.2 (Hydrogen Peroxide) solution.
[0051] The remaining polysilicon material 64 is then covered with
an oxide cap 80 using, for example, CVD of silicon dioxide
deposition and planarization. The oxide 80 protects the deep trench
62 (e.g., storage trench) during the subsequent V-groove etch, as
discussed below.
[0052] Next, the tungsten placeholders 81 are etched (again,
selectively to the oxide cap 80 and the nitride layer 12) down to
the silicon 10 surface using H.sub.2O.sub.2 (Hydrogen Peroxide)
which can be a dry etch.
[0053] The exposed crystalline silicon surface is etched with a
crystallographic preferential etch such as KOH or EDA (Ethylene
Diamine Pyrocatechol). The crystallographic preferential etch
etches silicon on the <100> surface much faster than on the
<111> surface. This results in the formation of
V-grooves.
[0054] The V-grooves 90 comprise rectangular based prismatic pits
in the silicon 10. The walls of the V-grooves lie in the
<111> crystal plane of the silicon 10. As discussed above,
oxides grown on silicon are approximately 50%-70% thicker on
surfaces aligned with the <111> crystal plane relative to the
<100> crystal plane depending on oxidation conditions.
[0055] Immediately following the gate oxidation, it is preferable
to perform a rapid thermal anneal (1000.degree. C.-1100.degree. C.
for 15-30 seconds) to partially reflow the gate oxide in the
V-groove. This reflow will thicken the oxide slightly at the bottom
of the groove, improving reliability.
[0056] FIG. 10A illustrates an oxide (e.g., silicon dioxide,
silicon oxynitride, etc.) layer 101 formed within the V-groove 90
which will serve as the gate dielectric of the array MOSFET. To the
contrary, FIG. 10B illustrates an opening 102 for a support device
(such as the support MOSFET devices, discussed above) which has a
conventional planar surface which lies within the <100> plane
of the silicon and which, when oxidized, forms a substantially
thinner oxide layer 103.
[0057] The gate conductor material 112, 113 (e.g., polysilicon,
metal or other conductor) is then damascened over the oxide layers
101, 103 and planarized (again, using techniques well known to
those ordinarily skilled in the art such as chemical mechanical
polishing "CMP"), as illustrated in FIGS. 11A and 11B.
[0058] FIG. 12A is a cross-sectional view of the structure shown in
FIG. 11A along line A-A. FIG. 12A illustrates the V-groove 90, the
thick gate conductor oxide 101 and the gate conductor material 112,
discussed above. Similarly, FIG. 12B is a cross-sectional view of
the structure shown in FIG. 11B along line B-B. FIG. 12B shows the
planar surface 102, the thin gate conductor oxide 103 and the gate
conductor material 113, discussed above.
[0059] An etch which removes oxides at a much faster rate than it
removes the gate conductor or nitride is applied to the structure
and removes the oxide cap 80 and a portion of the oxide collar 63,
as shown in FIG. 13A. For example, a suitable etch may include any
one of the well known dry etches commonly practiced for oxide
collar formation, such as CHF.sub.3+He+O.sub.2. The recess formed
by the foregoing selective etch is filled with additional
conductive material 131 (preferably polysilicon) which is added to
the previous conductive material 64, as shown in FIG. 13B. This
process also forms a conductive strap 134 using processes
well-known to those ordinarily skilled in the art. The conductive
material 131 can be the same material as conductive material 64 or
can be a different material depending upon the specific
application. The conductive materials 64, 131 will be referred to
hereinafter simply as conductive material 64.
[0060] A protective mask 133 is formed over the gate conductor 112
using common techniques (such as lithographic masking techniques)
and the conductive material in the trench 64 is etched to the top
of the silicon 10, as shown in FIG. 13C. Subsequently, an oxide cap
132 is deposited and planarized (again using common techniques,
discussed above), as shown in FIG. 13C.
[0061] An etch which removes the gate conductor material at a much
faster rate than it removes oxide or nitride materials is applied
to selectively remove a portion of the gate conductor 112, as shown
in FIG. 13D. For example, a suitable etch may include any one of
the well known dry etches commonly practiced for oxide collar
formation, such as CHF.sub.3+He+O.sub.2. An oxide cap 136 is formed
in the opening formed by the foregoing selective etch and the oxide
is planarized to the top of the nitride pad (again, using well
known techniques, discussed above), as shown in FIG. 13D.
Subsequently, an active area mask 135 is formed (again using common
masking techniques, discussed above) to define the active areas of
the array, as shown in FIG. 13D.
[0062] Common anisotropic etch processes, are used to form a
shallow trench isolation (STI) recess. For example, first the
portion of nitride pad 12 and oxide pad 11 not protected by the
active area mask 135 and the exposed portion of the oxide cap 132
are removed down to the silicon 10 and polysilicon 64. Then a
silicon etch is used to recess the silicon 10 and polysilicon 64 to
the desired isolation depth. Anisotropic etches are used in
conjunction with the active area mask 135 to remove portions of the
nitride pad 12 and remove portions of the deep trench structure 62,
as shown in FIG. 13E. The mask 135 is then removed. The recess
formed by the active area mask etching is preferably filled with
tetraethylorthosilicate (TEOS) or silane or HDP oxide to form
shallow trench isolation region 137 over the active area of the
array, as shown in FIG. 13E.
[0063] FIG. 14 illustrates a top view of the structure shown in
FIG. 13E. The cross-sectional view shown in FIG. 13E appears along
line A-A in FIG. 14. FIG. 14 illustrates the shallow trench
isolation regions 137 as well as the deep trench area 62 and gate
conductor the area 112.
[0064] FIG. 15 illustrates a photoresist 150 covering the structure
illustrated in FIG. 14. The photoresist includes openings 151
exposing portions of the planarized structure below, which includes
nitride areas, an oxide capping the gate and deep trench, and the
shallow trench isolation region 137.
[0065] The structure shown in FIG. 15 is subjected to a selective
etch which etches oxide materials at a much faster rate than it
etches nitride or polysilicon materials. This etch forms openings
into which a conductive material (such as tungsten or any
conductive material such as those discussed above) is deposited,
planarized and recessed (e.g. damascened) to form wiring patterns
such as word lines (WL) 160, 161, as shown in FIGS. 16 and 17.
[0066] More specifically, FIGS. 16 and 17 illustrate wordlines 160,
161 over the V-groove gate conductors 112 and over the deep trench
structures 62. After the wordlines 160, 161 are formed, an oxide
170 (such as any of the oxides discussed above) is deposited in the
cavity over the conductive layers and is planarized to the top of
the nitride cap 12.
[0067] The openings 151 in the photoresist 150, shown in FIG. 15
are intentionally shown misaligned with the edges of the deep
trench structures 62 and the gate conductors 112 to illustrate an
advantage of the invention. As shown in FIG. 16, the misalignment
of the openings 151 causes the wordlines 160, 161 to be misaligned.
However, the presence of the nitride pad 12 causes the wordlines to
be self-aligned with the gate conductor 112 and with the deep
trench structure 62 as shown in FIG. 17. Therefore, the invention
compensates for misalignment of the wordlines and allows for the
subsequent formation of a bitline diffusion contact which may be
self-registered to the edge of the gate conductor. The "borderless"
bitline contacts results in a dense memory cell layout.
[0068] As shown in FIG. 18, the nitride pad is removed by a
selective etch process, such as hot phosphoric acid, exposing the
silicon surface 10. Source and drain regions 181 are formed by
implanting N-type dopants (such as phosphorus arsenic, etc.) for
the array and support NFETs to complete the metal oxide
semiconductor (MOS) device 182. A P+ source and drain dopant is
implanted for the PFETs in the supports. The source and drain
regions 181 are self-aligned by the oxide cap 170. An oxide 180 is
deposited over the structure and is selectively removed from the
horizontal surfaces (using, for example reactive ion etching) to
form the sidewalls spacers 180.
[0069] Therefore, as discussed above, the invention utilizes
V-groove metal oxide semiconductor (VMOS) devices 108 in a shallow
trench isolation structure. The V-groove allows simultaneous
formation of a thick oxide layer 101 (for the array) and a thin
oxide layer 103 (for the support devices). Thus, the invention
allows adequate boost voltage on the gate (wordline) of the array
MOSFET, while maintaining gate oxide reliability, and good support
device performance.
[0070] Further with the invention, the wordlines 160, 161 are
borderless (e.g., self-aligned) to the VMOS gate conductor 112 and
the deep trench structure 62 (because of the action of the nitride
pad 12), even if the mask for the wordlines it is misaligned. Also,
the stripes 15 of the invention allow adjacent VMOS devices 182 and
deep trench structures 62 to be aligned with one another.
[0071] Additionally, the oxide shield 80, 63 (FIG. 8) protects the
deep trench structure 62 while forming the V-groove 90 for the gate
conductor 112, which reduces defects and increases yield when
compared to conventional structures and processes.
[0072] While the invention has been described in terms of preferred
embodiments, those skilled in the art will recognize that the
invention can be practiced with modification within the spirit and
scope of the appended claims.
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