U.S. patent application number 09/799917 was filed with the patent office on 2001-08-02 for floating gate method and device.
Invention is credited to Chang, A.J., Sung, Kuo-Tung.
Application Number | 20010010960 09/799917 |
Document ID | / |
Family ID | 22148695 |
Filed Date | 2001-08-02 |
United States Patent
Application |
20010010960 |
Kind Code |
A1 |
Chang, A.J. ; et
al. |
August 2, 2001 |
Floating gate method and device
Abstract
The present invention provides a novel integrated circuit
device, which has a flash memory cell. The flash memory cell (100)
has a tunnel dielectric layer (113) overlying a surface of a
semiconductor substrate. A floating gate layer (107) is defined
overlying the tunnel dielectric layer. The gate layer has an edge
defined thereon, where a sidewall spacer (108) extends along and on
the edge. The sidewall spacer includes a first portion defined
adjacent to the edge and a second portion extending from the first
portion to a region substantially outside the edge. The combination
of the sidewall spacer and the gate layer provide a novel surface
for increasing gate coupling ratio.
Inventors: |
Chang, A.J.; (Hsinchu,
TW) ; Sung, Kuo-Tung; (Hsinchu, TW) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Family ID: |
22148695 |
Appl. No.: |
09/799917 |
Filed: |
March 5, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09799917 |
Mar 5, 2001 |
|
|
|
09079140 |
May 14, 1998 |
|
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Current U.S.
Class: |
438/264 ;
257/E21.209; 257/E21.69; 257/E27.103; 257/E29.129 |
Current CPC
Class: |
H01L 27/11521 20130101;
H01L 29/42324 20130101; H01L 27/11524 20130101; H01L 29/40114
20190801; H01L 27/115 20130101 |
Class at
Publication: |
438/264 |
International
Class: |
H01L 021/336 |
Claims
What is claimed is:
1. A method for forming an integrated circuit device, said
integrated circuit comprising a flash memory cell, said method
comprising: forming a tunnel dielectric layer overlying a surface
of a semiconductor substrate; forming a floating gate layer
overlying the tunnel dielectric layer, the gate layer having an
edge defined thereon; and forming a sidewall spacer extending along
and on the edge and extending beyond the edge, the sidewall spacer
comprising a first portion defined adjacent to the edge and a
second portion extending from the first portion to a region
substantially outside the edge.
2. The method of claim 1 wherein the integrated circuit device is a
flash EEPROM device.
3. The method of claim 1 wherein the floating gate layer comprises
polysilicon.
4. The method of claim 1 wherein the tunnel dielectric layer
comprises oxide.
5. The method of claim 1 wherein the sidewall spacer comprises
polysilicon.
6. The method of claim 1 wherein the sidewall spacer is made of
substantially the same material as the floating gate layer.
7. The method of claim 1 wherein the steps of forming the floating
gate layer and the sidewall spacer comprises: forming a first
polysilicon layer overlying the tunnel dielectric layer; forming an
oxide layer overlying the first polysilicon layer; patterning the
first polysilicon layer and the oxide layer to define the floating
gate layer having the edge, said floating gate layer having a
patterned layer of oxide thereon; forming a second polysilicon
layer overlying the floating gate layer, the edge, and the
patterned oxide; removing horizontal portions of the second
polysilicon layer while leaving vertical portions of the
polysilicon layer intact to define the sidewall spacer on the edge
and an edge portion of the patterned oxide; and selectively
removing the patterned oxide leaving the first portion of the
sidewall spacer defined adjacent to the edge and the second portion
extending from the first portion to the region substantially
outside the edge.
8. The method of claim 1 wherein the sidewall is in electrical
contact with the floating gate layer.
9. The method of claim 1 further comprising a step of forming a
control gate layer overlying the floating gate layer and the
sidewall.
10. An integrated circuit device, said integrated circuit
comprising a flash memory cell, said flash memory cell comprising:
a tunnel dielectric layer overlying a surface of a semiconductor
substrate; a floating gate layer overlying the tunnel dielectric
layer, the floating gate layer having an edge defined thereon; and
a sidewall spacer extending along and on the edge and extending
beyond the edge, the sidewall spacer comprising a first portion
defined adjacent to the edge and a second portion extending from
the first portion to a region substantially outside the edge.
11. The device of claim 10 wherein the integrated circuit device is
a flash EEPROM device.
12. The device of claim 10 wherein the floating gate layer
comprises polysilicon.
13. The device of claim 10 wherein the tunnel dielectric layer
comprises oxide.
14. The device of claim 10 wherein the sidewall spacer comprises
polysilicon.
15. The device of claim 10 wherein the sidewall spacer is
substantially the same material as the floating gate layer.
16. The device of claim 10 wherein the sidewall is in electrical
contact with the floating gate layer.
17. The device of claim 10 further comprising a control gate layer
overlying the floating gate layer and the sidewall.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to the manufacture of
semiconductor integrated circuits. More particularly, the invention
is illustrated with regard to memory cell structures for a flash
memory cell or flash E.sup.2PROM or EPROM cell, but it will be
recognized that the invention has a wider range of applicability.
Merely by way of example, the present invention can be applied to a
variety of embedded memory cell structures such as microprocessors
("MICROs"), microcontrollers, application specific integrated
circuits ("ASICs"), and the like.
[0002] A variety of memory devices have been proposed or used in
industry. An example of such a memory device is an erasable
programmable read-only memory ("EPROM") device. The EPROM device is
both readable and erasable, i.e., programmable. In particular, an
EPROM is implemented using a floating gate field effect transistor,
which has binary states. That is, a binary state is represented by
the presence of absence of charge on the floating gate. The charge
is generally sufficient to prevent conduction even when a normal
high signal is applied to the gate of the EPROM transistor.
[0003] Numerous varieties of EPROMs are available. In the
traditional and most basic form, EPROMs are programmed electrically
and erased by exposure to ultraviolet light. These EPROMs are
commonly referred to as ultraviolet erasable programmable read-only
memories ("UVEPROM"s). UVEPROMs can be programmed by running a high
current between a drain and a source of the UVEPROM transistor
while applying a positive potential to the gate. The positive
potential on the gate attracts energetic (i.e., hot) electrons from
the drain-to-source current, where the electrons jump or inject
into the floating gate and become trapped on the floating gate.
[0004] Another form of EPROM is the electrically erasable
programmable read-only memory ("EEPROM" or "E.sup.2PROM"). EEPROMs
are often programmed and erased electrically by way of a phenomenon
known as Fowler-Nordheim tunneling. Still another form of EPROM is
a "Flash EPROM," which is programmed using hot electrons and erased
using the Fowler-Nordheim tunneling phenomenon. Flash EPROMs can be
erased in a "flash" or bulk mode in which all cells in an array or
a portion of an array can be erased simultaneously using
Fowler-Nordheim tunneling, and are commonly called "Flash cells" or
"Flash devices."
[0005] A limitation with the flash memory cell is high voltage is
often required to program the device. In some conventional devices,
the high voltage can be up to double the amount of voltage needed
to operate the device. As device size becomes smaller, high voltage
is often detrimental to the operation of the device, as well as its
reliability. In particular, high voltages often require a high
voltage supply, which uses a more efficient voltage pump. This
voltage pump generally requires a thicker oxide for the transistor
device, which is often more difficult to make accurately.
Additionally, higher voltages often lead to reliability and quality
problems. These and other limitations exist in conventional flash
memory devices. From the above it is seen that a flash memory cell
structure that is easy to fabricate, cost effective, and reliable
is often desired.
[0006] From the above, it is seem that an improved isolation
structure for an integrated circuit device is highly desirable.
SUMMARY OF THE INVENTION
[0007] The present invention provides a technique, including a
method and device, for an improved flash memory device. In
particular, the present invention provides a novel gate structure,
including floating and control gates, for a flash memory cell.
[0008] In a specific embodiment, the present invention provides a
novel integrated circuit device, which has a flash memory cell. The
flash memory cell has a tunnel dielectric layer overlying a surface
of a semiconductor substrate. A floating gate layer is defined
overlying the tunnel dielectric layer. The gate layer has an edge
defined thereon, where a sidewall spacer extends along and on the
edge. The sidewall spacer includes a first portion defined adjacent
to the edge and a second portion extending from the first portion
to a region substantially outside the edge. The combination of the
sidewall spacer and the gate layer provide a novel surface for
increasing gate coupling ratio ("GCR").
[0009] In an alternative embodiment, the present invention provides
a novel method for forming an integrated circuit device that
includes a flash memory cell. The method includes steps of forming
a tunnel dielectric layer overlying a surface of a semiconductor
substrate, and forming a floating gate layer overlying the tunnel
dielectric layer. The gate layer has an edge defined thereon. The
method also includes a step of forming a sidewall spacer extending
along and on the edge. The sidewall spacer has a first portion
defined adjacent to the edge and a second portion extending from
the first portion to a region substantially outside the edge. Among
other features, the combination of the sidewall spacer and the gate
layer provides a novel surface structure for increasing GCR.
[0010] Numerous benefits are achieved in one or more embodiments of
the present invention over conventional techniques. For example,
the present invention provides a relatively simple structure to
increase a gate coupling ratio of a flash memory device in an
embodiment. The increased gate coupling ratio leads to lower
voltages needed to program the device. Additionally, the present
invention uses a simple technique for manufacturing the novel flash
memory cell. This technique relies on conventional technology
including sidewall spacers. These and other benefits are described
throughout the present specification, and more particularly
below.
[0011] The present invention achieves these benefits in the context
of known process technology. A further understanding of the nature
and advantages of the present invention, however, may be realized
by reference to the latter portions of the specification and
attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 a simplified cross-sectional view diagram of a
conventional flash memory device;
[0013] FIGS. 2A-2D are simplified diagrams of a flash memory device
according to embodiments of the present invention; and
[0014] FIGS. 3-6 are simplified cross-sectional view diagrams of a
method according to an embodiment of the present invention.
DESCRIPTION OF THE SPECIFIC EMBODIMENTS
[0015] I. Conventional Device Structure
[0016] FIG. 1 is a simplified cross-sectional view diagram of a
conventional flash memory device 10. This memory device 10 includes
source/drain regions 23, which are defined in substrate 25. Field
isolation oxide regions 21 are defined in the substrate 25 to
isolate the memory device 10. A gate structure including a floating
gate 11 and a control gate 19 is defined overlying an oxide layer
12, which is defined overlying the substrate 25. Oxide layer 12 is
commonly termed the "tunnel oxide," since electrons tunnel through
the oxide layer to the floating gate. A dielectric layer is
sandwiched between the floating gate 11 and the control gate 19.
The dielectric layer includes an oxide layer 13, which is defined
overlying the floating gate 11. A nitride layer 15 is defined
overlying the oxide layer 13. Another oxide layer 17 is defined
overlying the nitride layer 15. The combination of the two oxide
layers and the nitride layer sandwiched in between is commonly
called an "ONO" structure. An example of this memory device is one
developed by Intel Corporation ("Intel"). Intel called its process
FLOTOX (i.e., FLOating gate Tunneling OXide). Other processes are
called, for example, FETMOX, SIMOS, etc., which differ slightly
from company to company.
[0017] The general storage cell structure includes an access
transistor and a double polysilicon storage cell with a floating
polysilicon gate isolated in silicon dioxide, which is capacitively
coupled to a second polysilicon control gate, which is stacked
directly above the floating gate. The memory cell can be used in
NMOS, as well as CMOS technology.
[0018] The storage cell is erased by Fowler-Nordheim tunneling of
electrons. For example, selected voltages are applied to the
V.sub.DD, V.sub.BB, and V.sub.PP to inject electrons through the
thin oxide layer from the floating gate to the junction. The
floating gate thereby becomes relatively more positively charged.
This shifts the threshold voltage in the negative direction so that
in the READ mode the transistor will be "on." In the program mode
the control gate is at a high voltage while a fixed voltage is
applied to the drain junction to generate hot electrons. These hot
electrons have sufficient energy to overcome the oxide barrier and
enter into the floating gate. The threshold voltage thereby shifts
in the positive direction so that in the read mode the transistor
will be "off." Typically, the erased state corresponds to a logical
"1" stored in the cell, and the programmed state corresponds to a
logical "0" stored in the cell. Of course, in particular
implementations, the reverse notational convention can also be used
such that an erased state corresponds to a logical "0" and a
programmed state corresponds to a logical "1".
[0019] Numerous limitations exist in this conventional cell
structure. As device size becomes smaller, it becomes advantageous
to use lower voltages on the control gate to program the device.
Lower voltages are often achieved by way of a higher gate coupling
ratio. Gate coupling ratio is defined according to the simplified
expression:
GCR.varies.C.sub.ono/(C.sub.tox+C.sub.ono)
[0020] where
[0021] GCR is the gate coupling ratio;
[0022] C.sub.ono is capacitance of the oxide/nitride/oxide; and
[0023] C.sub.tox is capacitance of the tunnel oxide.
[0024] As shown in the above expression, GCR is generally increased
by decreasing the thickness of the tunnel oxide layer, which
reduces capacitance of such layer. Unfortunately, it is generally
impossible to maintain effective device performance having a tunnel
oxide thickness of less than about 110 Angstroms for devices having
a channel length of less than about 1.5 microns. Additionally, the
geometric configuration of the conventional device limits relative
area of the tunnel oxide layer to the ONO layer. Accordingly, GCR
simply cannot be adjusted in an easy and cost effective manner.
Some manufacturers have attempted to provide different geometric
configurations from the conventional device shown by FIG. 1, but
such configurations often come with the additional expense or
limitation in processing the device.
[0025] II. Present Device Structure and Method
[0026] FIGS. 2A-2D are simplified diagrams of a flash memory device
according to embodiments the present invention. These diagrams are
merely examples and should not limit the scope of the claims
herein. One of ordinary skill in the art would recognize other
alternatives, variations, and modifications. In FIG. 2A, for
example, memory device 100 includes a variety of features such as
field isolation oxide regions, which are used to isolate the active
device regions. The device also includes source/drain regions in a
well region.
[0027] A stacked gate structure 110 is defined overlying a channel
region 106. A thin gate dielectric layer 113 is defined overlying
channel region 106. The thin gate dielectric layer is often made of
a high quality oxide layer such as thermal oxide or the like. The
stacked gate structure 110 includes at least two gate structures,
including floating gate 107 and control gate 111. The floating gate
and the control gate are separated from each other by a dielectric
layer 109. This dielectric layer can be a single layer or multiple
layers, e.g., oxide on nitride on oxide. Control gate 111 is
defined overlying the dielectric layer.
[0028] Floating gate 107 is selectively formed to increase GCR in
the present device. Floating gate includes a layer of conductive
material having top surface 117, which is adjacent to dielectric
layer 109. Floating gate 107 also includes sidewall spacers 108,
which extend outside the top surface 117. A combination of the
conductive material layer and conductive sidewall spacers 108
provides a novel geometric configuration that increases an area
that is coupled to control gate 111 while reducing an area that is
coupled to channel region 106. In a specific embodiment, the
surface of the floating gate that is capacitively coupled to the
control gate is much larger than the surface of the floating gate
that is capacitively coupled to the dielectric or tunnel oxide
layer.
[0029] In FIG. 2B, for example, memory device 200 includes a
variety of features such as field isolation oxide regions 202,
which are used to isolate the active device regions, which is shown
in the simplified side-view diagram. The device also includes
source/drain regions 204, 206 in a well region, as shown in the
simplified top-view diagram 201. Some like reference numerals are
used in these Figs. as shown in the above Figs.
[0030] A stacked gate structure 110 is defined overlying a channel
region 106. A thin gate dielectric layer 113 is defined overlying
channel region 106. The thin gate dielectric layer is often made of
a high quality oxide layer such as thermal oxide or the like. The
stacked gate structure 110 includes at least two gate structures,
including floating gate 107 and control gate 111. The floating gate
and the control gate are separated from each other by a dielectric
layer 109. This dielectric layer can be a single layer or multiple
layers, e.g., oxide on nitride on oxide. Control gate 111 is
defined overlying the floating gate including sidewall spacers and
field oxide regions.
[0031] Floating gate 107 is selectively formed to increase GCR in
the present device. Floating gate includes a layer of conductive
material having top surface 117, which is adjacent to dielectric
layer 109. Floating gate 107 also includes sidewall spacers 108,
which extend outside the top surface 117 and sit on the field oxide
regions. Floating gate extends diagonally across active region and
ends at field oxide regions. A combination of the conductive
material layer and conductive sidewall spacers 108 provides a novel
geometric configuration that increases an area that is coupled to
control gate 111 while reducing an area that is coupled to channel
region 106. In a specific embodiment, the surface of the floating
gate that is capacitively coupled to the control gate is much
larger than the surface of the floating gate that is capacitively
coupled to the dielectric or tunnel oxide layer.
[0032] In FIG. 2C, for example, memory device 300 includes a
variety of features such as field isolation oxide regions 202,
which are used to isolate the active device regions, which is shown
in the simplified side-view diagram. The device also includes
source/drain regions 204, 206 in a well region, as shown in the
simplified top-view diagram 302. Some like reference numerals are
used in these Figs. as shown in the above Figs.
[0033] A stacked gate structure 110 is defined overlying a channel
region 106. A thin gate dielectric layer 113 is defined overlying
channel region 106. The thin gate dielectric layer is often made of
a high quality oxide layer such as thermal oxide or the like. The
stacked gate structure 110 includes at least two gate structures,
including floating gate 107 and control gate 111. The floating gate
and the control gate are separated from each other by a dielectric
layer 109. This dielectric layer can be a single layer or multiple
layers, e.g., oxide on nitride on oxide. Control gate 111 is
defined overlying the floating gate with sidewall spacers and field
oxide regions. Control gate does not extend over outside edges of
the sidewall spacers. A select gate 301 is also shown. Select gate
301 overlies a thin layer of gate oxide.
[0034] Floating gate 107 is selectively formed to increase GCR in
the present device. Floating gate includes a layer of conductive
material having top surface 117, which is adjacent to dielectric
layer 109. Floating gate 107 also includes sidewall spacers 108,
which extend outside the top surface 117. A combination of the
conductive material layer and conductive sidewall spacers 108
provides a novel geometric configuration that increases an area
that is coupled to control gate 111 while reducing an area that is
coupled to channel region 106. In a specific embodiment, the
surface of the floating gate that is capacitively coupled to the
control gate is much larger than the surface of the floating gate
that is capacitively coupled to the dielectric or tunnel oxide
layer.
[0035] In FIG. 2D, for example, memory device 400 includes a
variety of features such as field isolation oxide regions 202,
which are used to isolate the active device regions and is shown in
the simplified side-view diagram. The device also includes
source/drain regions 204, 206 in a well region, as shown in the
simplified top-view diagram 401. Some like reference numerals are
used in these Figs. as shown in the above Figs.
[0036] A stacked gate structure 110 is defined overlying a channel
region 106. A thin gate dielectric layer 113 is defined overlying
channel region 106. The thin gate dielectric layer is often made of
a high quality oxide layer such as thermal oxide or the like. The
stacked gate structure 110 includes at least two gate structures,
including floating gate 107 and control gate (and select gate
combination) 111. The floating gate and the control gate are
separated from each other by a dielectric layer 109. This
dielectric layer can be a single layer or multiple layers, e.g.,
oxide on nitride on oxide. Control gate 111 is defined overlying
the floating gate, including a center region of the floating gate
interior portions of both sidewall spacers, and an edge region of
the sidewall spacer to form a split gate-type structure. Control
gate also extends overlying the substrate to the drain region
206.
[0037] Floating gate 107 is selectively formed to increase GCR in
the present device. Floating gate includes a layer of conductive
material having top surface 117, which is adjacent to dielectric
layer 109. Floating gate 107 also includes sidewall spacers 108,
which extend outside the top surface 117. A combination of the
conductive material layer and conductive sidewall spacers 108
provides a novel geometric configuration that increases an area
that is coupled to control gate 111 while reducing an area that is
coupled to channel region 106. In a specific embodiment, the
surface of the floating gate that is capacitively coupled to the
control gate is much larger than the surface of the floating gate
that is capacitively coupled to the dielectric or tunnel oxide
layer.
[0038] In the embodiments noted above, GCR increases by increasing
the relative area of the top surface (including sidewalls) to the
bottom surface, which is coupled to the channel region. Ideally,
GCR approaches one in embodiments of the present invention.
Practically, however, it is quite difficult for GCR to equal one.
Accordingly, GCR ranges from values greater than 0.5, or greater
than 0.75, or greater than 0.8, or greater than 0.9 in the
embodiments of the present invention, although GCR is not limited
to these values. Of course, the final GCR value will depend upon
the particular application.
[0039] The present invention provides larger values of GCR using a
novel fabrication method. This fabrication method uses sidewall
spacer technology, which may use less steps than conventional
techniques, which are becoming quite complicated. By way of easier
fabrication steps, the present invention may provide higher device
yields and better device reliability. As merely an example, the
present invention uses previously existing technology, which is
often considered undesirable, to form a novel device structure.
[0040] In a specific embodiment, a method according to the present
invention may be briefly outlined as follows:
[0041] (1) Provide substrate;
[0042] (2) Form field isolation regions on substrate;
[0043] (3) Form tunnel dielectric layer on substrate;
[0044] (4) Form first polysilicon layer on substrate;
[0045] (5) Form thick CVD oxide layer on the polysilicon layer;
[0046] (6) Define first polysilicon layer and CVD oxide layer to
pattern the first polysilicon layer and the CVD oxide layer;
[0047] (7) Form second polysilicon layer on defined layers;
[0048] (8) Form sidewall spacers on the defined layers from the
second polysilicon layer;
[0049] (9) Selectively remove patterned CVD oxide layer to form
floating gate from the sidewall spacers and patterned first
polysilicon layer;
[0050] (10) Form oxide-on-nitride-on-oxide layer ("ONO" layer) on
sidewall spacers and defined first polysilicon layer;
[0051] (11) Form third polysilicon layer on the ONO layer;
[0052] (12) Define third polysilicon layer to form control gate
layer; and
[0053] (13) Perform remaining fabrication steps as necessary.
[0054] The above sequence of steps is used to define a novel flash
memory cell using an improved gate structure. This sequence of
steps is merely an illustration and should not limit the scope of
the claims herein. One of ordinary skill in the art would recognize
other variations, modifications, and alternatives. The novel flash
memory cell includes a floating gate layer, which is recessed
between sidewall spacers defined on edges of the floating gate
layer. Among other features, the present flash memory cell has a
higher GCR ratio, which is desirable. Details of a method used to
fabricate the present invention are discussed below.
[0055] FIGS. 3-6 illustrate a method according to the present
invention. This method is merely an example and should not limit
the scope of the claims herein. One of ordinary skill in the art
would recognize other alternatives, variations, and modifications.
As shown, the method begins by providing a semiconductor substrate
115, typically the starting point for the fabrication process.
Field oxide regions 103 form onto the semiconductor substrate by
use of a technique known in the art, such as the local oxidization
of silicon (LOCOS), as shown by FIG. 3. Alternatively, the
isolation regions may be trench isolation. Trench isolation can be
formed by way of directional or reactive ion etching or milling of
the substrate to form trenches or "slits" in the substrate between
active regions. These trenches are commonly filled with a
dielectric material to isolate a first active region to a second
active region. In a CMOS embodiment, for instance, P type well
region 101 and N type well region (not shown) are defined onto the
semiconductor substrate, which is typically separated by the field
oxide region 103. The P type well region 101 and the N type well
region define the location for an N type channel device and a P
type channel device, respectively.
[0056] A gate oxide layer 113 is grown overlying both the P type
and N type well regions. The gate oxide layer is typically a thin
layer of oxide, but is not limited to the oxide material. Other
materials such as silicon oxynitride, silicon nitride, and the
like, may also be used. In some embodiments, a step of ion
implanting P type conductivity impurities into the substrate
defines a buried region, which acts as a channel stop region. The
ion implant step is also used to adjust the threshold voltage of
each of the devices. The buried channel is of P type
conductivity.
[0057] A polysilicon layer (or gate layer) is formed overlying the
surface of the gate oxide layer. The gate layer is commonly made of
polysilicon and is also known as the poly 1 layer and the like. The
gate polysilicon layer is often doped with an N type dopant such as
phosphorus and the like. Doping can occur using POCl.sub.3
diffusion, in-situ doping techniques, and implantation techniques.
The gate polysilicon can be formed in a polycrystalline state or an
amorphous state, which is later converted into the polycrystalline
state. Amorphous silicon can be formed using low temperatures,
e.g., 550 degrees C. and less.
[0058] A dielectric layer is deposited overlying the floating gate
layer. The dielectric layer can be any suitable material such as an
oxide layer or a nitride layer. In a specific embodiment, the
dielectric layer is an oxide layer made of chemical vapor
deposition, which is commonly termed a CVD oxide layer. (The CVD
oxide layer is preferably made by way of a silicon bearing compound
and an oxygen bearing compound. As merely an example, the
dielectric layer is defined to form structure 131 and may be SOG,
BPSG, NSG, and others.)
[0059] A masking step defines a floating gate region or floating
gate layer 107 and dielectric region 131 from the polysilicon layer
and the dielectric layer, respectively, as shown by FIG. 3. In
particular, the floating gate region and the dielectric region are
often formed by standard process steps such as masking, exposing,
developing, etching, and others. The underlying oxide layer
typically acts as an etch stop during the etching step, and often
remains overlying both the N type and P type well regions. As
illustrated, the floating gate region and the dielectric layer
region include edges having substantially vertical sides, but are
not limited to these types of sides. The vertical sides are made by
way of plasma processing or wet processing in some cases. Plasma
processing occurs using plasma etching tools. These tools can be
configured to provide substantially vertical edges, which occur by
anisotropic etching processes.
[0060] A polysilicon layer 141 is defined overlying the structure
of the above Fig. The polysilicon layer is conformal. It is formed
using chemical vapor deposition techniques. The polysilicon layer
is known as the poly 2 layer and the like. The polysilicon layer is
often doped with an N type impurity such as phosphorus and the
like. Doping can occur using POCl.sub.3 diffusion, in-situ doping
techniques, and implantation techniques. The polysilicon can be
formed in a polycrystalline state or an amorphous state, which is
later converted into the polycrystalline state. Amorphous silicon
can be formed using low temperatures, e.g., 550 degrees C. and
less. Preferably, polysilicon layer 141 is in electrical and
physical contact with the floating gate region, which is also made
of polysilicon. In a specific embodiment, the polysilicon layer 141
is substantially the same in characteristic (e.g., dopant
concentration, structure) as floating gate region.
[0061] An etching process is used to define the polysilicon layer
141 to form sidewall spacers 108, which are shown in FIG. 5. The
etching process can be any suitable directional etching technique.
As merely an example, a reactive ion etching process can be used to
define the sidewall spacers. The reactive ion etching process
substantially removes horizontal portions of the polysilicon layer
141 while leaving the vertical sections or spacers 108
substantially intact. The sidewall spacers are defined on edges of
the polysilicon region 107 and the dielectric region 131.
[0062] A selective etching step removes the dielectric region 131
from the polysilicon region 107, as illustrated by FIG. 6. The
selective etching step may be a dry etching technique or a wet
etching technique. An example of a wet etching technique can use
hydrofluoric acid or the like. A plasma etching technique may use a
fluorine bearing compound or the like. Of course, the type of
etching technique used depends upon the application. As shown, the
sidewall spacers protrude outwardly and extend beyond the surface
of the polysilicon region. That is, a first portion of a sidewall
spacer is defined along the edge of the floating gate layer and a
second portion of the sidewall spacer, which was previously defined
along the edge of the dielectric layer region, extends outwardly,
since the dielectric region is no longer present.
[0063] A dielectric layer 109 forms overlying the surface of the
floating gate layer. The dielectric layer can be an oxide layer, a
nitride layer, or any combination thereof. In a preferred
embodiment, the dielectric layer is a silicon nitride layer, which
is sandwiched between two oxide layers. As shown, the dielectric
layer forms overlying the top surface of the floating gate region
and the sidewalls to enclose and isolate the floating gate
structure, which includes the floating gate region and the
sidewalls. The dielectric layer is preferably made by way of
thermal oxidation or nitridation or the like. This forms a high
quality dielectric layer to isolate and insulate the floating gate
structure from a control gate layer.
[0064] A control gate layer is defined overlying the dielectric
layer to form the structure shown in, for example, FIG. 2. The
control gate layer is preferably a polysilicon layer. The
polysilicon layer is generally doped with impurities such as an
N-type impurity. The N-type impurity is diffused, implanted, or
in-situ doped. In most cases, it is desirable to in-situ dope the
impurity into the control gate layer to prevent any possible damage
to the dielectric layer. Alternatively, a lower temperature
diffusion process may be used to introduce impurities into the
control gate layer.
[0065] In addition to those steps described above, LDD implants are
made to form the N- type and P- type LDD regions. A mask typically
of photoresist overlying the top surface of the substrate exposes
regions for the N- type LDD implant. The N- type implant forms the
N- type LDD regions for an N type channel device. The mask is then
stripped by way of standard techniques in the art. Another mask
exposes P- type LDD regions for the P- type LDD implant. The P-
type implant forms the P- type LDD regions for a P type channel
device. The mask is then stripped. Source/drain regions are defined
in the memory device. An N+type implant is made to define
source/drain regions of the N-type impurity device. A P+ type
implant is made to define source/drain regions of the P-type
impurity device. To complete the cell structure, the method
undergoes steps of applying an inter-dielectric film overlying the
surface region of the memory device of FIG. 2, for example. Contact
regions or vias are made in the inter-dielectric film. Remaining
fabrications steps are performed to complete the device.
[0066] The embodiment described above is merely a single flash
memory device with a novel gate structure. Integrated circuits
include one or more of these devices in a cell. Thousands,
millions, billions, and even trillions of these devices are formed
in a single integrated circuit chip. Thus, the integrated circuit
chip can have 4 Meg., 16 Meg. 64 Meg. 256 Meg., 1 Gig. or more
devices on a single sliver of silicon. The channel length of these
devices range from about 0.4 .mu.m to 0.25 .mu.m and less. The
flash memory device can be formed in a stand alone integrated
circuit chip, commonly termed the FLASH memory chip, in some
embodiments. Alternatively, the flash memory device can be
integrated into a microprocessor, microcomputer, digital signal
processor, application specific integrated circuit, and the like.
Of course, the number of cells and design size depend highly upon
the application.
[0067] Although the above descriptions have been described in terms
of a stacked gate flash cell, a variety of other flash memory cells
can be used. For example, the present invention can be applied to
cells using processes called split gate flash, and others. Of
course, the type of cell or process used depends upon the
application.
[0068] While the above is a full description of the specific
embodiments, various modifications, alternative constructions and
equivalents may be used. For example, while the description above
is in terms generally to a flash memory structure, it would be
possible to implement the present invention embedded structures.
For example, these embedded structures include, among others,
microprocessors, microcontrollers, and the like. Additionally, the
flash memory structure can be integrated into an application
specific integrated circuit ("ASIC") or the like. Therefore, the
above description and illustrations should not be taken as limiting
the scope of the present invention which is defined by the appended
claims.
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