Sung; Kuo-Tung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sung; Kuo-Tung.The latest application filed is for "cascode cmos structure".

Company Profile

0.19.6

Sung; Kuo-Tung - Zhudong Town TW
Sung; Kuo-Tung - Zhodong Town TW
Sung; Kuo-Tung - Hsinchu TW
Sung; Kuo-Tung - Hsin-Chu TW
Sung; Kuo-Tung - Taipei TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Cascode CMOS structure Grant 9,607,121 - Hsueh , et al. March 28, 2	2017-03-28
Cascode Cmos Structure App 20150020039 - HSUEH; Fu-Lung ; et al.	2015-01-15
Cascode CMOS structure Grant 8,847,321 - Hsueh , et al. September 30, 2	2014-09-30
Contact implement structure for high density design Grant 8,217,469 - Hou , et al. July 10, 2	2012-07-10
Cascode Cmos Structure App 20110215420 - HSUEH; Fu-Lung ; et al.	2011-09-08
Novel Contact Implement Structure For High Density Design App 20110140203 - Hou; Yung-Chin ; et al.	2011-06-16
Method and device for producing undercut gate for flash memory Grant 6,469,341 - Sung , et al. October 22, 2	2002-10-22
Method of improving edge recess problem of shallow trench isolation Grant 6,352,897 - Sung March 5, 2	2002-03-05
Memory cell with built in erasure feature Grant 6,331,721 - Sung , et al. December 18, 2	2001-12-18
New poly spacer split gate cell with extremely small cell size App 20010011744 - Sung, Kuo-Tung	2001-08-09
Floating gate method and device App 20010010960 - Chang, A.J. ; et al.	2001-08-02
Floating gate method and device Grant 6,261,903 - Chang , et al. July 17, 2	2001-07-17
High density programmable read-only memory employing double-wall spacers Grant 6,255,205 - Sung July 3, 2	2001-07-03
Device with differential field isolation thicknesses and related methods App 20010001490 - Sung, Kuo-Tung ; et al.	2001-05-24
Split gate flash cell with extremely small cell size Grant 6,194,272 - Sung February 27, 2	2001-02-27
Method to improve cell performance in split gate flash EEPROM Grant 6,194,269 - Sung , et al. February 27, 2	2001-02-27
Method of implementing differential gate oxide thickness for flash EEPROM Grant 6,184,093 - Sung February 6, 2	2001-02-06
Device with differential field isolation thicknesses and related methods Grant 6,171,927 - Sung , et al. January 9, 2	2001-01-09
Method of forming interpoly dielectric and gate oxide in a memory cell Grant 6,136,647 - Sung October 24, 2	2000-10-24
Flash memory device isolation method and structure Grant 6,121,116 - Sung September 19, 2	2000-09-19
Self-aligned contact process using silicon spacers Grant 6,093,627 - Sung July 25, 2	2000-07-25
Manufacturing process of a split gate flash memory unit Grant 6,083,792 - Sung July 4, 2	2000-07-04
Single-poly flash memory cell for embedded application and related methods Grant 6,044,018 - Sung , et al. March 28, 2	2000-03-28
Method of forming memory cell with built-in erasure feature Grant 5,963,806 - Sung , et al. October 5, 1	1999-10-05

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