U.S. patent application number 09/814431 was filed with the patent office on 2001-08-02 for fabrication method to approach the conducting structure of a dram cell with straight forward bit line.
This patent application is currently assigned to Vanguard International Semiconductor Corporation. Invention is credited to Liang, Wen-Jya, Liaw, Ing-Ruey.
Application Number | 20010010958 09/814431 |
Document ID | / |
Family ID | 26707010 |
Filed Date | 2001-08-02 |
United States Patent
Application |
20010010958 |
Kind Code |
A1 |
Liaw, Ing-Ruey ; et
al. |
August 2, 2001 |
FABRICATION METHOD TO APPROACH THE CONDUCTING STRUCTURE OF A DRAM
CELL WITH STRAIGHT FORWARD BIT LINE
Abstract
A method for fabricating a conducting structure for a
semiconductor device is described. A first dielectric layer is
formed on a substrate. The first dielectric layer is etched by
using a first photoresist layer, to form original contact holes for
exposing surface of the substrate. The first dielectric layer is
etched by using a second photoresist layer which is aligned with
desired contact holes selected from the original contact holes, to
broaden top region of part of the desired contact holes as offset
landing regions. A conductive layer is deposited in the desired
contact holes, which includes the offset landing region, original
contact holes, and on the first dielectric layer. Surface of the
conductive layer is planarized to expose the first dielectric
layer. In this planarization, original contact structures and
desired contact structures having landing plugs are formed, which
landing plugs are defined by the first and second photoresist
layer. A second dielectric layer is deposited on the first
dielectric layer, the original contact structures, and the desired
contact structures;. Bit line contacts are formed in the second
dielectric layer, wherein the bit line contacts are aligned and
contacted with offset sites of the landing plugs. Bit lines are
formed on the bit line contacts, to provide the bit lines in a
substantially straight shape.
Inventors: |
Liaw, Ing-Ruey; (Hsinchu,
TW) ; Liang, Wen-Jya; (Hsinchu, TW) |
Correspondence
Address: |
CHRISTENSEN, O'CONNOR, JOHNSON, KINDNESS, PLLC
1420 FIFTH AVENUE
SUITE 2800
SEATTLE
WA
98101-2347
US
|
Assignee: |
Vanguard International
Semiconductor Corporation
|
Family ID: |
26707010 |
Appl. No.: |
09/814431 |
Filed: |
March 21, 2001 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
09814431 |
Mar 21, 2001 |
|
|
|
09292128 |
Apr 14, 1999 |
|
|
|
6249018 |
|
|
|
|
09292128 |
Apr 14, 1999 |
|
|
|
09031260 |
Feb 26, 1998 |
|
|
|
Current U.S.
Class: |
438/253 ;
257/E21.658; 257/E27.086; 438/396; 438/672 |
Current CPC
Class: |
H01L 27/10808 20130101;
Y10S 257/908 20130101; H01L 27/10888 20130101 |
Class at
Publication: |
438/253 ;
438/396; 438/672 |
International
Class: |
H01L 021/8242; H01L
021/20 |
Claims
What is claimed is:
1. A method for fabricating a conducting structure for a
semiconductor device, which comprises following steps: forming a
first dielectric layer on a substrate; etching the first dielectric
layer by using a first photoresist layer, thereby forming original
contact holes for exposing surface of the substrate; etching the
first dielectric layer by using a second photoresist layer which is
aligned with desired contact holes selected from the original
contact holes, thereby broadening top region of part of the desired
contact holes as offset landing regions; depositing a conductive
layer in the desired contact holes, which includes the offset
landing region, original contact holes, and on the first dielectric
layer; planarizing surface of the conductive layer for exposing the
first dielectric layer, thereby forming original contact structures
and desired contact structures having landing plugs, which are
defined by the first and second photoresist layer; depositing a
second dielectric layer on the first dielectric layer, the original
contact structures, and the desired contact structures; forming bit
line contacts in the second dielectric layer, the bit line contacts
are aligned and contacted with offset sites of the landing plugs;
and forming bit lines on the bit line contacts, thereby providing
the bit lines in a substantially straight shape.
2. The method of claim 1, said step of forming the contact hole and
said step of forming the offset landing region are
exchangeable.
3. The method of claim 1, wherein said offset landing pad and said
desired contact structures are formed by one photoresist layer.
4. The method of claim 1, wherein said step of planarizing
comprising an etching process.
5. The method of claim 1, wherein said step of planarizing
comprising a CMP process.
Description
[0001] This is a divisional of application Ser. No. 09/292,128,
filed on Apr. 14,1999.
FIELD OF THE INVENTION
[0002] The present invention relates to a method for achieving a
multilevel contact structure, which is used in the manufacture of
integrated circuits, and more specifically, to a conducting
structure applied in a DRAM cell.
BACKGROUND OF THE INVENTION
[0003] The provision of interconnections in the design of a COB
(capacitor over bit line) cell of DRAM is particularly important.
In the conventional design, a bit line is twisted to allow the
capacitor to contact the substrate. FIG. 1 illustrates such a
conventional design. An active area 100 is formed over a substrate.
A contact hole 110 is subsequently formed over portions of the
active area 100. Then, a bit line contact 120 is aligned with and
formed over the contact hole 110. Finally, a bit line 130 is formed
on the bit line contact 120. Portions of the bit line 130 overlap
with the bit line contact 120 to form electrical interconnections
and than turn back to an off-axis position of active area as
bypassing the node contact plug to leave a enough isolation spacing
from the node contact. The path of the bit line 130 is thus twisted
as a consequence.
[0004] The provision of bit lines that are twisted, rather than
substantially straight, results in many disadvantages. Series
resistance and parasitic capacitance degrade the bit signal as well
as raise the resolution and overlay difficulties in wafer
processing steps. One possible solution to this limitation could be
to twist the orientation of the active area instead of the bit
line. However, such a design induces other processing or material
issues that still more involving in device manufacturing.
[0005] As the urge for higher packing density of DRAM, the planner
dimension (or area) of the unit cell keeps going to smaller and
smaller via the advances in the lithographic system and the self
aligned contact (SAC) technology. However, because of the tolerance
of isolation thickness in SAC etching as well as the polishing
level variation in CMP planarization, a definite height in vertical
is still in need. The aspect ratio of the cell node contact (or bit
line contact in CUB cell ) goes still worse and worse. This makes
the reliability of the contact resistance and/or the substrate
damage become uncontrollable. A two-step contact structure, which
uses projected landing pads or recessed landing plugs raised from
substrate as step buffering for the second contact forming steps,
has been undertaken commonly by most of the DRAM chip supplier.
SUMMARY OF THE INVENTION
[0006] In this disclosure, substrate contact landing plugs with
off-axis landing sites is achieved by using a novel integrated
process. So the aspect ratio of the node contact can be
substantially reduced. By introducing one more lithographic layer
of isolated hole, we can use the simplest and most reliable
patterns of piecewise straight active area, unit sized plug contact
and substantially straight bit line layouts, with the least cost in
processing steps and slightest resultant surface fluctuation.
[0007] For approaching the conducting structure, a conventional COB
cell with piecewise straight active areas is used as an
illustration. After the accomplishment of the processing steps of
the access device, a first dielectric layer is deposited. A contact
pattern is then formed on the first dielectric layer for exposing
the surface of substrate both at the node contact and bit line
contact area, by using a first photoresist layer as a mask to etch
the first dielectric layer. This is usually a SAC process that the
contacts are self aligned to the substrate as etched. An offset
landing plug pattern is then defined by a photoresist-clear pattern
only beside the contact pattern at the bit line contact area and
recess-etched to an extent into the first dielectric layer, so as
to electrically connect with the primary contact structure at the
bit line contact site finally. The contact structure is then formed
by a deposition-etched process, which performs as a landing plug
for the upper contact structures. The top area of the landing plug
is thus defined via the additive pattern of the primary contact as
well as the offset landing plug pattern. A second dielectric layer
is then deposited on the first dielectric layer and the contact
structure. Thereafter, a bit line contact pattern is defined by a
third photoresist layer. The bit line contact is just located at
the position of the offset landing plug and etched to its top,
thereby, providing a capability of forming a substantially straight
bit line passing over the bit line contact, which is electrically
connected with the active area through the bit line contact and the
landing plug contact structure.
BRIEF DESCRIBING OF THE DRAWINGS
[0008] FIG. 1 is a conducting structure in accordance with prior
art.
[0009] FIG. 2 is a layout pattern in accordance with the present
invention.
[0010] FIG. 3 is a cross-sectional view of the present
semiconductor structure with a contact hole and offset landing
region.
[0011] FIG. 4 is a cross-sectional view of the present
semiconductor structure with a contact structure having an offset
landing plug.
[0012] FIG. 5 is a top view of a contact structure in accordance
with the present invention.
[0013] FIG. 6 is a top view of the present semiconductor structure
having a straight bit line connected with the contact
structure.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0014] For overcoming the disadvantages mentioned above, the
present invention discloses a fabrication method to approach a
conducting structure with a substantially straight bit line. By
broadening a top portion of traditional contact structure, an
offset landing plug would be formed in the broadened region and
serve as a part of the contact structure. The offset landing plug
has an extensive area, which provides the semiconductor a
capability of forming a substantially straight bit line. For
illustrating clearly, an embodiment is used to describe the
invention in the following paragraphs.
[0015] FIG. 2 shows a layout pattern for fabricating a
semiconductor structure with substantially straight bit lines in
the invention. Patterns 200' are used to map active areas on a
surface of semiconductor substrate. A photoresist layer, which is
utilized to define the active areas, is formed over the
semiconductor substrate by transferring patterns 200' onto the
photoresist layer in a photolithography process. Thereafter, the
active areas are formed in the region defined by patterns 200'. The
contact structures are made of conductive materials for
electrically connecting devices and circuits in the semiconductor
structure. At the first, patterns 210 are used to define a
plurality of contact structures, which are formed on portions of
the active areas. Then, patterns 220' are selectively applied to
define offset landing plug above some of contact structures. After
then, patterns 220' could be used again to define bit line contacts
on the surfaces of offset landing plugs for further providing bit
lines, which are defined by patterns 240', without twist.
[0016] As discussed above, the locations of conducting structures
are defined by several layout patterns. Therefore, the alignment of
patterns would be a crucial issue of achieving the desired
structure. Typically, the more complicated layout patterns would
induce more inaccurate conducting structures. For fabricating
accurate conducting structures, the present invention allows the
patterns 220' merely aligning with some desired contact structures
instead of every contact structure, thereby simplifying the layout
patterns 220' as well as increasing the accuracy of mapped
conducting structures.
[0017] FIG. 3 displays a cross-sectional view of a semiconductor
structure along axis A-A' (see FIG. 2) for describing an embodiment
of forming a desired conducting structure according to the present
invention. Active area 200 is defined on substrate 400 and isolated
from other semiconductor devices by isolation regions 405, such as
Field Oxide or Trench. A first dielectric layer 410 is deposited on
the surfaces of active area 200 and isolation region 405.
Typically, the first dielectric layer 410 could be selected from
the dielectric materials, such as SiO.sub.2, Si.sub.3N.sub.4, PSG,
and BPSG.
[0018] For electrically connecting devices or circuits inside
active area 200, a first photoresist layer (not shown in figure) is
placed on the surface of the first dielectric layer 410 to define
vertical portion of contact hole 206. Applying the first
photoresist layer as an etching mask, the first dielectric layer
410 would be etched downwardly until surface 215a of active area
200 exposed. Then, first photoresist layer is removed from the
surface of first dielectric layer 410. When the first photoresist
layer has been stripped, a second photoresist layer (not shown in
figure) is disposed on the surface of first dielectric layer 410 in
order to define offset landing portion 215b of contact hole 206.
Thereafter, etching first dielectric layer 410 by means of serving
the second photoresist layer as a mask, portion 215b would be
formed in the top region of contact hole 206. In the process of
forming horizontally extensive portion 215b, first dielectric layer
410 would be merely etched a shallow depth instead of reaching
active area 200. When contact hole 206, which has both vertical
portion 215a and horizontal portion 215b, is achieved, the second
photoresist layer would be stripped so as to proceed following
processes.
[0019] Referring to FIG. 4, a conductive layer is formed inside the
contact hole 206 as well as on the surface of first dielectric
layer 410. Since the top region of contact hole 206 has been
broadened as extensive portion 215b, the performance of step
coverage of contact hole 206 would be better than without extensive
portion 206. Then, planarizing the surface of the conductive layer,
contact structure 210 is formed in the contact hole 206 as two
parts, the vertical portion 208 and the offset landing plug 220.
Typically, the planarization process is alternative between a
method of etching back and CMP. As for the conductive layer, it
could be usually selected from Tungsten, Aluminum, and
Ploysilicon.
[0020] After then, second dielectric layer 420 is deposited on the
surface of first dielectric layer 410 and contact structure 210. A
third photoresist layer (not shown in figure) is disposed on the
surface of second dielectric layer 420, so as to define the area of
bit line contact 230. As mentioned above, the masks of defining the
area of offset landing plug 220 and bit line contact 230 could be
the same one. Nevertheless, by applying the third photoresist layer
as an etching mask, bit line contact hole (the same position with
bit line contact 230) is formed in second dielectric layer 420 as
well as exposed the surface of offset landing plug form it. After
the third photoresist layer stripped, a second conductive layer is
deposited in the bit line contact hole and surface of second
dielectric layer 420. Patterning and etching the second conductive
layer, a desired conducting structure with a substantially straight
bit line is achieved and shown as the figure. Through contact
structure 210 and bit line contact 230, bit line 240 is able to
connect with active area 200 electrically. Furthermore, offset
landing plug 220 provides the capability of shaping bit line 240
without twisting.
[0021] FIG. 5 and FIG. 6 illustrate a top view of conducting
structure according to the present embodiment. Referring to FIG. 5,
active areas 200 are formed over a semiconductor substrate. The
contact structures 210 are formed over a portion of the active
areas 200. The offset landing plug 220 is selectively formed on one
of the contact structures 210. For a good electrical connection, a
wet etch process may be used to enlarge the top dimensions of the
primary contact hole 210 and the offset shallow hole 220 as just
etched.
[0022] FIG. 6 is an illustration of the top view of the final
result from the above embodiment. It also shows the result of
pattern rounding and the enlargement of contact size after DHF
clean usually performed before the deposition of plug material,
which provide the sufficient overlap and reliable connection of the
whole contact structure. Bit line contacts 230 are formed on the
surface of offset landing plugs 220 within the contact structures
210. Then, bit lines 240 are formed parallel with active areas 200,
thereby straightening the bit lines 240 from twisting in accordance
with prior art.
[0023] As illustrated above, the present invention discloses a
contact structure, with an offset landing plug, within a single
dielectric layer. The present method of approaching the specific
conducting structure, is not only providing a COB DRAM cell the
simplest piecewise straight active areas and substantially straight
bit line, but also allowing a layout in the cost of merely an extra
conventional contact hole mask layer. Therefore, the depth of the
contact structure would not be heightened by means of performing
the present fabrication process. In addition, since the offset
landing plug is selectively imposed on the desired contact
structure instead of all contact structures in a way without
creating any step difference. Therefore, the mask of offset landing
plug would be designed as simple as possible, so as to reduce the
risk of miss-patterning caused by a complicated mask, probably.
Furthermore, before the second dielectric layer deposited, the
present conducting structure provides a rather smooth top surface
compared to the conventional projected-type landing pad structure.
Thus, it doesn't need an extra planarization step for the second
dielectric layer often used in those structures. All the above
advantages of the invention will significantly reduce the
complexity of manufacture process as well as the cost of the device
production. Finally, it should be noticed that an alternative to
approach the Conducting Structure with non-additional mask layer is
practically possible, by applying a multi-sized plug contact
pattern layout. In other words, using contact mask with a broadened
size pattern at the bit line node in company with the normal size
pattern at the storage node, the off-axis landing plug contact
structure is thereby achieved within one photoresist mask pattern
layer. Therefore, in such a design, the cost of the extra
lithograph etch process of the offset landing plug could be saved.
However, in such an approach, a novel broadened contact etching
technology with precisely etching end point control, which is
supposed to be stop at the boundary of active area without damaging
the isolation region, is still needed eagerly. Since otherwise the
override and undercut of the isolation region boundary may cause
serious isolation and/or junction leakage issues in many cases.
[0024] As is understood by a person skilled in the art, the
forgoing description of the preferred embodiment of the present
invention is illustrative of the present invention rather than a
limitation thereon. It is intended to cover various modifications
and similar arrangements included within the spirit and scope of
the appended claims. The scope of the claims should be accorded
with the broadest interpretation so as to encompass all such
modifications on the similar structure. While the preferred
embodiment of the invention has been illustrated and described, it
will be appreciated that various changes can be made therein
without departing from the spirit and scope of the invention.
* * * * *