U.S. patent application number 09/769385 was filed with the patent office on 2001-08-02 for semiconductor memory device.
Invention is credited to Higashide, Yoshiko, Ohbayashi, Shigeki.
Application Number | 20010010643 09/769385 |
Document ID | / |
Family ID | 18546529 |
Filed Date | 2001-08-02 |
United States Patent
Application |
20010010643 |
Kind Code |
A1 |
Higashide, Yoshiko ; et
al. |
August 2, 2001 |
Semiconductor memory device
Abstract
A semiconductor memory device according to the present invention
comprises, in general, a memory cell array, a plurality of
first-layer and second-layer bit lines. The memory cell array
includes a matrix of memory cells arranged along a line and row
directions, each memory cell being formed within a memory cell
region. Each of first-layer bit lines is extending along the row
direction, and provided on a plurality of the memory cell regions.
Each of second-layer bit lines is connected with the first-layer
bit line via a connecting hole. The memory cell regions include
first and second memory cell regions, the first memory cell region
is provided with the connecting hole, the second memory cell region
is not provided with the connecting hole. Also, at least one of the
memory cells formed within the first memory cell regions is a dummy
cell incapable of electrically serving as the normal memory
cell.
Inventors: |
Higashide, Yoshiko; (Tokyo,
JP) ; Ohbayashi, Shigeki; (Yokyo, JP) |
Correspondence
Address: |
BIRCH STEWART KOLASCH & BIRCH
PO BOX 747
FALLS CHURCH
VA
22040-0747
US
|
Family ID: |
18546529 |
Appl. No.: |
09/769385 |
Filed: |
January 26, 2001 |
Current U.S.
Class: |
365/185.2 |
Current CPC
Class: |
G11C 7/18 20130101; G11C
5/063 20130101 |
Class at
Publication: |
365/185.2 |
International
Class: |
G11C 016/06 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 28, 2000 |
JP |
2000-019897 |
Claims
What is claimed is:
1. A semiconductor memory device, comprising: a memory cell array
including a matrix of memory cells arranged along line and row
directions, each memory cell being formed within a memory cell
region; a plurality of first-layer bit lines extending along the
row direction, each provided on a plurality of said memory cell
regions; and a plurality of second-layer bit lines, each of which
is connected with said first-layer bit line via a connecting hole;
wherein said memory cell regions include first memory cell regions
on which said connecting hole is provided, and second memory cell
regions on which said connecting hole is not provided, and wherein
at least one of said memory cells formed within said first memory
cell regions is a dummy cell incapable of serving an electrical
memory operation.
2. A semiconductor memory device, comprising: a memory cell array
including a matrix of memory cells arranged along line and row
directions, each memory cell being formed within a memory cell
region; a plurality of first-layer bit lines extending along the
row direction, each provided on a plurality of said memory cell
regions; and a plurality of second-layer bit lines, each of which
is connected with said first-layer bit line via a connecting hole;
wherein said memory cell regions include first memory cell regions
on which said connecting hole is provided, and second memory cell
regions on which said connecting hole is not provided, and wherein
at least one of said memory cells formed within said memory cell
regions adjacent to said first memory cell regions along the line
direction is a dummy cell incapable of serving an electrical memory
operation.
3. The semiconductor memory device according to claim 1, wherein
each memory cell is connected with a pair of said first-layer bit
lines, one of said pair of said first-layer bit lines is connected
with one of said second-layer bit lines through said connecting
hole within said memory cell region of said dummy cell, and another
one of said pair of said first-layer bit lines is connected with
one of said second-layer bit lines through said connecting hole
within said memory cell region of said memory cell capable of
serving the electrical memory operation.
4. The semiconductor memory device according to claim 3, wherein
two or four of said memory cell regions of said dummy cells are
arranged in series along the row direction.
5. The semiconductor memory device according to claim 3, further
comprising: a plurality of dummy cell bit lines connected with said
dummy cells for maintaining said dummy cells to a GND
potential.
6. The semiconductor memory device according to claim 4, further
comprising: a plurality of dummy cell bit lines connected with said
dummy cells for maintaining said dummy cells to a GND
potential.
7. The semiconductor memory device according to claim 5, wherein
said memory cell array further includes a GND line extending along
the row direction, each of said dummy cell is connected with said
GND line via said dummy cell bit lines.
8. The semiconductor memory device according to claim 6, wherein
said memory cell array further includes a GND line extending along
the row direction, each of said dummy cell is connected with said
GND line via said dummy cell bit lines.
9. The semiconductor memory device according to claim 1, wherein
each of said dummy memory cell includes a pair of memory node
portions and a pair of load transistors with drain-source regions,
and each drain-source region is disconnected with any of said
memory node portions.
10. The semiconductor memory device according to claim 2, wherein
each of said dummy memory cell includes a pair of memory node
portions and a pair of load transistors with drain-source regions,
and each drain-source region is disconnected with any of said
memory node portions.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Technical field of the Invention
[0002] The present invention relates to a semiconductor memory
device including two layers of bit lines formed thereon.
[0003] 2. Description of Related Arts
[0004] Semiconductor memory devices used in the recent office
automation equipments, for example, a personal computer and a word
processor, demand the semiconductor memory devices capable of
storing and reading larger amount of data. In order to meet this
demand, a variety of approaches have been proposed up to the
present. Among others, commonly assigned U.S. Pat. Nos. 5,280,441
and 5,379,820 both granted to Wada et al. disclose a circuit design
with a T-shaped bit line for connection between the memory device
and circuits arranged therearound, which decreases limitations on
the circuit and allows the circuits to be arranged in a suitable
manner around the memory device. Also, commonly assigned U.S. Pat.
Nos. 5,563,820 and 5,699,308 both granted to Wada et al. teach an
integrated semiconductor memory device, of which high density is
achieved by appropriately adjusting intervals between the adjacent
first-layer bit lines. The aforementioned U.S. patents are
incorporated herein by reference in this patent application.
[0005] When the integration of MOSFETs formed beneath the
first-layer bit line is greater than that of metal wire layers, it
is expected that the dimensions of memory cell regions may be
subject to those of the dimensions of the first-layer and
second-layer bit lines.
[0006] In particular, when the through-hole acting as a connecting
hole between the first-layer and second-layer bit lines is arranged
on a memory cell region, the interval of adjacent first-layer bit
lines are extended so that the dimension of the memory cell region
should also be extended. Thus, the dimension of a memory cell
arrays is extended, and the area thereof is increased. In other
words, this causes the enlargement of the memory cell array,
preventing the array from being highly integrated.
[0007] Details of prior arts and defects thereof are also described
in the description of the Japanese Patent Application No.
11-347449, filed by the applicant.
SUMMARY OF THE INVENTION
[0008] The present invention is to address to the aforementioned
problem, and an object thereof is to prevent the dimensions of
memory cell array from being extended due to an existence of the
connecting holes even where the dimension of memory cell regions
may be determined by those of first-layer and second-layer bit
lines.
[0009] The semiconductor memory device according to the first
invention comprises: a memory cell array including a matrix of
memory cells arranged along line and row directions, each memory
cell being formed within a memory cell region; a plurality of
first-layer bit lines extending along the row direction, each
provided on a plurality of the memory cell regions; and a plurality
of second-layer bit lines, each of which is connected with the
first-layer bit line via a connecting hole; wherein the memory cell
regions include first memory cell regions on which the connecting
hole is provided, and second memory cell regions on which the
connecting hole is not provided, and wherein at least one of the
memory cells formed within the first memory cell regions is a dummy
cell incapable of serving an electrical memory operation.
[0010] The semiconductor memory device according to the second
invention comprises: a memory cell array including a matrix of
memory cells arranged along line and row directions, each memory
cell being formed within a memory cell region; a plurality of
first-layer bit lines extending along the row direction, each
provided on a plurality of the memory cell regions; and a plurality
of second-layer bit lines, each of which is connected with the
first-layer bit line via a connecting hole; wherein the memory cell
regions include first memory cell regions on which the connecting
hole is provided, and second memory cell regions on which the
connecting hole is not provided, and wherein at least one of the
memory cells formed within the memory cell regions adjacent to the
first memory cell regions along the line direction is a dummy cell
incapable of serving an electrical memory operation.
[0011] In the semiconductor memory device according to the third
invention, each memory cell is connected with a pair of the
first-layer bit lines, one of the pair of the first-layer bit lines
is connected with one of the second-layer bit lines through the
connecting hole within the memory cell region of the dummy cell,
and another one of the pair of the first-layer bit lines is
connected with one of the second-layer bit lines through the
connecting hole within the memory cell region of the memory cell
capable of serving the electrical memory operation.
[0012] In the semiconductor memory device according to the fourth
invention, two or four of the memory cell regions of the dummy
cells are arranged in series along the row direction.
[0013] Also, the semiconductor memory device according to the fifth
invention further comprises: a plurality of dummy cell bit lines
connected with the dummy cells for maintaining the dummy cells to a
GND potential.
[0014] In the semiconductor memory device according to the sixth
invention, the memory cell array further includes a GND line
extending along the row direction, each of the dummy cell is
connected with the GND line via the dummy cell bit lines.
[0015] In the semiconductor memory device according to the seventh
invention, each of the dummy memory cell includes a pair of memory
node portions and a pair of load transistors with drain-source
regions, and each drain-source region is disconnected with any of
the memory node portions.
[0016] Further scope of applicability of the present invention will
become apparent from the detailed description given hereinafter.
However, it should be understood that the detailed description and
specific examples, while indicating preferred embodiments of the
invention, are given by way of illustration only, since various
changes and modifications within the sprit and scope of the
invention will become apparent to those skilled in the art from
this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The present invention become more fully understood from the
detailed description given hereinafter and accompanying drawings
which are given by way of illustration only, and thus are not
limitative of the present invention and wherein,
[0018] FIG. 1 is a design pattern of a memory cell array according
to Embodiment 1 of the present invention;
[0019] FIG. 2 is a design pattern of a memory cell array according
to Embodiment 2 of the present invention;
[0020] FIG. 3 is a design pattern of a memory cell array according
to Embodiment 3 of the present invention;
[0021] FIG. 4 is a design pattern of a memory cell according to
Embodiment 4 of the present invention;
[0022] FIG. 5 is a design pattern of a dummy cell according to
Embodiment 4 of the present invention;
[0023] FIG. 6 is an equivalent circuitry diagram of the memory cell
according to Embodiment 4 of the present invention;
[0024] FIG. 7 is an equivalent circuitry diagram of the dummy cell
according to Embodiment 4 of the present invention;
[0025] FIG. 8 is a design pattern of a memory cell array according
to Embodiment 4 of the present invention;
[0026] FIG. 9 is an equivalent circuitry diagram of the dummy cell
according to Embodiment 4 of the present invention;
[0027] FIG. 10 is a design pattern of a memory cell array according
to Embodiment 5 of the present invention;
[0028] FIG. 11 is a design pattern of a dummy cell according to
Embodiment 5 of the present invention;
[0029] FIG. 12 is an equivalent circuitry diagram of the dummy cell
according to Embodiment 5 of the present invention; and
[0030] FIG. 13 is a design pattern of a memory cell array according
to Embodiment 6 of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0031] Embodiment 1.
[0032] FIG. 1 is a design pattern of a memory cell array of a SRAM
(Static Random Access Memory) according to Embodiment 1 of the
present invention, including eight memory cells arranged in a
4.times.2 matrix, with four memory cells in a row direction and two
memory cells in a line direction, each being outlined by dotted or
imaginary lines. Also, first-layer and second-layer bit lines are
illustrated in a hatched form to distinguish them from others for
the purpose of clarification.
[0033] Reference numerals 171a to 171d denote memory cell regions,
which serves as electrically operable memory cells. (Hereinafter,
memory cells and memory cell regions are referred to as normal
cells and normal cell regions, respectively.) Reference numerals
501a to 501d denote memory cell regions, which serves as
electrically inoperable memory cells. (Hereinafter, memory cells
and memory cell regions are referred to as dummy cells and dummy
cell regions, respectively.) Each of the normal and dummy cell
regions are illustrated to have substantially the same size,
although the dimensions of the normal and dummy cell regions may be
manufactured in different sizes. Also, each of patterns beneath the
first bit lines in normal and dummy cell regions have substantially
the same sizes.
[0034] Reference numerals 32a, 32b and 132a denote first-layer bit
lines made of metal wire layers. Reference numerals 152a and 152b
denote second-layer bit lines made of metal wire layers.
[0035] As shown in FIG. 1, the first-layer bit lines 32a and
second-layer bit lines 152a and 152b are paired with each other,
respectively. The first-layer bit line 32a is connected with memory
devices provided in normal cell regions 171a and 171b through a bit
line contact 166a and with memory devices provided in normal cell
regions 171c and 171d through a bit line contact 166c. On the other
hand, the first-layer bit line 32b, which has a vermiculate
configuration, is connected with memory devices provided in normal
cell regions 171a and 171b through a bit line contact 166b and with
memory devices provided in normal cell regions 171c and 171d
through a bit line contact 166d. The first-layer bit line 32b is
formed on the dummy cell regions 501a to 501d, without being
connected with the dummy cell regions through the bit line
contact.
[0036] The first-layer bit line 132a is a bit line for dummy cells
(referred to as a "dummy cell bit line") and is connected with
dummy memory cells 501a and 501b through the bit line contact 166e
and with dummy cells 501c and 501d through a bit line contact
166f.
[0037] The first-layer bit line 32a is connected with the
second-layer bit line 152a via a through-hole 142a in the normal
cell region 171b. The first-layer bit line 32b is connected with
the second-layer bit line 152b via a through-hole 142b in the dummy
cell region 501c.
[0038] Also, the first-layer bit line 132a is connected with the
second-layer bit line, which is not shown in this drawing, via the
through-hole 142c.
[0039] By the way, a boundary line along the line direction between
memory cell regions of an adjacent first and second normal cells is
defined such that it follows on the middle points of the minimum
distance between edges of adjacent first-layer bit lines on the
first and second normal cells, and extends parallel with the row
direction.
[0040] In case where the normal cell is adjacent to the dummy cell,
the boundary line therebetween is defined as an extending line of
the aforementioned boundary line between memory cell regions of
adjacent first and second normal cells.
[0041] The width of the memory cell regions along the line
direction is defined as a minimum distance between the right and
left boundary lines of one memory cell region.
[0042] As shown in FIG. 2 according to Embodiment 2 (although not
shown in FIG. 1), the boundary lines along the line direction of
the memory cell region located on the 11th line and second row, for
example, are defined, at one side, by the boundary line thereof at
the left side based upon a relationship between the adjacent normal
cells located on the 11th line and first row and on the 11th line
and the second row, and at another side, by the boundary line
thereof at the right side based upon the relationship between the
adjacent normal cells located on the 11th line and second row and
on the 11th line and the third row.
[0043] Also, boundary lines along the row direction between
adjacent memory cell regions are defined as follows. In a series of
the first through fourth memory cell regions arranged along the row
direction, and in general, the bit line contact is commonly
connected with two adjacent memory cells such as the first and
second memory cells, and the third and fourth memory cells.
Therefore, boundary lines along the row direction between the first
and second memory cells, and the third and fourth memory cells are
defined such that they follows on the bit line contacts. Also,
another boundary line along the row direction between the second
and third memory cells is defined such that it traces on a middle
position between the bit line contacts. Thus, the boundary lines
along the row direction between adjacent memory cell regions are
defined such that they follow on the bit line contacts or on the
middle positions between the bit line contacts, and extend parallel
in the line direction.
[0044] Therefore, the length of the memory cell regions along the
row direction is defined as the minimum distance between the
adjacent boundary lines along the row direction.
[0045] The dimensions and boundary lines of the memory cell regions
are defined as above, however, any other definitions can be
applied, when they represent a unit of a memory cell which
memorizes one bit memory.
[0046] Next, the advantages according to Embodiment 1 as described
above are described hereinafter. In Embodiment 1, a through-hole
corresponding to one of the first-layer bit line is arranged on the
normal cell region, and the dummy cell regions are arranged
adjacent to the normal cell regions along the line direction. Thus,
the another of the first-layer bit line can be arranged on the
dummy cell regions. Therefore, the first-layer and second-layer bit
lines can be constructed without extending the dimension along the
line direction of each normal cell region even where the
through-hole is arranged.
[0047] Also, the through-hole corresponding to the another bit line
is arranged on the dummy cell regions so that the connection of the
first-layer and second-layer bit lines can be realized without
dimensional extension along the line direction of the normal cell
regions due to the through-holes.
[0048] Further, each normal cell region has dimensions along the
line and row directions, which are substantially the same as those
of each dummy cell region so that a layout of the memory cell array
can be simple, thereby to readily design the memory cell array.
[0049] Embodiment 2.
[0050] Next, referring to FIG. 2, Embodiment 2 of the present
invention is discussed hereinafter. FIG. 2 shows a pattern of the
memory cell array including more memory cells than those shown in
FIG. 1 of Embodiment 1. In particular, FIG. 2 shows the pattern of
sixteen memory cells along the row direction, five memory cells in
the line direction, and a plurality of first-layer and second-layer
bit lines.
[0051] The pattern shown in FIG. 1 according to Embodiment 1
corresponds to a portion of the pattern shown in FIG. 2, which are
defined by the memory cell regions on second and third rows and on
the fifth to eighth lines.
[0052] As shown in FIG. 2, four dummy cell regions in series along
the row direction compose a set of the dummy cell regions, which
shifts by one row every four lines. For example, a set of the dummy
cell regions is located on the first to fourth lines at the second
row, and on the fifth to eighth lines at the third row.
[0053] The set of the four dummy cell regions basically has a
function as follows. The dummy cell region 501a is a bending region
where the first-layer bit line 32b is bent. The dummy cell region
501b is a spacing region where the first-layer bit line 32b is
spaced from the through-hole 142a. The dummy cell region 501c is an
arranging region where the through-hole 142b is arranged. The dummy
cell region 501d is a connecting region where the through-hole 142c
is connected with the dummy cell bit line 132a.
[0054] Further, a GND line is provided on the right side of memory
cell regions arranged on the fifth row. The GND line is made of a
metal wire for providing a GND potential, in which use of a
first-layer metal wire 132b is illustrated in this instance.
[0055] The dummy cell bit line 132a for dummy cells 501a to 501d is
connected with the first-layer metal wire 132b via the through-hole
142c, the second-layer metal wire 152c, and the through-hole 142d.
Thus, the potential of the dummy cell bit line 132a is maintained
to the GND potential.
[0056] Also, active region portions of dummy cell regions (not
shown), which are connected with the bit line 132a via bit line
contacts 166e and 166f, have their potentials maintained to the GND
potential. Similarly, other dummy cell bit lines have the
potentials maintained to the GND potential.
[0057] Next, the dimension of the memory cell array is described
hereinafter. Since the conventional memory cell array consists of
normal cells only, each of which has the same dimension, an
arrangement of the through-holes causes the dimension of each
memory cell region to be extended, thus, increasing the area of the
memory cell array.
[0058] However, in case where the following conditions meet with
arrangement of the dummy cell regions, the total area of the memory
cell array can be substantially reduced or shrank.
[0059] Suppose if no through-hole is arranged on the memory cell
region, then the memory cell array can be designed and manufactured
as small as possible, in which the minimum width along the line
direction of each normal memory cell region (each dummy cell
region) is represented as "C". In addition, in order to arrange the
through-holes in a conventional manner, the aforementioned width is
required to be added by an increased width (represented as "a")
along the line direction of each memory cell region. The row number
of the memory cell regions arranged along the line direction is
represented as "n". In case where only one of the above-mentioned
set of the dummy cell regions is arranged in each row, the width
along the line direction of the memory cell array are: in the
conventional case: (C+a).times.n, and in the case of this
embodiment: C.times.(n+1).
[0060] Therefore, the area of memory cell array can be reduced or
shrank with arrangement of the dummy cell regions, if the following
condition formula is satisfied:
(C+a).times.n>C.times.(n+1)
[0061] As described above, since four dummy cell regions are
arranged in series along the row direction as a set of the dummy
cell regions, the bit lines can be regularly arranged thereon.
Thus, the memory cell array according to this embodiment can be
designed in a simple manner.
[0062] Also, the active regions of dummy cells connected with the
dummy cell bit lines and the bit line contacts have the potentials
maintained to the GND potential so that the potentials of the dummy
cell bit lines can be kept stable. Therefore, the GND potential can
reduce adverse affects to the normal cells due to the astable
potentials of dummy cell bit lines, and so on.
[0063] Further, the dummy cell bit lines are connected with the GND
line so that no particular GND wire region for the dummy cell bit
lines should be arranged. Thus, the area of the memory cell array
can be substantially reduced.
[0064] When the row number (n) meets the aforementioned condition
formula, the area of the memory cell array can be reduced or shrank
with arrangement of the dummy cell regions, in comparison with the
case where the area thereof is increased in the conventional
manner.
[0065] Embodiment 3.
[0066] FIG. 3 shows an another pattern of memory cell array
according to Embodiment 3. While FIG. 2 according to Embodiment 2
shows the GND line formed on only one row in series along the row
direction, FIG. 3 according to Embodiment 3 shows GND lines
arranged on a plurality of lines along the row direction. In
particular, the GND line is provided on the first to seventh lines
at the fourth row, on the ninth to sixteenth lines at the third
row, and on the third and fourth rows at eighth line. Thus, in case
even where the GND line is continuously provided on a plurality of
rows, the dummy cell regions can be arranged.
[0067] Embodiment 4.
[0068] Referring to FIGS. 4 and 5, Embodiment 4 is described
hereinafter. FIGS. 4 and 5 show patterns beneath the first-layer
metal wire of the normal cells and dummy cells shown in FIG. 1,
respectively. Referring to the pattern of the normal cell shown in
FIG. 4, reference numerals 61a to 61c denote separating insulative
layers, reference numerals 62a to 62j denote active layers,
reference numerals 63a to 63c denote poly-silicon layers, reference
numerals 65a to 65d denote third-layer metal wires, reference
numerals 64a to 64d and 67a to 67d denote first contacts connecting
between the active layers and the third-layer metal wires, and
reference numerals 64e and 64f denote second contacts connecting
between the poly-silicon layers and the third-layer metal
wires.
[0069] Reference numerals 65a and 65b denote a GND wire and a Vcc
wire, respectively. In particular, reference numerals 64a and 64b
are referred to as "GND contacts", and reference numerals 64c and
64d are referred to as "Vcc contacts". Reference numerals 166a and
166b are the bit line contacts as described in Embodiment 1 and 2,
which connect between the first-layer bit lines 32a and 32b, and
active layers 62a and 62d, respectively.
[0070] The active layers 62b, 62e, 62g, and 62i are to form memory
nodes of the memory cell, in which memory data are stored. The
active layers 62b and 62g are connected with each other via the
first contacts 67c and 67a, respectively, and via the third-layer
metal wire 65c so as to form one memory node. The active layers 62e
and 62i are connected with each other via the first contacts 67d
and 67b, respectively, and via the third-layer metal wire 65d so as
to form the another memory node.
[0071] Also, the active layers 62c and 62f are connected with the
GND wire 65a via the GND contacts 64a and 64b, thus, they are
referred to as "GND active layers". Similarly, since the active
layers 62h and 62j are connected with the Vcc wire 65b via the Vcc
contacts 64c and 64d, they are referred to as "Vcc active layers".
The poly-silicon layer 63a corresponds to a word line.
[0072] FIG. 6 illustrates an equivalent circuitry of the normal
cell shown in FIG. 4, in which the same reference numerals are used
for corresponding principal parts shown in FIG. 4.
[0073] In FIG. 6, reference numerals 201a and 201b denote a pair of
load transistors, and active regions 62g and 62i corresponds to
source-drain regions of the load transistors.
[0074] FIG. 5 is a pattern of the dummy cell, which is similar to
that shown in FIG. 4, except that no contact corresponding to the
bit line contact 166a is provided, the bit line contact 166e is
substituted for the bit line contact 166b and is connected with the
dummy cell bit line 132a (See FIG. 2.), and no contact
corresponding to the first contacts 67a and 67b is provided.
[0075] FIG. 7 shows an equivalent circuitry of the dummy cell shown
in FIG. 5. In FIG. 7, since the first contact 67a is not provided,
the active region 62g serving as the drain-source region of the
load transistor 201a is not connected with the third-layer metal
wire 65c forming a memory node so that no corresponding connection
wire in the circuitry is provided.
[0076] Also, since the first contact 67b is not provided, the
active region 62i serving as the drain-source region of the load
transistor 201b is not connected with the third-layer metal wire
65d forming a memory node so that no corresponding connection wire
in the circuitry is provided. Thus, the dummy cell cannot
electrically perform the memory operation. As can be seen also in
FIG. 2, the active region 62d is maintained to the GND potential
via the bit line contact 166e.
[0077] According to the present embodiment, each dummy cell has a
memory cell pattern substantially the same as that of each normal
cell. Therefore, a plurality of consecutive patterns can be formed
on the memory cell array so that problems such as malfunction of
normal cells is unlikely caused in photolithography processes due
to inconsecutive patterns.
[0078] FIG. 8 illustrates the patterns beneath the first-layer
metal wire, which correspond to those according to Embodiment 1
shown in FIG. 1. The patterns beneath the first-layer metal wire of
normal cells and dummy cells according to the present embodiment
can be consecutively formed.
[0079] Also, the drain-source regions of the load transistors on
dummy cells are designed to disconnect to memory nodes so that the
dummy cells cannot electrically perform the normal memory
operation. Thus, performance of each normal cell is not to be
influenced because of the incapability of each dummy cell.
[0080] Furthermore, since the drain-source regions of the load
transistors on dummy cell regions are designed to disconnect to the
memory nodes, a current path between Vcc and GND is cut off so that
a redundant current flowing through the dummy cells can be
reduced.
[0081] Moreover, as shown in FIG. 9, the bit line contact 66a,
which connects to the wire maintained to the GND potential, is
provided also with the active layer 62a so that the active region
can be maintained to the GND potential via the bit line contact of
the dummy cell.
[0082] Embodiment 5.
[0083] Referring to FIGS. 10 through 12, Embodiment 5 is described
hereinafter. FIG. 10 is a pattern of the memory cell array
according to Embodiment 5, which is similar to that shown in FIG.
2, except that a set of two dummy cell regions arranged in series
along the row direction shifts by one row every two lines according
to Embodiment 5 as shown in FIG. 10. Meanwhile, according to
Embodiment 2 shown in FIG. 2, the set of four dummy cell regions
arranged in series along the row direction shifts by one row every
four lines. For example, the set of the dummy cell regions
according to Embodiment 5 is located on the first and second lines
at the second row, and on the third and fourth lines at the third
row. The other memory cell regions in FIG. 10 are normal cell
regions, each of which electrically performs the normal memory
operation.
[0084] Also, in the memory cell array shown in FIG. 10, there
provides no dummy cell bit line corresponding to dummy cell bit
line 132a in FIG. 1.
[0085] FIG. 11 shows a pattern of the dummy cell according to
Embodiment 5 beneath the first-layer metal wire, and FIG. 12 shows
an equivalent circuitry of the dummy cell as shown in FIG. 11.
FIGS. 11 and 12 are similar to FIGS. 5 and 6, respectively, except
that since no dummy cell bit line connected with the GND line is
provided, there provides no bit line contact and no contact
corresponding to the bit line contact 166e and the first contact
67c and 67d, respectively.
[0086] The dummy cell according to Embodiment 5, which is not
maintained to the GND potential, nevertheless, provides no adverse
affect the normal cells.
[0087] Embodiment 6.
[0088] Embodiments 1 through 5 of the present invention are
discussed as examples of SRAM in which each memory cell has a pair
of bit lines, however, the present invention can also be applied to
a DRAM (Dynamic Random Access Memory), in which each memory cell
has a single bit line.
[0089] In this case, the dummy memory cell regions should have a
width greater than those of normal cell regions. In particular, a
through-hole connecting between the first-layer and second-layer
bit lines is provided on a normal cell region, and dummy cell
regions are provided adjacent thereto along the line direction. The
width of each dummy cell region may be extended so that the normal
cell regions have no adverse impact due to the connection between
the first-layer and second-layer bit lines.
[0090] Alternatively, as can be seen in FIG. 13, the through-hole
connecting between the first-layer and second-layer bit lines can
be provided on the dummy cell regions so that the normal cell
regions have no adverse impact due to connection between the
first-layer and second-layer. Thus, the through-hole can be
arranged without extending the dimension along the line direction
of each normal cell region.
[0091] According to the aforementioned embodiments, several
examples are discussed, in which the bit lines are composed of the
first-layer and second-layer metal wires, however, the bit lines
may be made of any conductive layers such as poly-silicon wire
layers and silicide layers as well as metal wires.
[0092] In accordance with this regard, the connecting holes between
the first-layer and second-layer metal wires should not be limited
to the through-holes, but may be any ones capable of electrically
connecting therebetween, for example, poly-silicon contacts and
silicide contacts.
[0093] Further, although the first-layer and second-layer bit lines
are described in the above embodiments that they connect
orthogonally to each other, they may connect obliquely or parallel
to each other.
[0094] (Advantages according to the present invention)
[0095] The semiconductor memory device according to the present
invention is so constructed and arranged as described above,
several advantages can be enjoyed as follows.
[0096] According to the first invention, at least one of the memory
cell regions, on which the connecting holes is provided, is the
dummy cell region incapable of electrically performing the memory
operation so that the first-layer and second-layer bit lines can be
connected with each other without an extension of the width along
the line direction of memory cell region of the normal cell capable
of electrically operating as the memory cell.
[0097] According to the second invention, at least one of the
memory cell regions adjacent to the memory cell regions along the
line direction, on which the connecting holes is provided, is the
dummy cell region so that the first-layer and second-layer bit
lines can be connected with each other without an extension of the
width of memory cell region.
[0098] According to the third invention, each memory cell is
connected with a pair of the first-layer bit lines, and one of the
pair of the first-layer bit lines is connected with one of the
second-layer bit lines through the connecting hole arranged within
the dummy cell region, while the another one of the pair of the
first-layer bit lines is connected with one of the second-layer bit
lines through the connecting hole arranged within the normal cell
region, therefore, the first-layer and second-layer bit lines can
be connected with each other without extension of the width of
memory cell regions.
[0099] According to the fourth invention, two or four of the memory
cell regions of the dummy cells are arranged in series along the
row direction so that the memory cell array can be designed in a
simple and regular manner.
[0100] According to the fifth invention, a plurality of dummy cell
bit lines are connected with the dummy cells so as to maintain the
dummy cells to a GND potential, thereby reducing the adverse
affects to the normal cells.
[0101] According to the sixth invention, since each of the dummy
cell bit lines is connected with the GND line, which is extending
along the row direction of the memory cell array, no particular GND
wire region for the dummy cell bit lines should be arranged.
[0102] According to the seventh invention, since each source-drain
region of the load transistor is disconnected with any of the
memory node portions, the dummy cell cannot serve the electrical
memory operation.
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