U.S. patent application number 09/796389 was filed with the patent office on 2001-08-02 for use of blind vias for soldered interconnections between substrates and printed wiring boards.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Armezzani, Gregg J., Desai, Kishor V., Perkins, Jeffery S., Pessarchick, John J..
Application Number | 20010010628 09/796389 |
Document ID | / |
Family ID | 21935290 |
Filed Date | 2001-08-02 |
United States Patent
Application |
20010010628 |
Kind Code |
A1 |
Armezzani, Gregg J. ; et
al. |
August 2, 2001 |
Use of blind vias for soldered interconnections between substrates
and printed wiring boards
Abstract
A method is provided for connecting two conductive layers in an
electronic circuit package comprising the steps of placing one or
more blind vias in a first substrate positioned on top of a first
conductor; placing one or more blind vias in a second substrate
positioned under a second conductor; attaching one or more signal
lines to one or more of the one or more blind vias; and assembling
ball grid array components such that the first conductor is
electrically connected to the second conductor. Also claimed is an
electronic circuit package incorporating the blind vias for
electrical connection between layers in accordance with the present
invention.
Inventors: |
Armezzani, Gregg J.;
(Endwell, NY) ; Desai, Kishor V.; (Fremont,
CA) ; Perkins, Jeffery S.; (Hauppauge, NY) ;
Pessarchick, John J.; (Binghamton, NY) |
Correspondence
Address: |
IBM Corporation, N50/040-4
1701 North Street
Endicott
NY
13760
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
10504
|
Family ID: |
21935290 |
Appl. No.: |
09/796389 |
Filed: |
February 28, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09796389 |
Feb 28, 2001 |
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09415330 |
Oct 8, 1999 |
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09415330 |
Oct 8, 1999 |
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09044966 |
Mar 19, 1998 |
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6023029 |
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Current U.S.
Class: |
361/803 |
Current CPC
Class: |
H05K 2201/10734
20130101; H05K 1/112 20130101; Y10T 29/49117 20150115; Y10T
29/49126 20150115; H05K 1/0298 20130101; Y10T 29/49144 20150115;
H05K 2201/09227 20130101; H05K 2201/09509 20130101 |
Class at
Publication: |
361/803 |
International
Class: |
H05K 001/11; H05K
001/14 |
Claims
What is claimed is:
1. A method for electrically connecting two conductors in an
electronic circuit package comprising the steps of: placing one or
more blind vias in a first substrate positioned on top of a first
conductor; placing one or more blind vias in a second substrate
positioned under a second conductor; attaching one or more signal
lines to one or more of the one or more blind vias; and assembling
ball grid array components such that the first conductor is
electrically connected to the second conductor.
2. The method of claim 1, wherein the first substrate is made of
laminated resin impregnated cloth/metal composite, polyimide/metal
composite, teflon/metal composite, or ceramic/metal composite.
3. The method of claim 1, wherein the second substrate is made of
laminated resin impregnated cloth/metal composite, polyimide/metal
composite, teflon/metal composite, or ceramic/metal composite.
4. The method of claim 1 wherein the second substrate is a
semiconductor device.
5. The method of claim 1, wherein the second substrate is a
laminate chip carrier.
6. The method of claim 1, wherein at least one separate signal line
is connected to each of the one or more blind vias.
7. The method of claim 1, wherein the step of assembling the ball
grid array components further comprises: depositing solder paste
between the first substrate and the second substrate; placing
solder balls in the solder paste between the first substrate and
the second substrate; and reflowing the solder paste.
8. The method of claim 7, wherein the solder paste is water
soluble, no clean, or solvent clean eutectic or non-eutectic alloy
mixtures of solder powder, flux, solvents, and binders.
9. The method of claim 7, wherein the solder balls are C4 solder
balls.
10. The method of claim 7, wherein the width of each blind via is
in the range of 0.002" to 1/4 of the ball diameter of the solder
balls.
11. The method of claim 1, wherein each step is repeated as needed
for the specific application.
12. An electronic circuit package comprising: a first conductor; a
substrate with one or more blind vias positioned on top of the
first conductor; a second conductor; a second substrate with one or
more blind vias positioned under the second conductor; one or more
circuit lines connected to one or more of the blind vias; and a
ball grid array connection electrically connecting the first
conductor to the second conductor using the one or more blind
vias.
13. The electronic circuit package of claim 12, wherein the first
substrate is made of laminated resin impregnated cloth/metal
composite, polyimide/metal composite, polyimide/metal composite,
teflon/metal composite, or ceramic/metal composite.
14. The electronic circuit package of claim 12, wherein the second
substrate is made of laminated resin impregnated cloth/metal
composite, polyimide/metal composite, teflon/metal composite, or
ceramic/metal composite.
15. The electronic circuit package of claim 12, wherein the second
substrate is a semiconductor device.
16. The electronic circuit package of claim 12, wherein at least
one separate signal line is connected to each of the one or more
blind vias.
17. The electronic circuit package of claim 12, wherein the ball
grid array connection further comprises solder and solder
balls.
18. The electronic circuit package of claim 17, wherein the solder
balls are C4 solder balls.
19. The electronic circuit package of claim 17, wherein the solder
is composed of one or more tin/lead alloys.
Description
TECHNICAL FIELD OF THE INVENTION
[0001] The present invention relates to electronic circuit packages
such as printed wiring boards and laminate chip carriers with a
blind via used in place of a land connected to a plated through
hole. The blind via then connects one or more internal layers of
the electronic circuit package to a surface land.
BACKGROUND OF THE INVENTION
[0002] Electronic circuits contain many (sometimes millions) of
components such as resistors, capacitors, inductors, diodes,
electromechanical switches, and transistors. High density packaging
of electronic components is particularly important to allow fast
access to large amounts of data in computers. High density
electronic circuit packages also are important in high frequency
devices and communications devices. The components are connected to
form circuits and circuits are connected to form functioning
devices. The connections perform power and signal distribution. In
a multi-layer electronic circuit package, some layers of the
package serve as conductors and other layers serve as signal
planes, depending on the operational requirements of the device.
The devices require mechanical support and structural protection.
The circuits themselves require electrical energy to function. The
functioning devices, however, produce heat, or thermal energy which
must be dissipated so that the devices do not stop functioning.
Moreover, while high density packaging of a number of components
can improve performance of the device, the heat produced by the
power-consuming components can be such that performance and
reliability of the devices is adversely impacted. The adverse
impact arises from electrical problems such as increased
resistivity and mechanical problems such as thermal stress caused
by increased heat.
[0003] Electronic circuit packages, such as chips, modules, circuit
cards, circuit boards, and combinations of these, thus must meet a
number of requirements for optimum performance. The package must be
structurally sturdy enough to support and protect the components
and the wiring. In addition, the package must be capable of
dissipating heat and must have a coefficient of thermal expansion
that is compatible with that of the components. Finally, to be
commercially useful, the package should be inexpensive to produce
and easy to manufacture.
[0004] High density packages necessarily involve increased wiring
density and thinner dielectric coatings between layers in a
multi-layer electronic circuit package. The layers in a multi-layer
package typically are electrically connected by vias and
through-holes. The term "via" is used for a conductive pathway
between adjacent layers in a multi-layer electronic circuit
package. The term "through-hole" is used for a conductive pathway
that extends to a non-adjacent layer.
[0005] Presently, a widely used technique for achieving such
electrical connection, is to provide vias having a metal plated on
the walls of the vias. However, plating is a relatively expensive
process including the processing steps of cleaning, seeding or
catalyzing the walls and then plating with the desired metal such
as copper. Because of the relative expense associated with plating,
alternatives have been suggested to provide electrical conductivity
in unplated vias, whether through-holes or blind vias. The
alternative methods include providing solder-paste-filled blind
vias, solder balls in blind vias, solder-filled through-holes,
solder rings, and copper powder mixed into solder paste. Each of
these methods depend on the solder bridging unplated/unsoldered
prepreg.
[0006] For high density packages the through-holes are increasingly
narrow in diameter and the through-holes in each layer must be
aligned precisely. The through-holes and vias are likely to be
plated at least where they connect at either end. The routing of
lines in a dense electronic circuit package is made more difficult
by surface joining features that typically are formed as lands
connected to plated through-holes or vias.
[0007] The land and through hole/via features also limit the
density of the interconnect pattern. More particularly, each
conductor site must be separated from other sites by a certain
amount of dielectric material which limits the density of the
sites.
SUMMARY OF THE INVENTION
[0008] It is an object of this invention to provide an electronic
circuit package with blind vias forming electrical connections
between a first conductive layer and a second conductive layer.
[0009] A further object of this invention is to provide an
electronic circuit package that uses blind vias manufactured to
specifications such that the amount of solder from ball grid array
joints that enter the blind vias is limited such that the joint is
not starved for lack of solder.
[0010] A third object of this invention is to provide methods of
fabrication of electronic circuit packages with blind vias forming
electrical connections between a first conductive layer and a
second conductive layer.
[0011] Accordingly, a method is provided for connecting two
conductive layers in an electronic circuit package comprising the
steps of placing one or more blind vias in a first substrate
positioned on top of a first conductor; placing one or more blind
vias in a second substrate positioned under a second conductor;
attaching one or more signal lines to one or more of the one or
more blind vias; and assembling ball grid array components such
that the first conductor is electrically connected to the second
conductor using the blind vias. Also claimed is an electronic
circuit package incorporating the blind vias for electrical
connection between conductive layers in accordance with the present
invention.
[0012] It is an advantage of the present invention that the blind
vias provide electrical connection between two conductive layers of
the electronic circuit package.
[0013] It is a further advantage that the blind vias are
manufactured to be compatible with the use of a ball grid array
that uses solder for the joints of the array.
[0014] It is a further advantage of the invention that the need for
lands separate from the through-holes/vias is eliminated thereby
permitting higher density of electrical connections.
[0015] Other features and advantages of the present invention will
become apparent in the following detailed description of the
preferred embodiment of the invention taken in conjunction with the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a depiction of layers of a multi-layer electronic
circuit package using blind vias for electrical connections, in
accordance with the present invention.
[0017] FIG. 2 is a flow chart of one method of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0018] The present invention is of an electronic circuit package
using blind vias to provide connection between two conductive
circuits. In addition, the blind vias can be manufactured to be
compatible with the use of solder for joints in a ball grid array.
This eliminates the need for lands around the openings of a through
hole/via and, therefore, permits higher density of connections. In
this application the term "blind via" is used to refer to a partial
depth conductive via. The invention can best be understood by
reference to the drawings.
[0019] FIG. 1 illustrates sample layers 10 of an electronic circuit
package in accordance with the present invention. Referring to FIG.
1, at the bottom of the layers 10 is a first conductor 12. On top
of the first conductor 12 is a first substrate 14 such as a printed
wiring board core or subcomposite. The first substrate 14
preferably is composed of a dielectric material such as a laminated
resin impregnated cloth/metal composite, a polyimide/metal
composite, a teflon/metal composite, a ceramic/metal composite, or
other suitable material.
[0020] FIG. 1 shows, as an example, four blind vias, labeled 16,
18, 20, and 22, respectively. The shape of the blind vias 16, 18,
20, and 22 in FIG. 1 is illustrative only. Other shapes are
possible and may be preferable for a given application. The blind
vias can be formed by any standard electronic circuit package
fabrication technique, such as drilling or laser drilling. From
each blind via 16, 18, 20, and 22, extends a corresponding signal
line, labeled 24, 26, 28, and 30, respectively. The direction and
placement of the signal lines is illustrative only. Other
placements and directions are possible and within the scope of the
invention. Multiple signal lines per blind via also are within the
scope of the invention.
[0021] Also shown in FIG. 1 are two solder balls, 32 and 34. The
use of spherical shaped balls in electronic circuit packages is
well-known in the art. With the increase in the number of
input/output leads extending from electronic devices, such as
integrated circuits, ball grid array (BGA) packages have been
developed. A BGA package is a type of packaged electronic device in
which at least one electronic device, such as an integrated circuit
chip, is mounted to a substrate and an electrical connection to an
electrically conductive material not part of the packaged
electronic device, such as a printed circuit board, is made by an
array of solder balls located on a surface of the substrate.
[0022] The solder ball 32 is positioned to cover the openings of
blind vias 16 and 20. The solder ball 34 is positioned to cover the
openings of blind vias 18 and 22. No particular effort is needed to
achieve such positioning. The balls will be naturally held in place
over the openings of the vias. The solder balls 32 and 34 typically
are of BGA size but can be as small as C4 scale, and are composed
of eutectic or high melt tin/lead alloys. Other size solder balls
and solder balls of a different composition are possible and are
within the scope of the invention.
[0023] This invention also applies to other interconnect methods
and materials such as conductive epoxy, gold-to-gold diffusion,
welding, solder paste, and solder plated copper balls.
[0024] Solder (not shown) typically is used at the joints of the
solder balls 32 and 34. The size of the blind vias in comparison to
the solder balls is important and should be structured such that
the amount of solder entering the blind vias is controlled.
Further, the amount of solder used should be sufficient to ensure
that none of the joints are starved for solder if some of the
solder does fall into one or more of the blind vias.
[0025] Located above blind vias 20 and 22 is a second conductor 36.
The blind vias 20 and 22 and signal lines 28 and 30 are in a second
substrate 38 such as a printed wiring board core or laminate chip
carrier or other layers of the electronic circuit package. The
second substrate 38 typically is made of a dielectric such as a
laminated resin impregnated cloth/metal composite, polyimide/metal
composite, teflon/metal composite, ceramic/metal composite, or
other suitable material. Alternatively, the second substrate 38
could be a semiconductor device such as silicon, germanium, or
galliumarsenide. By means of the blind vias, the solder balls, and
the signal lines, the first conductor 12 is electrically connected
to second conductor 36.
[0026] As shown in FIG. 1, using blind vias and solder balls
eliminates the need for lands around the beginning point and ending
point of through-holes and vias. Arrangements such as those in FIG.
1 permit higher density of electrical connections. Also as shown in
FIG. 1, the blind vias are compatible with the use of solder balls
in a ball grid array that uses solder for the joints of the
array.
[0027] The assembly of the layers shown in FIG. 1 is summarized in
FIG. 2, which describes the steps of the method. Namely, once the
first conductor 12 is constructed, the first substrate 14 such as a
printed wiring board/electronic circuit package substrate 14 is
placed on top of the first conductor 12 using any one of many
standard techniques in the industry. Blind vias 16 and 18 then are
placed in the first substrate 14 by drilling, laser drilling, or
any other suitable technique. Signal lines 24 and 26 are attached
to blind vias 16 and 18, respectively.
[0028] Blind vias 20 and 22 are drilled, laser drilled or otherwise
placed in second substrate 38. Signal lines 28 and 30 are attached
to blind vias 20 and 22, respectively. Second conductor 36 is
constructed on second substrate 38.
[0029] The ball grid array components then are assembled with
standard assembly processing, including depositing solder paste
(not shown), placing solder balls such as 32 and 34, and subsequent
reflow. Solder reflow involves the controlled thermal excursion of
the assembly above the melting point of the solder to form an alloy
with the base metal on the components. Upon cooling, this alloy
hardens and forms a fixed conductive (electrical or thermal) path
between circuit lines to interconnect two or more components
together.
[0030] 63/37 is the lowest melt tin/lead alloy. Its melting point
is 183.degree. C.; however, it is typical to exceed this
temperature during reflow to achieve 0.5 to 1.5 minutes duration in
the molten state. This insures good wetting and proper alloying
with the base metal. Typical peak temperatures range from
210-230.degree. C.
[0031] Note that the blind via depth and diameter must be within
limits such that too much solder from the solder paste does not
enter the via. If that occurs, the solder joints may be starved for
solder, which is undesirable. In the preferred embodiment of the
invention, the blind vias are in the range of 0.002" in diameter to
one-fourth of the diameter of the solder balls.
[0032] The depth and diameter of the blind vias also should be
controlled to minimize voiding the blind vias. Proper selection of
the solder paste or solder ball/flux combination and reflow profile
are essential to minimize voiding the blind via. Examples of
suitable solder paste include solvent cleanable, water soluble, or
no clean mixtures of fine tin/lead eutectic alloy solder powder, a
fluxing agent such as polymerized or unpolymerized rosin whose
primary constituent is abietic acid, a suitable solvent such as
tallow alcohol or benzyl alcohol, and any number of non-active
thickener or binder components. However, this will vary depending
on the specific application, the size of the solder balls, and the
width of the blind vias.
[0033] It is important to note that the present invention does not
require filling the blind vias with solder paste. Rather, the
present invention anticipates that the blind vias will be partly
filled with solder paste during the reflow process, but such
partial filling is not required.
[0034] An alternative method for assembly of the ball grid array
components would be to pass the layers 10 through a solder process
prior to the ball grid array assembly process. This could be
accomplished using a process similar to a hot air solder leveling
process. That is, a process where components are dipped or passed
over molten solder and blown off with high incident angle heated
air flow to level the molten solder on the component and remove the
excess. Upon cooling, the component is left with a uniform
protective layer of solder on all exposed metal surfaces.
[0035] Alternatively, the solder paste could be deposited and
reflowed prior to placement of the solder balls of the ball grid
array. The alternative method under certain circumstances could
allow greater control over the placement of solder at the joints
versus inside the blind vias.
[0036] Although specific embodiments have been described herein for
purposes of illustration, various modifications may be made without
departing from the spirit or scope of the invention.
* * * * *