U.S. patent application number 09/747555 was filed with the patent office on 2001-06-28 for method of manufacturing semiconductor device.
Invention is credited to Kim, Jae Kap.
Application Number | 20010005611 09/747555 |
Document ID | / |
Family ID | 19628717 |
Filed Date | 2001-06-28 |
United States Patent
Application |
20010005611 |
Kind Code |
A1 |
Kim, Jae Kap |
June 28, 2001 |
Method of manufacturing semiconductor device
Abstract
Provided is, a method of manufacturing a semiconductor device
having a stacked capacitor configured to reduce a step difference
between a memory cell region and a logic circuit region adjacent
thereto. In the method of manufacturing a semiconductor device, a
sacrificial film removed after formation of the semiconductor
device having a stacked capacitor, is preserved in the logic
circuit region to be used as an interlayer insulating film. Thus, a
step difference between a memory cell region having the capacitor
and a logic circuit region, is removed, thereby facilitating
formation of multi-layered interconnection wirings formed after
forming the capacitor, and attaining fineness of the
interconnection wirings.
Inventors: |
Kim, Jae Kap; (Kyoungki-do,
KR) |
Correspondence
Address: |
Timothy J. Keefer
Wildaman, Harrold, Allen & Dixon
225 West Wacker Drive
Chicago
IL
60606
US
|
Family ID: |
19628717 |
Appl. No.: |
09/747555 |
Filed: |
December 22, 2000 |
Current U.S.
Class: |
438/239 ;
257/E21.019; 257/E21.648; 257/E21.66; 257/E27.088; 438/241;
438/258; 438/266 |
Current CPC
Class: |
H01L 27/10894 20130101;
H01L 27/10852 20130101; H01L 27/10814 20130101; H01L 28/91
20130101 |
Class at
Publication: |
438/239 ;
438/241; 438/258; 438/266 |
International
Class: |
H01L 021/8242; H01L
021/336 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 23, 1999 |
KR |
99-61042 |
Claims
What is claimed is:
1. A method of manufacturing a semiconductor device having a logic
circuit region, a transistor having a gate electrode, and
source/drain electrodes, and a memory cell region having a stacked
capacitor structure, the method comprising the steps of: a first
step of forming a first contact plug connected to the drain
electrode, and forming a bit line connected to the source electrode
and a first interconnection wiring connected to the respective
electrodes in the logic circuit region; a second step of forming a
second contact plug connected to the first contact plug; a third
step of flatly forming an interlayer insulating film over the
resultant structure having the second contact plug; a fourth step
of forming a contact partially exposing an the upper portion of the
first interconnection wiring by partially removing the interlayer
insulating film, and forming a second interconnection wiring by
filling up the contact with a conductive material; a fifth step of
producing a space where a stacked capacitor is to be formed, by
selectively removing a portion of the interlayer insulating film in
the memory cell region, forming a charge preservation electrode on
the side wall of the interlayer insulating film, and then removing
the portion of the interlayer insulating film in the memory cell; a
sixth step of forming a dielectric film and an upper electrode on
the charge preservation electrode; and a seventh step of flatly
forming an interlayer insulating film on the resultant
structure.
2. The method according to claim 1, wherein the first step
comprises the sub-steps of: flatly forming a first interlayer
insulating film on the resultant structure having the gate
electrode, the source electrode and the drain electrode; forming a
contact exposing the upper portion of the drain electrode formed in
the memory cell region by partially removing the first interlayer
insulating film formed in the memory cell region; forming the first
contact plug by filling up the contact with a first conductive
material; forming a second interlayer insulating film on the
resultant structure having the first contact plug; forming contacts
exposing the upper portion of the respective electrodes in the
logic circuit region and the upper portion of the first contact
plug formed on the source electrode in the memory cell region or
forming a contact exposing the upper portion of the source
electrode, by partially removing the second and first interlayer
insulating films in sequence; flatly forming a second conductive
material and a first intermediate insulating film in sequence by
filling up the contacts; and forming a bit line exposing the upper
portion of the first contact plug formed on the drain electrode by
partially removing the first intermediate insulating film and the
second conductive material in sequence, and forming the bit line
and first interconnection wiring by flatly forming a third
interlayer insulating film and a first etching stopper film on the
resultant structure.
3. The method according to claim 2, further comprising the step of
forming an oxide film over the first etching stopper film.
4. The method according to claim 2, wherein the second step
comprises the sub-steps of: forming a contact exposing the upper
portion of the first contact plug formed on the drain electrode by
partially removing the first etching stopper film and the third
interlayer insulating film; forming a third conductive material on
the resultant structure to fill up the contact; and forming the
second contact plug by flatly removing the third conductive
material by an etch-back process.
5. The method according to claim 4, wherein the fourth step
comprises the sub-steps of: forming a contact exposing the upper
portion of the first interconnection wiring by partially removing
the interlayer insulating film, the first etching stopper film, the
third interlayer insulating film and the first intermediate
insulating film in sequence by an etching process; forming a
concavity by partially removing the interlayer insulating film
having the contact by an etching process; forming a fourth
conductive material to fill up the contact and concavity; and
forming the second interconnection wiring by flatly removing the
fourth conductive material formed on the interlayer insulating film
by an etch-back process.
6. The method according to claim 4, wherein the fourth step
comprises the sub-steps of: forming a concavity by partially
removing the interlayer insulating film formed in the logic circuit
region by an etching process; forming a contact exposing the upper
portion of the first interconnection wiring by partially removing
the interlayer insulating film of the portion where the concavity
is formed, the first etching stopper film, the third interlayer
insulating film and the first intermediate insulating film in
sequence by an etching process; forming a fourth conductive
material to fill up the contact and concavity; and forming the
second interconnection wiring by flatly removing the fourth
conductive material formed on the interlayer insulating film by an
etch-back process.
7. The method according to claim 5, wherein the fifth step
comprises the sub-steps of: forming a fifth interlayer insulating
film over the resultant structure having the second interconnection
wiring; forming a pattern by partially removing the fifth and
fourth interlayer insulating films formed in the memory cell region
by an etching process; forming a conductive material for a charge
preservation electrode having a predetermined thickness over the
resultant structure having the pattern; and forming a
photosensitive film on the conductive material for a charge
preservation electrode formed in the logic circuit region.
8. The method according to claim 7, wherein the sixth step
comprises the sub-steps of: etching the exposed conductive material
for a charge preservation electrode formed in the logic circuit
region to a predetermined thickness; forming a cylindrical charge
preservation electrode in the memory cell region by removing the
fifth and fourth interlayer insulating films remaining on the
memory cell region and removing the photosensitive film formed in
the logic circuit region to expose the upper portion of the second
contact plug; forming a capacitor dielectric film having a
predetermined thickness along the step difference on the charge
preservation electrode; forming a conductive material for a plate
electrode on the charge preservation electrode by filling up the
inside of the cylindrical charge preservation electrode; and
forming a plate electrode by sequentially removing the conductive
material for a plate electrode formed in the logic circuit region,
the capacitor dielectric film and the conductive material for a
charge preservation electrode.
9. A method of manufacturing a semiconductor device having a logic
circuit region, a transistor having a gate electrode, and
source/drain electrodes, and a memory cell region having a stacked
capacitor structure, the method comprising the steps of: a first
step of forming a first contact plug connected to the drain
electrode, and forming a bit line connected to the source electrode
and a first interconnection wiring connected to the respective
electrodes in the logic circuit region; a second step of forming a
second contact plug connected to the first contact plug; a third
step of flatly forming an interlayer insulating film over the
resultant structure having the second contact plug; a fourth step
of producing a space where a stacked capacitor is to be formed, by
selectively removing a portion of the interlayer insulating film in
the memory cell region, forming a charge preservation electrode on
the side wall of the interlayer insulating film, and then removing
the portion of the interlayer insulating film in the memory cell; a
fifth step of forming a dielectric film and an upper electrode on
the charge preservation electrode; and a sixth step of flatly
forming an interlayer insulating film on the resultant
structure.
10. The method according to claim 9, wherein the first step
comprises the sub-steps of: flatly forming a first interlayer
insulating film on the resultant structure having the gate
electrode, the source electrode and the drain electrode; forming a
contact exposing the upper portions of the source and drain
electrodes formed in the memory cell region by partially removing
the first interlayer insulating film formed in the memory cell
region; forming the first contact plug by filling up the contact
with a first conductive material; forming a second interlayer
insulating film on the resultant structure having the first contact
plug; forming contacts exposing the upper portion of the respective
electrodes in the logic circuit region and the upper portion of the
first contact plug formed on the source electrode in the memory
cell region or forming a contact exposing the upper portion of the
source electrode, by partially removing the second and first
interlayer insulating films in sequence; flatly forming a second
conductive material and a first intermediate insulating film in
sequence by filling up the contacts; and forming a bit line
exposing the upper portion of the first contact plug formed on the
drain electrode by partially removing the first intermediate
insulating film and the second conductive material in sequence, and
forming the bit line and first interconnection wiring by flatly
forming a third interlayer insulating film and a first etching
stopper film on the resultant structure.
11. The method according to claim 10, wherein the first step
comprises the sub-steps of: flatly forming a first interlayer
insulating film on the resultant structure having the gate
electrode, the source electrode and the drain electrode; forming a
contact exposing the upper portions of the source and drain
electrodes formed in the memory cell region by partially removing
the first interlayer insulating film formed in the memory cell
region; forming the first contact plug by filling up the contact
with a first conductive material; forming a second interlayer
insulating film on the resultant structure having the first contact
plug; forming contacts exposing the upper portion of the respective
electrodes in the logic circuit region and the upper portion of the
first contact plug formed on the source electrode in the memory
cell region or forming a contact exposing the upper portion of the
source electrode, by partially removing the second and first
interlayer insulating films in sequence; flatly forming a second
conductive material and a first intermediate insulating film in
sequence by filling up the contacts; and forming a bit line
exposing the upper portion of the first contact plug formed on the
drain electrode by partially removing the first intermediate
insulating film and the second conductive material in sequence, and
forming the bit line and first interconnection wiring by flatly
forming a third interlayer insulating film and a first etching
stopper film on the resultant structure.
12. The method according to claim 10, further comprising the step
of forming an oxide film over the first etching stopper film.
13. The method according to claim 10, wherein the second step
comprises the sub-steps of: forming a contact exposing the upper
portion of the first contact plug formed on the drain electrode by
partially removing the first etching stopper film and the third
interlayer insulating film; forming a third conductive material on
the resultant structure to fill up the contact; and forming the
second contact plug by flatly removing the third conductive
material by an etch-back process.
14. The method according to claim 13, wherein the fourth step
comprises the sub-steps of: forming a fifth interlayer insulating
film over the resultant structure having the second interconnection
wiring; forming a pattern by partially removing the fifth and
fourth interlayer insulating films formed in the memory cell region
by an etching process; forming a conductive material for a charge
preservation electrode having a predetermined thickness over the
resultant structure having the pattern; and forming a
photosensitive film on the conductive material for a charge
preservation electrode formed in the logic circuit region.
15. The method according to claim 14, wherein the fifth step
comprises the sub-steps of: etching the exposed conductive material
for a charge preservation electrode formed in the logic circuit
region to a predetermined thickness; forming a cylindrical charge
preservation electrode in the memory cell region by removing the
fifth and fourth interlayer insulating films remaining on the
memory cell region and removing the photosensitive film formed in
the logic circuit region to expose the upper portion of the second
contact plug; forming a capacitor dielectric film having a
predetermined thickness along the step difference on the charge
preservation electrode; forming a conductive material for a plate
electrode on the charge preservation electrode by filling up the
inside of the cylindrical charge preservation electrode; and
forming a plate electrode by sequentially removing the conductive
material for a plate electrode formed in the logic circuit region,
the capacitor dielectric film and the conductive material for a
charge preservation electrode.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method of manufacturing a
semiconductor device, and more particularly, to a method of
manufacturing a semiconductor device configured to reduce a step
difference between a memory cell region and a logic circuit region
adjacent thereto, thereby attaining fineness of interconnection
wirings.
[0003] 2. Description of the Related Art
[0004] Recently, in accordance with high integration and high
performance of a semiconductor device, the cell size is gradually
reduced. Accordingly, the height of a stacked capacitor provided in
a semiconductor device becomes increased so as to cope with the
reduced cell size and to attain a required secured capacitance.
[0005] In other words, in order to compensate for a reduction in
the surface area of a dielectric corresponding to the reduced cell
size, the height of a stacked capacitor is increased, resulting in
a relatively large step difference between a memory cell region
where the capacitor is formed, and a logic circuit region adjacent
thereto.
[0006] A method of manufacturing a conventional semiconductor
device will be described with reference to FIG. 1.
[0007] FIG. 1 is a cross-sectional view illustrating a method of
manufacturing a conventional semiconductor device.
[0008] According to the method of manufacturing a conventional
semiconductor device, as shown in FIG. 1, a predetermined logic
circuit is formed on a logic circuit region A on a semiconductor
substrate 10, and a first etching stopper film 11 is formed on a
memory cell region B by depositing nitride on the entire surface
where a plurality of transistors for driving a capacitor to be
formed in a subsequent process, are formed.
[0009] Then, oxide is stacked on the first etching stopper film 11
and then planarized by a chemical mechanical polishing (CMP)
process, thereby forming a first interlayer insulating film 21.
[0010] Here, reference numeral 1 denotes a well of first
conductivity type (e.g., an n-type), 2 denotes a well of a second
conductivity type (e.g., a p-type), 3 denotes an isolation
insulating layer, 4 denotes an active region used as a source
electrode 4a or a drain electrode 4b, 5 denotes a gate oxide layer,
6 denotes a gate electrode, and 7 denotes an intermediate
insulating film.
[0011] Subsequently, a first contact hole (not shown) exposing the
drain electrode 4b in the memory cell region B is formed by
partially removing the first interlayer insulating film 21 of the
memory cell region B and the first etching stopper film 11.
[0012] Next, the first contact hole is filled with a conductive
material (e.g., polysilicon), and then the conductive material
remaining on the first interlayer insulating film 21 is removed by
an etch-back process, thereby forming a first contact plug 31.
[0013] Here, the first contact plug 31 formed in the drain
electrode 4b of the memory cell region B is electrically connected
to a charge preservation electrode in a subsequent process.
[0014] Also, when the drain electrode 4b in the memory cell region
B is exposed, the source electrode 4a may also be exposed to form a
contact plug, for forming a bit line contact in the contact plug
during a subsequent process.
[0015] Subsequently, oxide is deposited on the entire surface of
the structure having the first contact plug 31, thereby forming a
second interlayer insulating film 22.
[0016] Next, the second interlayer insulating film 22, the first
interlayer insulating film 21 and the first etching stopper film 11
are partially removed in sequence, thereby forming a second contact
hole exposing the source electrode 4a in the memory cell region B
to be connected with a bit line during a subsequent process, the
active region 4 in the logic circuit region A to be connected with
a first interconnection wiring, and the surface of the gate
electrode 6.
[0017] Here, in the case where a contact plug is also formed in the
source electrode 4a in the above-described process, the second
contact hole for a bit line is formed on the contact plug.
[0018] Then, a conductive material is deposited over the second
contact hole and on the second interlayer insulating film 22 to
form a first conductive layer 41a and 41b, and then an insulating
material is deposited on the entire surface of the first conductive
layer 41a and 41b to form a second intermediate insulating film
25.
[0019] Here, the first conductive layer is patterned in a
subsequent process, so that the first conductive layer 41a
remaining in the logic circuit region A is used as an
interconnection wiring and the first conductive layer 41b remaining
in the memory cell region B is used as a bit line.
[0020] Thereafter, the second intermediate insulating film 25, the
first conductive layer 41b and the second interlayer insulating
film 22 disposed under the first conductive layer 41b, are
patterned to form the interconnection wiring and the bit line.
[0021] Here, the second interlayer insulating film 22 is patterned
to expose the surface of the first contact plug 31 or to allow the
second interlayer insulating film 22 to be partially left over.
[0022] Next, nitride is deposited on the entire surface of the
resultant structure to form a second etching stopper film 12, and
an oxide film 24 is then deposited on the entire surface of the
second etching stopper film 12 and planarized by a CMP process,
thereby forming a third interlayer insulating film 23.
[0023] Subsequently, the second interlayer insulating film 22, the
second etching stopper film 12 and the third interlayer insulating
film 23 on the memory cell region B, are selectively removed to
form a second contact plug 42 on the first contact plug 31.
[0024] Thereafter, a conductive material for a dielectric film and
a conductive material for an upper electrode are sequentially
deposited on the resultant structure, and then patterned to form a
dielectric film 45 and an upper electrode 47.
[0025] Subsequently, an interlayer insulating film 49 is formed on
the resultant structure, thereby completing a semiconductor
device.
[0026] As described above, in the conventional semiconductor device
manufacturing method, a step difference between the memory cell
region B and the logic circuit region A adjacent thereto becomes
severe.
[0027] Also, in the logic circuit region A formed in the vicinity
of a capacitor, the line width of a wiring is reduced and the
wiring space becomes narrower in accordance with high integration
of a semiconductor device.
[0028] In order to increase the integration density, as the wiring
is formed in multiple layers, the number of interconnection wirings
for electrically connecting the multi-layered wiring increases.
[0029] While it is necessary to more accurately form patterns in
the logic circuit region A for attaining high integration, the step
difference caused by a capacitor becomes gradually severe. Thus, it
is quite difficult to pattern layers formed after forming the
capacitor, e.g., interconnection wirings.
[0030] In other words, according to the conventional method for
forming a stacked capacitor, a large step difference between a
memory cell region and a logic circuit region adjacent thereto
makes it difficult to achieve fine interconnection wirings formed
after forming the stacked capacitor. Also, the large step
difference makes it difficult to form multi-layered interconnection
wirings in the logic circuit region.
SUMMARY OF THE INVENTION
[0031] To solve the above problems, it is an object of the present
invention to provide a method of manufacturing a semiconductor
device, which can reduce a step difference between a memory cell
region and a logic circuit region adjacent thereto.
[0032] It is another object of the present invention to provide a
method of manufacturing a semiconductor device, which can attain
fineness of interconnection wirings by simply forming multi-layered
interconnection wirings. Accordingly, to achieve the first object,
there is provided a method of manufacturing a semiconductor device
having a logic circuit region, a transistor having a gate
electrode, and source/drain electrodes, and a memory cell region
having a stacked capacitor structure, the method including the
steps of a first step of forming a first contact plug connected to
the drain electrode, and forming a bit line connected to the source
electrode and a first interconnection wiring connected to the
respective electrodes in the logic circuit region, a second step of
forming a second contact plug connected to the first contact plug,
a third step of flatly forming an interlayer insulating film over
the resultant structure having the second contact plug, a fourth
step of forming a contact partially exposing an the upper portion
of the first interconnection wiring by partially removing the
interlayer insulating film, and forming a second interconnection
wiring by filling up the contact with a conductive material, a
fifth step of producing a space where a stacked capacitor is to be
formed, by selectively removing a portion of the interlayer
insulating film in the memory cell region, forming a charge
preservation electrode on the side wall of the interlayer
insulating film, and then removing the portion of the interlayer
insulating film in the memory cell, a sixth step of forming a
dielectric film and an upper electrode on the charge preservation
electrode, and a seventh step of flatly forming an interlayer
insulating film on the resultant structure.
[0033] To achieve the second object, there is provided a method of
manufacturing a semiconductor device having a logic circuit region,
a transistor having a gate electrode, and source/drain electrodes,
and a memory cell region having a stacked capacitor structure, the
method including the steps of a first step of forming a first
contact plug connected to the drain electrode, and forming a bit
line connected to the source electrode and a first interconnection
wiring connected to the respective electrodes in the logic circuit
region, a second step of forming a second contact plug connected to
the first contact plug, a third step of flatly forming an
interlayer insulating film over the resultant structure having the
second contact plug, a fourth step of producing a space where a
stacked capacitor is to be formed, by selectively removing a
portion of the interlayer insulating film in the memory cell
region, forming a charge preservation electrode on the side wall of
the interlayer insulating film, and then removing the portion of
the interlayer insulating film in the memory cell, a fifth step of
forming a dielectric film and an upper electrode on the charge
preservation electrode, and a sixth step of flatly forming an
interlayer insulating film on the resultant structure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0034] The above object and advantages of the present invention
will become more apparent by describing in detail a preferred
embodiment thereof with reference to the attached drawings in
which:
[0035] FIG. 1 is a cross-sectional view illustrating a conventional
method of a semiconductor device;
[0036] FIGS. 2 through 10 are cross-sectional views illustrating
processing steps of a method of manufacturing a semiconductor
device according to an embodiment of the present invention;
[0037] FIGS. 11 through 13 are cross-sectional views illustrating
processing steps of a method of manufacturing a semiconductor
device according to another embodiment of the present
invention;
[0038] FIG. 14 is a cross-sectional view illustrating a method of
manufacturing a semiconductor device according to a still another
embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0039] Preferred embodiments of the present invention will now be
described in detail with reference to the accompanying
drawings.
[0040] FIGS. 2 through 10 are cross-sectional views illustrating
processing steps of a method of manufacturing a semiconductor
device according to an embodiment of the present invention.
[0041] In method of manufacturing a semiconductor device according
to an embodiment of the present invention, as shown in FIG. 2,
logic circuits are formed in a logic circuit region A of a
semiconductor substrate 100 in subsequent processing steps, and a
transistor and a stacked capacitor are formed in a memory cell
region B, respectively.
[0042] In other words, logic circuit elements and transistors
having an isolation insulating film 102, p- and n-type wells 104,
106a and 106b, a gate insulating film 108, gate electrodes 110a and
110, source electrodes 113a and 113 and drain electrodes 113b and
113, are formed in the logic circuit region A and the memory cell
region B.
[0043] Next, a first intermediate insulating film 112 is formed on
the gate electrodes 110a and 110. A first etching stopper film 114
having a predetermined thickness according to a step difference, is
formed on the isolation insulating film 102, the source and drain
electrodes 113, 113a and 113b and the first intermediate insulating
film 112. A first interlayer insulating film 116 is flatly formed
on the first etching stopper film 114. Here, a bit line to be
formed in a subsequent process is connected to the source electrode
113a of the memory cell region B, and a capacitor is connected to
the drain electrode 113b.
[0044] An oxide or nitride film may be used as the first
intermediate insulating film 112. Also, a nitride layer and an
oxide layer may be used as the first etching stopper film 114 and
the first interlayer insulating film 116, respectively.
[0045] Here, after thickly forming an insulating film (oxide film),
the first interlayer insulating film 116 can be planarized by
uniformly removing some of the insulating film by a CMP
process.
[0046] Formation of the cross-sectional structure of a
semiconductor device shown in FIG. 2 can be achieved by known
methods in the art, and can easily realized by conventional
techniques. Thus, a detailed explanation of specific processes for
forming multiple layers (or films) will not be given in this
embodiment.
[0047] Next, as shown in FIG. 3, in the memory cell region B,
contacts are formed on the source electrode 113a to be connected
with a bit line and on the drain electrode 113b to be connected
with a capacitor. That is, the first interlayer insulating film 116
is etched by an etching process in which a contact mask (not shown)
and the first etching stopper film 114 are used as etching
barriers, and the first etching stopper film 114 is partially
removed, thereby forming contacts (not shown) exposing the upper
portions of the source and drain electrodes 113a and 113b.
[0048] Thereafter, the thus-formed contacts are filled by deposit a
conductive material, e.g., silicon, thereon, and the conductive
material formed on the first interlayer insulating film 116 is
removed by an etch-back process using an etching gas or by a CMP
process, thereby forming a first contact plug 118 on the source and
drain electrodes 113a and 113b of the memory cell region B.
[0049] Subsequently, oxide is deposited over the entire surface of
the resultant structure having the first interlayer insulating film
116 and the first contact plug 118, thereby flatly forming a second
interlayer insulating film 120.
[0050] Although it has been described in this embodiment that
contacts and a contact plug are simultaneously formed on the source
electrode 113a to be connected with a bit line and on the drain
electrode 113b to be connected with a capacitor, the present
invention is not limited thereto. Alternatively, a contact and a
contact plug may be first formed only on the drain electrode 113b
and then a contact may be formed on the source electrode 113a when
a bit line contact is formed.
[0051] Thereafter, a contact is formed in the first contact plug
118 on the source electrode 113a to be connected with the bit line,
and contacts are formed on source and drain electrodes 113 and the
gate electrode 110 of the logic circuit region A to be connected
with the first interconnection wiring.
[0052] Subsequently, as shown in FIG. 4, a conductive material 122
and a second intermediate insulating film 124 are sequentially
formed on the second interlayer insulating film 120 having the
contact.
[0053] Here, the contacts formed in the source and drain electrodes
113 of the logic circuit region A may be self-aligned such that the
second interlayer insulating film 120 and the first interlayer
insulating film 118 are etched using a contact mask (not shown) and
the first etching stopper film 114 as etching barriers and the
first etching stopper film 114 is then etched.
[0054] Also, the conductive material 122 is used as a bit line in
the memory cell region B and is used as a first interconnection
wiring in the logic circuit region A. A stacked structure of
titanium/titanium nitride/tungsten (Ti/TiN/W) is preferably used as
the conductive material 122.
[0055] Otherwise, in the case where contacts and the first contact
plug are not formed on the source electrode 113a to be connected
with a bit line, the contacts may be simultaneously formed on the
source electrode 113a to be connected with a bit line when the
contacts are formed on the source and drain electrodes 113 of the
logic circuit region A in a self-aligned manner.
[0056] Next, as shown in FIG. 5, the second intermediate insulating
film 124 and the conductive material 122 are etched by performing a
photolithography process.
[0057] Subsequently, the second interlayer insulating film 120 is
partially etched to expose the upper portion of the first contact
plug 118 formed in the drain electrode 113b of the memory cell
region B, thereby forming a bit line connected to the source
electrode 113a of the memory cell region B and a first
interconnection wiring connected to the source and drain electrodes
113 and the gate electrode 110b of the logic circuit region A.
Here, the second interlayer insulating film 120 may be etched to be
left thinly without exposing the upper portion of the first contact
plug 118.
[0058] Subsequently, a second etching stopper film 126 having a
predetermined thickness is formed on the resultant structure having
the upper portion of the first contact plug 118 formed on the drain
electrode 113b exposed, in accordance with the step difference. A
third interlayer insulating film 128 is flatly formed on the second
etching stopper film 126, and then a third etching stopper film 130
is formed on the third interlayer insulating film 128.
[0059] Here, a nitride film is preferably used as the second and
third etching stopper films 126 and 130, and an oxide film is
preferably used as the third interlayer insulating film 128. The
third interlayer insulating film 128 can be flatly formed such that
an insulating film is thickly formed and then some of the upper
portion of the insulating film is uniformly removed by a CMP
process.
[0060] Unlike the above, in this embodiment, an oxide film having a
predetermined thickness may be formed on the third etching stopper
film 130. This is for preventing the third etching stopper film 130
from being damaged when a second contact plug is formed on the
first contact plug connected to the drain electrode 113b of the
memory cell region B during a subsequent process.
[0061] Next, as shown in FIG. 6, the third etching stopper film 130
over the drain electrode 113b is etched by an etching process using
a contact mask (not shown), the third interlayer insulating film
128 is etched by an etching process using the second etching
stopper film 126 as an etching barrier, and the second etching
stopper film 126 is etched to form a contact (not shown) exposing
the upper surface of the first contact plug 118 formed on the drain
electrode 113b.
[0062] Subsequently, a conductive material filling up the contact
is deposited on the entire surface of the resultant structure, and
then the conductive material formed on the third etching stopper
film 130 is removed by an etch-back process, e.g., using an etching
gas or by a CMP process, thereby forming a second contact plug 132
connected to the first contact plug 118.
[0063] Next, as shown in FIG. 7, a fourth interlayer insulating
film 134 is formed over the entire surface of the resultant
structure having the second contact plug 132 and the fourth
interlayer insulating film 134, the third etching stopper film 130,
the third interlayer insulating film 128, the second etching
stopper film 126 and parts of the second intermediate insulating
film 124 are sequentially removed using a photolithography process,
thereby forming a contact (not shown) exposing the upper surface of
the first interconnection wiring 122b.
[0064] Here, whereas the fourth interlayer insulating film 134
formed of an oxide film, is used as an interlayer insulating film
in the logic circuit region A, it is used as a sacrificial film
during formation of a capacitor in the memory cell region B.
[0065] Subsequently, a conductive material for a second
interconnection wiring is formed over the entire surface of the
resultant structure having the contact to a predetermined
thickness, to fill up the contact, and the residual upper portion
of the fourth interlayer insulating film 134 is exposed by a CMP
process or an etch-back process using etching gas, thereby forming
a second interconnection wiring 136 connected to the first
interconnection wiring 122b.
[0066] In this embodiment, the contact exposing parts of the upper
portion of the first interconnection wiring 122b, is first formed,
and a concavity in which the second interconnection wiring 136 is
to be formed, is then formed. However, even though the formation
sequence is reversed, the same result can be obtained. Unlike the
above, in this embodiment, after a capacitor may be formed in the
memory cell region B without formation of the second
interconnection wiring 136, the second interconnection wiring 136
may be formed in the logic circuit region A. This is particularly
advantageously used in the case where a capacitor is not relatively
high.
[0067] As shown in FIG. 8, a fifth interlayer insulating film 138
is formed over the entire surface of the resultant structure having
the second interconnection wiring 136. The fifth and fourth
interlayer insulating films 138 and 134 are partially removed in
sequence by an etching process using a mask (not shown) for a
charge preservation electrode to be patterned. Here, each one
pattern corresponding to a unit cell is formed in the memory cell
region B. The fifth and fourth interlayer insulating films 138 and
134 are preserved as they are in the logic circuit region A having
the second interconnection wiring 136, while the fifth and fourth
interlayer insulating films 138 and 134 existing on the interface
between the memory cell region B and the logic circuit region A,
are removed.
[0068] Subsequently, a conductive material 140 for a charge
preservation electrode having a predetermined thickness is formed
over the entire surface of the resultant structure having the
patterned fifth interlayer insulating film 138, along the step
difference, and then a photosensitive film 142 is coated over the
conductive material 140 for a charge preservation electrode in the
logic circuit region A.
[0069] Thereafter, the conductive material 140 for a charge
preservation electrode is anisotrophically etched using the
photosensitive film 142 as a mask so as to be left on the fifth
interlayer insulating film 138 and on the side walls of the fourth
interlayer insulating film 134.
[0070] Then, the photosensitive film 142 is removed, and the fifth
and fourth interlayer insulating films 138 and 134 remaining on the
memory cell region B are removed using the third etching stopper
film 130 and the conductive material 140 for a charge preservation
electrode in the logic circuit region A as etching barriers,
thereby forming a cylindrical charge preservation electrode 140a
connected to the second contact plug 132.
[0071] Next, as shown in FIG. 9, a capacitor dielectric film 144
having a predetermined thickness is formed over the entire surface
of the resultant structure having the charge preservation electrode
140a, and a conductive material 146 for a plate electrode is formed
over the entire surface of the capacitor dielectric film 144.
[0072] Subsequently, as shown in FIG. 10, the conductive material
156 for a plate electrode formed in the logic circuit region A, the
capacitor dielectric film 144 and the conductive material 140 for a
charge preservation electrode are sequentially etched by an etching
process using a plate electrode mask (not shown), thereby forming a
plate electrode 146a in the memory cell region B.
[0073] Thereafter, a sixth interlayer insulating film 148 is formed
flatly on the resultant structure having the plate electrode 146a
and then a third interconnection wiring 150 connected to the second
interconnection wiring 136, thereby completing a semiconductor
device having a stacked capacitor.
[0074] According to the above-described embodiment of the present
invention, unlike the conventional semiconductor device having a
large step difference between a memory cell region B and a logic
circuit region A adjacent thereto, a sacrificial film removed in
the course of forming a capacitor is preserved in a logic circuit
region to be used as an interlayer insulating film, thereby
completely removing a step difference between a memory cell region
and the logic circuit region. Therefore, fineness of
interconnection wirings formed over the capacitor can be
effectively realized, and formation of multi-layered
interconnections can be easily realized.
[0075] A method of manufacturing a semiconductor device according
to another embodiment of the present invention will now be
described in detail.
[0076] FIGS. 11 through 13 are cross-sectional views illustrating
processing steps of a method of manufacturing a semiconductor
device according to another embodiment of the present
invention.
[0077] In the method of manufacturing a semiconductor device
according to another embodiment of the present invention, as shown
in FIG. 11, a transistor having a gate electrode 210a and
source/drain electrodes 213a and 213b is formed, and a bit is then
formed to expose the upper surface of a first contact plug 218.
[0078] Then, a second etching stopper film 226 and a third
interlayer insulating film 228 are flatly formed over the entire
surface of the resultant structure, and a third etching stopper
film 230 is formed on the third interlayer insulating film 228,
which is the substantially same as in the first embodiment of the
present invention.
[0079] Subsequently, as shown in FIG. 11, in a state in which the
third etching stopper film 230 is formed on the third interlayer
insulating film 228, the third etching stopper film 230 over the
drain electrode 213b is etched by an etching process using a
contact mask (not shown) and the third interlayer insulating film
228 is etched by an etching process using the contact mask and the
second etching stopper film 226 as etching barriers.
[0080] Thereafter, the second etching stopper film 226 is etched
using a mask (not shown) for etching an etching stopper film to
form a contact (not shown) exposing the upper surface of the first
contact plug 218.
[0081] Subsequently, a conductive material is deposited to fill up
the thus-formed contact and then patterned to allow the conductive
material formed in the memory cell region B to be left over and to
remove the conductive material formed in the logic circuit region
A, thereby forming a second contact plug 232 connected to the first
contact plug 218.
[0082] Here, unlike the first embodiment, two neighboring second
contact plugs 232 each connected to the first contact plug 218 on
the drain electrode 213b are connected to each other.
[0083] Next, as shown in FIG. 12, a fourth interlayer insulating
film 234 is formed on the resultant structure having the second
contact plug 232. The fourth interlayer insulating film 234, the
third etching stopper film 230, the third interlayer insulating
film 228, the second etching stopper film 226 and parts of the
second intermediate insulating film 224 are sequentially removed by
a photolithography process, thereby forming a contact (not shown)
exposing the upper portion of the first interconnection wiring 222b
in the logic circuit region A.
[0084] Subsequently, the fourth interlayer insulating film 234 is
etched to a predetermined thickness by a photolithography process,
thereby forming a concavity to be used as a second interconnection
wiring by a subsequent process.
[0085] Here, whereas the fourth interlayer insulating film 234
formed of oxide is used as an interlayer insulating film in the
logic circuit region A, it is used as a sacrificial film during
formation of a capacitor, in the memory cell region B.
[0086] Next, a conductive material for a second interconnection
wiring is formed on the resultant structure having the contact (not
shown) and the concavity (not shown) to a predetermined thickness
to fill up the contact and concavity, and then the remaining upper
portion of the fourth interlayer insulating film 234 is exposed by
a CMP process or an etch-back process using an etching gas, thereby
forming a second interconnection wiring 236.
[0087] In this embodiment, it has been described that the contact
(not shown) partially exposing the upper portion of the first
interconnection wiring 222b is first formed and the concavity (not
shown) where the second interconnection wiring 236 is to be formed,
is then formed. However, even if the formation sequence is
reversed, the same result can be obtained. Unlike the above, in
this embodiment, after a capacitor may be first formed in the
memory cell region B without formation of the second
interconnection wiring 236, the second interconnection wiring 236
may be formed in the logic circuit region A. This is particularly
advantageously used in the case where a capacitor is not relatively
high.
[0088] As shown in FIG. 13, a fifth interlayer insulating film 238
is formed over the entire surface of the resultant structure having
the second interconnection wiring 236. The fifth and fourth
interlayer insulating films 238 and 234 are partially removed in
sequence by an etching process using a mask (not shown) for a
charge preservation electrode to be patterned.
[0089] Here, the two neighboring second contact plugs 232 connected
to each other are partially removed to be isolated from each
other.
[0090] Also, each one pattern corresponding to a unit cell is
formed in the memory cell region B. The fifth and fourth interlayer
insulating films 238 and 234 are preserved as they are in the logic
circuit region A having the second interconnection wiring 236,
while the fifth and fourth interlayer insulating films 238 and 234
existing on the interface between the memory cell region B and the
logic circuit region A, are removed.
[0091] Subsequently, a conductive material 240 for a charge
preservation electrode having a predetermined thickness is formed
over the entire surface of the resultant structure having the
patterned fifth interlayer insulating film 238, along the step
difference, and then a photosensitive film 242 is coated over the
conductive material 240 for a charge preservation electrode in the
logic circuit region A.
[0092] Then, the processes for forming a charge preservation
electrode (not shown), a capacitor dielectric film (not shown) and
a plate electrode (not shown) are the substantially same as those
in the first embodiment, and an explanation thereof will be omitted
herein.
[0093] As described above, in the manufacturing method according to
another embodiment of the present invention, like in the first
embodiment, a sacrificial film removed in the course of forming a
capacitor is preserved in a logic circuit region to be used as an
interlayer insulating film, thereby completely removing a step
difference between a memory cell region and the logic circuit
region. Therefore, the substantially same effects as those in the
first embodiment can be obtained.
[0094] A method of manufacturing a semiconductor device according
to still another embodiment of the present invention will now be
described in detail with reference to the accompanying drawing.
[0095] FIG. 14 is a cross-sectional view illustrating a method of
manufacturing a semiconductor device according to a still another
embodiment of the present invention.
[0096] The method of manufacturing a semiconductor device according
to a still another embodiment of the present invention has the same
processing steps as those in the first embodiment, unlike in FIG. 7
illustrating the first embodiment, the second interconnection
wiring 135 is not formed in the logic circuit region A, and the
processing steps are the substantially same as those in the first
embodiment, except that after a capacitor is first formed in the
memory cell region B and a sixth interlayer insulating film 348 is
formed on the capacitor, the sixth interlayer insulating film 348,
the fourth interlayer insulating film 334, the third etching
stopper film 330, the third interlayer insulating film 328, the
second etching stopper film 326 and the second intermediate
insulating film 324 are sequentially removed by an etching process,
thereby forming a contact (not shown) in a first interconnection
wiring, and then forming a second interconnection wiring 350
through the contact. Thus, an explanation of the processing steps
other than the step of forming the second interconnection wiring
350 will not be given herein.
[0097] The above-described method of manufacturing a semiconductor
device according to still another embodiment of the present
invention is particularly preferred in the case where the capacitor
is not relatively high, and the same result as that in the first or
second embodiment can be obtained.
[0098] As described above, in the method of manufacturing a
semiconductor device according to the present invention, a
sacrificial film removed after formation of the semiconductor
device having a stacked capacitor, is preserved in the logic
circuit region to be used as an interlayer insulating film, unlike
in the conventional method in which a step difference between a
memory cell region and a logic circuit region adjacent thereto is
large. Thus, a step difference between a memory cell region having
the capacitor and a logic circuit region, is removed, thereby
facilitating formation of multi-layered interconnection wirings
formed after forming the capacitor, and attaining fineness of the
interconnection wirings.
* * * * *