U.S. patent application number 09/760402 was filed with the patent office on 2001-06-14 for cobalt silicide etch process and apparatus.
This patent application is currently assigned to Tegal Corporation. Invention is credited to DeOrnellas, Stephen P., Jerde, Leslie G., Marks, Steven.
Application Number | 20010003676 09/760402 |
Document ID | / |
Family ID | 23806229 |
Filed Date | 2001-06-14 |
United States Patent
Application |
20010003676 |
Kind Code |
A1 |
Marks, Steven ; et
al. |
June 14, 2001 |
Cobalt silicide etch process and apparatus
Abstract
Method and apparatus for etching a silicide stack including
etching the silicide layer at a temperature elevated from that used
to etch the rest of the layers in order to accomplish anisotropic
etch.
Inventors: |
Marks, Steven; (Petaluma,
CA) ; Jerde, Leslie G.; (Novato, CA) ;
DeOrnellas, Stephen P.; (Santa Rosa, CA) |
Correspondence
Address: |
Sheldon R. Meyer
FLIESLER, DUBB, MEYER & LOVEJOY LLP
Suite 400
Four Embarcadero Center
San Francisco
CA
94111-4156
US
|
Assignee: |
Tegal Corporation
|
Family ID: |
23806229 |
Appl. No.: |
09/760402 |
Filed: |
January 12, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09760402 |
Jan 12, 2001 |
|
|
|
09454814 |
Dec 3, 1999 |
|
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Current U.S.
Class: |
438/710 ;
257/E21.312; 438/712 |
Current CPC
Class: |
H01L 21/32137 20130101;
H01J 37/32009 20130101; H01J 2237/2001 20130101 |
Class at
Publication: |
438/710 ;
438/712 |
International
Class: |
H01L 021/302 |
Claims
We claim:
1. A method of processing a silicide layer which is included in a
layer stack positioned on a substrate of a wafer including the
steps, in any order, of: processing a layer of the wafer at a first
temperature; and processing the wafer at a second temperature in
order to process the silicide layer.
2. The method of claim 1 wherein: the process is performed with the
wafer at approximately 80.degree. C.; and the temperature for
processing the silicide layer is changed to about above 150.degree.
C.
3. The method of claim 1 wherein the stack includes a cobalt
silicide layer and a polysilicon layer, wherein the steps include:
processing the cobalt silicide layer at one temperature; and
processing the polysilicon layer at another temperature.
4. The method of claim 4 wherein: the cobalt silicide layer is
processed at about above 150.degree. C.; and the polysilicon layer
is processed at about 80.degree. C.
5. The method of claim 1 wherein: the temperature change occurs
rapidly.
6. The method of claim 1 wherein: said temperature changes rapidly
so as not to add substantially to the overall process time.
7. The method of claim 1 wherein: said silicide layer step includes
processing a metal silicide layer.
8. The method of claim 1 wherein: said silicide layer step includes
processing a cobalt silicide layer.
9. The method of claim 2 wherein: said silicide layer processing
step is performed using a cobalt silicide layer.
10. The method of claim 1 wherein: said process is carried out in a
capacitively coupled reactor.
11. The method of claim 1 wherein: said process is carried out in
an inductively coupled reactor.
12. The method of claim 1 wherein said stack has an oxide layer and
wherein: said process is carried out in a reactor which has high
selectivity to the oxide layer.
13. The method of claim 1 wherein said stack has an oxide layer and
wherein: said process is carried out in a capacitively coupled
reactor which has a high selectivity to the oxide layer.
14. The method of claim 1 wherein said stack has an oxide layer and
wherein: said process is carried out in an inductively coupled
reactor which has a high selectivity to the oxide layer.
15. The method of claim 1 wherein: said process is carried out in a
reactor having a chuck; and including the step of changing a heat
transfer rate between the chuck and the wafer in order to change
the temperature of the wafer.
16. The method of claim 1 wherein: said process is carried out in a
reactor having a chuck which is associated with a source of heat;
and including the step of controlling a heat transfer rate between
the chuck and the source of heat.
17. The method of claim 1 wherein: said process is carried out in a
reactor having a chuck and wherein the wafer is mounted on said
chuck so that there is a space defined between at least a portion
of said chuck and a portion of the wafer; and including the step of
controlling the pressure of a gas in said space in order to control
a heat transfer rate between the chuck and the wafer.
18. The method of claim 17 wherein: said controlling step includes
selectively maintaining a vacuum in said space.
19. The method of claim 17 wherein: said controlling step is
carried out by controlling the pressure of helium maintained in
said space.
20. The method of claim 16 wherein: said process is carried out in
a reactor having said chuck spaced from said source of heat; and
the controlling step includes controlling the pressure of a gas in
said space in order to control a heat transfer rate between the
chuck and the source of heat.
21. The method of claim 20 wherein: said controlling step includes
selectively maintaining a vacuum in said space.
22. The method of claim 20 wherein: said controlling step is
carried out by controlling the pressure of helium maintained in
said space.
23. The method of claim 17 wherein: said process is carried out in
a reactor having said chuck spaced from said source of heat; and
the controlling step includes controlling the pressure of a gas in
said space in order to control a heat transfer rate between the
chuck and the source of heat.
24. The method of claim 19 including the step of: controlling the
pressure of helium from between about zero torr and about twenty
torr.
25. The method of claim 19 including the step of: controlling the
pressure of helium at about one torr or less in order to maintain a
wafer at a higher temperature, and controlling the pressure of
helium at five torr or greater in order to maintain a wafer at a
lower temperature.
26. The method of claim 22 including the step of: controlling the
pressure of helium from between about zero torr and about twenty
torr.
27. The method of claim 22 including the step of: controlling the
pressure of helium at about one torr or less in order to maintain a
wafer at higher temperature, and controlling the pressure of helium
at five torr or greater in order to maintain a wafer at a lower
temperature.
28. A method of processing a silicide layer which is included in a
layer stack with another layer including the steps, in any order,
of: processing the silicide layer at an elevated temperature;
processing the another layer at a lower temperature.
29. The method of claim 28 wherein: the temperature for processing
the silicide layer is about above 150.degree. C.; and the
temperature for processing the another layer is at approximately
80.degree. C.
30. The method of claim 28 wherein: said method include processing
the silicide layer and the silicon layer anistropically.
31. An apparatus for processing a silicide layer which is included
in a layer stack positioned on a substrate of a wafer comprising: a
reactor chamber capable of generating a plasma; a chuck adapted for
holding a wafer; means included in the chuck for effecting the
temperature of the wafer.
32. The apparatus of claim 31 wherein: said means is for effecting
the temperature of the wafer without adding any additional heat to
the chuck.
33. The apparatus of claim 31 wherein: said chuck includes a wafer
back side space which can accept a gas in order to control the
transfer of heat between the wafer and the chuck.
34. The apparatus of claim 33 wherein: said chuck includes a heater
that can heat the wafer.
35. The apparatus of claim 34 wherein: said chuck includes a second
wafer back side space which can accept a gas in order to control
the transfer of heat between the chuck and the wafer.
36. The apparatus of claim 33 wherein: said chuck includes a second
wafer back side space which can accept a gas in order to control
the transfer of heat between the chuck and the wafer.
37. An apparatus for processing a silicide layer which is included
in a layer stack positioned on a substrate of a wafer comprising: a
reactor chamber capable of generating a plasma; a chuck adapted for
holding a wafer; and a heat transfer controller located in the
chuck that effects the transfer of heat between the chuck and the
wafer.
38. The apparatus of claim 27 wherein: said heat transfer
controller can effect the temperature of a wafer in the range of up
to least 200 degrees centigrade in a time range of up to 60
seconds.
39. A chuck for a reactor comprising: a mechanism that is adapted
to accept a wafer; and a heat transfer controller located in the
chuck that effects the transfer of heat between the chuck and the
wafer.
40. The chuck of claim 39 wherein: said heat transfer controller
includes a wafer back side space which can accept a gas in order to
control the transfer of heat between the wafer and the chuck.
41. The method of claim 3 wherein the stack has a hard mask layer
and the method further including: processing the hard layer at
about said another temperature.
42. The method of claim 3 wherein the stack has a hard mask layer
comprised of silicon dioxide and the method further including:
processing the hard layer at about said another temperature.
43. The method of claim 1 wherein: said processing steps are
carried out anistropically.
44. The method of claim 1 wherein: said processing steps are
carried out with low etch rates and low microloading.
45. The method of claim 1 wherein: said processing step with said
first temperature is carried out in the same chamber as the
processing step with said second temperature.
46. The method of claim 1 wherein: said processing step with said
first temperature is carried out in a different chamber than the
processing step with said second temperature.
47. The method of claim 1 wherein: at least one of the processing
steps can be carried out in an inductively coupled reactor.
48. The method of claim 1 wherein: at least one of the processing
steps can be carried out in a capacitively coupled reactor.
49. The method of claim 1 wherein: at least one of the processing
steps can be carried out in one of an electron cyclotron resonance
(ECR) reactor and a wave excited discharge reactor.
50. The chuck of claim 40 including: said heat transfer controller
include a second space which can accept a gas in order to control
the transfer of heat between the wafer and the chuck.
51. The chuck of claim 39 including: a heater located adjacent to
the wafer backside spacer.
52. The chuck of claim 51 wherein: said backside spacer separates
said heater from the wafer.
53. The chuck of claim 50 including: a heater located between the
backside space and the second space.
54. The method of claim 1 wherein: the method includes processing a
silicide layer consisting of a layer selected from the group
consisting of a cobalt silicide layer, a tantalum silicide layer, a
titanium silicide layer, and a molybdenum silicide layer.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to silicide etch processes and
apparatus generally and, in particular, to cobalt silicide etch
processes and apparatus.
BACKGROUND OF THE INVENTION
[0002] Since the sheet resistance of metal silicides is much lower
than polysilicon, metal silicides are commonly used as a cladding
on polysilicon to reduce power consumption and the RC time constant
in microelectronic integrated circuits. Of all known silicides,
cobalt silicide has the lowest sheet resistance and is thus the
most desirable silicide for microelectronic integrated circuit use.
The introduction of silicides, and particularly of cobalt silicide,
for microelectronic integrated circuit fabrication has, however,
been limited by the severe difficulty of etching these materials.
The reason for the etch difficulty of cobalt silicide is that
cobalt has no known compounds that can serve as volatile etch
reaction products at temperatures below 500.degree. C. (Handbook of
Chemistry and Physics).
SUMMARY OF THE INVENTION
[0003] Accordingly, the present invention has been developed to
solve the problem of the etching of silicides and, in particular,
cobalt silicide. The invention includes both a method and apparatus
for accomplishing this task.
[0004] The method of processing a silicide layer which is included
in a layer stack positioned on a substrate includes the steps, in
any order, of performing a process which can hold the substrate at
a first temperature and changing the temperature of the substrate
in order to process the silicide layer at a second temperature.
[0005] A method and apparatus of the invention provides for
processing a silicide layer which is included in the layer stack
with another layer including the steps, in any order, of processing
the silicide layer at an elevated temperature and processing
another layer at a lower temperature.
[0006] More specifically, the process includes etching a layer
stack including the silicide and at least one of an oxide and a
polysilicon. The process includes performing the etching of the
silicide at an elevated temperature and performing the etching of
the other layers at lower temperatures. Such a process can occur in
a single etch reactor or in two etch reactors, with the silicide
etch step occurring in a different reaction than the polysilicon
etch step. By such a mechanism, anisotropic etching of both the
silicide and the other layers can be accomplished. Additionally
such a method utilizes the rapid cooling and/or heating of the
wafer in order to bring the wafer temperature to the appropriate
range for etching of the relevant layer.
[0007] In another preferred aspect of the invention, the silicide
layer is etched at a temperature of 150.degree. C. or above while
the remaining layers of the layer stack are etched at approximately
80.degree. C. or below.
[0008] In an aspect of the invention, the silicide layer can
preferably include cobalt silicide. Other silicide layers can
include tantalum silicide, titanium silicide, or molybdenum
silicide. Further, the other layers can include, by way of example,
an oxide layer and/or polysilicon layers.
[0009] The novel method is carried out in a novel apparatus which
is designed for handling hard to process silicide films as well as
for effectively handling the remaining film. Such an apparatus,
preferably, has a high selectivity to oxide films. In particular,
the unique apparatus includes a reactor having a tri-electrode
configuration. En one embodiment, the method is carried out in such
a tri-electrode reactor having first and second electrodes and a
side peripheral electrode. The second electrode is provided with
high and low frequency power supplies. The side peripheral
electrode can alternatively be provided with a high frequency power
supply. This reactor includes a chuck which can rapidly change and
maintain the temperature of the wafer at advantageous levels in
order to process silicide layers and, alternatively, to process
other layers, including by way of example, oxide layers and
polysilicon layers.
[0010] Alternatively, the silicide films can be processed in a
tri-electrode reactor chamber wherein the chuck electrode is
provided with low and high frequency power supplies. The side
peripheral electrode can be grounded or floating. Alternatively,
the side peripheral electrode can be supplied with a low frequency
power supply. With such an arrangement it is again preferable that
the chuck is configurated in order to be able to rapidly change the
temperature of the wafer. Preferably for such an arrangement, other
layers such as oxide and polysilicon layers can be processed in a
separate reactor which is first described herein above with the
high frequency power supply communicating with the side peripheral
electrode.
[0011] It is to be understood that the above described reactors are
generally considered capacitively coupled reactors and that other
reactors including inductively coupled reactors can be used and be
in accordance with the invention. Thus, still alternatively, the
invention can be practical in an inductively coupled di-electrode
or tri-electrode reactor. In one embodiment, the top inductive coil
electrode would be at a high frequency and the bottom electrode
associated with the chuck would be at a low frequency. Both steps
of etching a silicide layer and a non-silicide layer could be
performed in the same chamber. Such a inductively coupled reaction
had multiple etch chambers, if desired, a silicide etch step could
be performed in one chamber and a non-silicide etch step could be
performed in another chamber.
[0012] Accordingly, an object of the invention includes using a
unique combination of one or more of a preferred reactor
configuration, wafer temperature and processing conditions to
successfully meet the microelectronic integrated circuit
fabrication requirements for suicides generally and cobalt silicide
in particular.
[0013] The volatility problem with potential etch reaction products
for cobalt makes the etchability of cobalt silicide similar in
difficulty to platinum or iridium since these elements also have no
known volatile reaction products at conventional etch process wafer
temperatures. This invention teaches the use of the above reactor
configurations, or other comparable reactors, the use of elevated
wafer temperatures, the use of suitable hard mask materials, the
process settings for gas chemistry, pressure, and RF power, and
high speed changes in wafer temperature to etch each of the
materials of a cobalt polycide stack. In particular the invention
addresses the following in a variety of combinations:
[0014] 1. The wafer temperature range, gas chemistry, pressure, and
RF power, required to achieve high etch rate, and anisotropic
etching of cobalt silicide with minimal etch rate and profile
microloading.
[0015] 2. The wafer temperature range to simultaneously meet all
the etch requirements of both the cobalt silicide and polysilicon
layers in the cobalt polycide stack.
[0016] 3. The use of rapid wafer temperature changes, through a
suitably designed wafer chuck to etch each layer in the cobalt
polycide stack to meet all etch requirements.
[0017] 4. The use of suitable hard mask materials to facilitate
elevated wafer temperature etching and meet the mask requirements
for etching cobalt polycide stack structures.
BRIEF DESCRIPTION OF THE FIGURES
[0018] FIG. 1 depicts a side elevational view of the polysilicon
stack partially etched in accordance with the invention.
[0019] FIG. 2 depicts the first embodiment of a reactor for
carrying out the method of the invention.
[0020] FIG. 3 depicts a second embodiment of a reactor for carrying
out the method of the invention.
[0021] FIG. 4 depicts a first embodiment of a chuck mechanism for
carrying out the method of the invention.
[0022] FIG. 5 depicts a second embodiment of a chuck mechanism for
carrying out the method of the invention.
[0023] FIG. 6 depicts another embodiment of a reactor for carrying
out the method of the invention.
[0024] FIG. 7 depicts yet a further embodiment of a reactor for
carrying out the method of the invention.
[0025] FIG. 8 depicts a graph of wafer temperature with respect to
helium pressure in a wafer backside delivery space for a chuck.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0026] The present method is beneficial for etching a layer stack,
including silicides and in particular a cobalt silicide. A cobalt
polysilicide stack is depicted in FIG. 1. The embodiment depicted
in FIG. 1 has been partially anisotropically etched using the
method of the invention. In FIG. 1, layers depicted include a
photoresist mask layer 120, of the hard mask layer 122 such as a
layer comprised of SiO.sub.2, a cobalt silicide layer (CoSi.sub.2)
124, a doped polysilicon layer 126, a gate oxide layer
(particularly SiO.sub.2) 128, and the silicon substrate 130. Other
stacks of different materials with different silicides are within
the spirit and scope of the invention. The relative thicknesses of
the various layers in a typical polyside stack in A units is given
by the below Table 1.
1 TABLE 1 Photoresist Mask 2000-5000 .ANG. Oxide hard Mask
1500-2000 .ANG. CoSi.sub.2 700-750 .ANG. Polysilicon 700-750 .ANG.
Gate Oxide 50-60 .ANG. Silicon Substrate Various
[0027] As the gate oxide layer is relatively thin, there is a
requirement that the inventive process and reactor have a high
selectivity to such oxide layer. There also needs to be a high
selectivity to the hard mask so that there is little or no pattern
degradation in the transfer of the pattern due to the erosion of
the mask. It is beneficial that this be accomplished and that the
stack be etched anisotropically. Such results can occur with the
stack when, by way of example, the suicide layer is etched with the
wafer temperature above about 150.degree. C. and preferably in the
range of 170.degree. C.-250.degree. C. However, the polysilicon
layer and the oxide layers are preferably etched at a temperature
of around 80.degree. C. or below in order that they are
anisotropically etched. With the capacitively coupled reactors
described herein, the polysilicon etch can be in the range of about
80.degree. C. to about 5.degree. C. and be anisotropic. With the
inductively coupled reactors described herein, the polysilicon etch
can be in the range of about 80.degree. C. to about negative
20.degree. C. and be anisotropic. Above around 80.degree. C. the
polysilicon layer will be etched isotropically, which for many
applications would be undesirable. Accordingly, the present
invention is able to accurately and rapidly control the temperature
of the substrate so that in one reactor chamber, as shown for
example in FIG. 2, layers of a single wafer can be etched at a
first temperature and the wafer temperature can be changed rapidly
so that etching can occur at a second temperature, with both etch
processes being anisotropic.
[0028] With respect to the reactor of FIG. 2, anisotropic etching
for the cobalt silicide layer can be successfully carried out using
the parameters specified below in Table 2. In this table, the etch
gas is chlorine and the temperature of the wafer during etching for
the cobalt silicide layer is specified. The pressure specified is
that of the main reactor chamber and the power applied to the high
frequency and low frequency power supplies is specified. The high
frequency power supply is operated at 13.56 MHz while the low
frequency power supply is operated at about 450 KHz. In this
process, the cobalt silicide is etched isotropically with etch
times on the order of 20 sec. to 30 sec.
2TABLE 2 Flow Cl.sub.2 Wafer Pressure HF: (MHz) LF: (KHz) Process
SCCM Temp.degree. C. (mT) Watts Watts 1 90 220 6.5 800 200 2 50 220
3.5 800 270 3 70 220 5 800 140 4 70 200 10 800 140
[0029] A more preferred process than that specified in Table 2
would be with the temperature of the wafer held at approximately
20.degree. C.-30.degree. C. lower than the temperature specified in
Table 2 for purposes of etching the cobalt silicide layer. For this
process, the chuck used was that depicted in FIG. 4, which chuck
will be described more fully herein below. This chuck is able to
control the temperature of the wafer by controlling the pressure of
helium held on the back side of the wafer. Preferably, the helium
is held at a pressure of about less than 1 torr in order to achieve
the higher temperatures in the wafer, with the range being
150.degree. C. and above. With helium pressurized at about 5-10
torr on the back side of the wafer, the wafer settles to a lower
temperature of about 80.degree. C. or below for etching of the
oxide and polysilicon layers. It is to be understood that
alternatively the flow rate of chlorine can be in the range of
about 5 SCCM to about 200 SCCM.
[0030] On high density devices a phenomenon called microloading
introduces etch rate variations. Microloading is a change in the
local etch rate relative to the area of the material being etched.
In one example of microloading, a large sparse area (leaving few
features after etching), will load the etching process with removed
material, slowing the etching rate down in that area, while a
smaller less sparse etch area proceeds at a faster rate. However,
in other situations, microloading can occur in dense areas. This
arrangement is highly desirable for anisotropic etch with profiles
of greater than 86.degree. and also for eliminating the above
indicated microloading.
[0031] For etching a cobalt silicide layer using the reactor of
FIG. 6, the following parameters of Table 3 are used.
3 TABLE 3 Main Chamber Pressure 3.5-6.5 mT HF (MHz) 500-800 Watts
LF (KHz) 50-270 Watts Cl.sub.2 Total Flow 5-200 SCCM Wafer Backside
Pressure 0T-10T Sidewall Temperature 80.degree. C. Top Electrode
Temperature 80.degree. C. Etch Time 20-30 sec
[0032] This table indicates that the pressure in the chamber is
approximately 5 millitorr and that the pressure of the helium on
the back side of the wafer is about 5 torr in order to ensure that
the wafer is maintained at an elevated temperature in order to have
anisotropic etching of the cobalt silicide. Etch results from this
process are shown below in Table 4.
4TABLE 4 Wafer Temperature Etch Rate Profile of CoSi.sub.2 90 C.
2800 .ANG./min 80 degrees 130 C. 3600 .ANG./min 83 degrees 170 C.
4800 .ANG./min 84 degrees 210 C. 5600 .ANG./min 85 degrees
[0033] With respect to Table 4, it is evident that the etch rate
and the profile was a function of temperature. The temperature is
adjusted by adjusting the backside pressure. Typically the best
results are achieved between 170.degree. C. and 220.degree. C. At
about 250.degree. C. the side wall are almost vertical at about
89.degree..
[0034] It is also to be understood that while the above chart shows
that the flow rate of chlorine is approximately 50-90 SCCM, that
additionally mixtures of chlorine and argon could be used. In such
a process the chlorine gas flow rate would be on the order of about
50 SCCM (but with a range of about 5 SCCM to about 200 SCCM) and
the argon gas flow rate would be on the order of about 20 SCCM.
Tri-Electrode Reactors of FIGS. 2 and 3
[0035] Referring to the figures and in particular to FIG. 2, a side
cross-sectional view of an embodiment of the plasma etch reactor
220 of the invention is depicted. This reactor 220 enhances and
improves upon the reactor depicted and described in U.S. Pat. No.
4,464,223, which patent is incorporated herein by reference.
[0036] Reactor 220 includes a reactor chamber 222 which is bounded
by a grounded upper electrode 224, a side peripheral electrode 226,
and a bottom electrode 228. In a preferred embodiment, the side
peripheral electrode 226 is connected to a power supply 230 which
provides power to the side peripheral electrode 226 preferably at
13.56 MHz at a power level of preferably up to about 1100 watts. It
is to be understood that this is a high frequency power supply
(preferably in the radio frequency range) and that the frequency
preferably can range from about 2 MHz to about 950 MHz. The power
can also preferably be supplied in the range of 200 watts to 3,000
watts with a voltage of between 100 volts to 5,000 volts.
[0037] A second power supply 232 is connected to the bottom
electrode 228. The second power supply 232 is preferably operated
at 450 KHz with the power being preferably supplied at 30 watts,
and at a voltage of 200 volts. This is the low frequency power
supply. It is to be understood that this power supply (preferably
in the radio frequency range) can be operated in the range of about
10 KHz to about 1 MHz with a power range of 2 watts to 1,000 watts,
and a voltage range of 5 volts to 3,000 volts. It is to be
understood that with current technology, the lower limit of the
high frequency power supply can overlap with the upper limit of the
high frequency power supply as long as the high frequency and the
low frequency values actually chosen are spaced apart by 1 or 2
MHz. As filtering networks improve such spacing may be eliminated.
Also connected to the bottom electrode 228 is a DC power supply
234. The high-frequency power applied to the side electrode 226
controls ion flux, while low-frequency power applied to the bottom
electrode 228 independently controls ion energy.
[0038] It is the control of the power supplies and principally the
high frequency power supply which advantageously controls the
density of etch plasma in order to provide superior etch
characteristics. Further, it is the design of reactor 220 which
provides the enhanced plasma density range from which the optimal
plasma density can be selected by the control of the power
supply.
[0039] Associated with the grounded upper electrode 224 is a
central nozzle 236 which directs a jet of process gas into the
reactor chamber 222 directed at the semiconductor wafer 248. The
jets of process gas from the nozzle 236 are able to effectively
reach the surface of the semiconductor wafer 248 and provide a
fresh, uniform distribution of process gas over the entire surface
of the semiconductor wafer 248. Such nozzle design is one of many
embodiments that could work with the present invention.
[0040] Immediately above the grounded upper electrode 224 and the
nozzle 236 is an exhaust stack 238, which is used to exhaust spent
gas species from the reactor chamber 222. It is to be understood
that a pump (not shown) is secured to the exhaust stack 238 in
order to evacuate the gas species from the reactor chamber 222.
[0041] As can be seen in FIG. 2, immediately below the upper
electrode 224 and nozzle 236 is a protruding, peripheral baffle
240. Baffle 240 is comprised of insulating material, and protrudes
into the exhaust path 242 between the nozzle 236 and the housing
244 of the plasma etch reactor 220. Protruding baffle 240 ensures
that there is a good mixture of the various gas species from the
nozzle 236 and the solid source 250 in the reactor chamber 222.
[0042] Immediately below the protruding baffle 240 and in this
embodiment incorporated into the side peripheral electrode 226 is a
magnet or plurality of magnets 246. Also preferably incorporated in
upper electrode 224 is a magnet or plurality of magnets 247. Either
one or both of these magnets 246 and 247 define a magnetic
confinement chamber about and coincident with the reactor chamber
222. This magnetic confinement chamber ensure that the charged ion
species in the reactor chamber do not leak therefrom, and that the
charge ion species are concentrated about the semiconductor wafer
248. This magnetic confinement chamber inhibits the charged ion
species from contacting on the walls of the reactor chamber
222.
[0043] Covering the side peripheral electrode 226 and the magnets
246 is the above referenced side peripheral solid source 250. This
solid source 250 provides for an innovative source of a gaseous
species which can be sputtered through the bombardment of, for
example, radio frequency excited ions which knock or erode atoms of
the gas species from the solid source 250 into the reaction chamber
222. The erosion of gaseous species from the surface of the solid
source can be affected by pulsing one or both of the above AC power
supplies. As a further advantage, as portions of the surfaces of
the solid source erode, no particles can be formed on the eroding
surface by the combination of gaseous species. Thus, contamination
from such particles formed on eroding portions of the solid surface
are eliminated.
[0044] Immediately below the solid source 250 is the electrostatic
wafer chuck 252 which positions the semiconductor wafer 248
relative to the reactor chamber 222. Wafer centering ring 253
centers the wafer 248 on the wafer chuck 252. In this embodiment,
the wafer chuck 252 as well as the bottom electrode 228 can be
moved vertically downward in order to insert and remove the wafer
248. As can be seen in FIGS. 2 and 3, a backside gas delivery space
255 is depicted. As described more fully with a description of the
chuck, a gas such as helium can be selectively delivered to space
255 in order to selectively control the temperature of wafer
248.
[0045] In this embodiment, if desired, the side peripheral
electrode 226 and the magnets 246 can be cooled using a cooling
water manifold 254. It is further to be understood that the solid
source 250 can be heated if desired using a hot water manifold 256.
Other methods of heating the solid source 250, and particularly the
front exposed surface thereof, include resistive and inductive
heating, and radiant heat provided by lamps and other sources of
photons.
[0046] The protruding baffle 240 as well as the configuration of
the magnets and the process gas jets from the nozzle, and the gas
species eroded from the solid source, provide for a high density
plasma adjacent to the surface of the semiconductor wafer. This
configuration greatly increases the range of densities that can be
achieved within the reactor chamber 222. The exact density required
can be selected from the greater range of densities by controlling
the power provided to the peripheral electrode 226 by the power
source 230. The power source can be turned down if there is a
desire to reduce the erosion rate of gas species from the solid
source, and to reduce the density of the plasma. Alternatively, the
power source may be turned up in order to increase the density of
the plasma in the reactor chamber 222.
[0047] By way of example only, if a polysilicon layer is being
etched, the power provided by high frequency power source 230 would
be turned down as a less dense plasma and a higher erosion or
generation rate is required from the solid source 250.
Alternatively, if a silicide is being etched, the power would be
turned up as a denser plasma and a lower erosion or generation rate
would be desired from the solid source. Further, the lower
frequency power source can also be adjusted to affect the results
of the etching process in the above invention.
[0048] The above range of operation is not possible with prior
devices. It is to be understood that one or more of the above
features can be used to enlarge the plasma density range and thus
improve the etch process and fall within the spirit and scope of
the invention.
[0049] An alternative embodiment of the reactor 220 is shown in
FIG. 3. Similar components are numbered with similar numbers as
discussed hereinabove. In FIG. 3, the nozzle 236 has been modified
in order to improve the uniformity of the mixture of the gaseous
species in reactor chamber 222. As can be seen in FIG. 3, the
nozzle 236 includes a manifold 270 which can channel the process
gases in a number of directions. From manifold 270 there are
horizontal ports 272, 274 which direct jets of the process gases
horizontally and parallel to the upper electrode 224. Port 276
directs jets of the gas vertically downward directly onto the wafer
248. Ports 278 and 280 channel jets of the process gases in a
direction skewed to the horizontal, and principally toward the
periphery of the wafer 248 in order to assure a uniform
distribution of process gases and/or a good mixture of the gas
species sputtered or otherwise eroded from the solid source 250 and
the jets of process gases. In this embodiment, it is also the
combination of the ports of the manifold 270 and the protruding
baffle 240 which ensures that a good mixture of (1) the gas species
sputtered or eroded from the solid source 250, and (2) the process
gases from the ports of the nozzle 236, are presented to the
surface of the semiconductor wafer 248.
[0050] In this alternative embodiment, if desired, a second low
frequency power supply 231 can be communicated with the peripheral
electrode 226. This power supply would preferably have a frequency
of 450 KHz. This power supply would be in all aspects similar to
power supply 232. The high frequency power supply 230 would control
the plasma density while the low frequency power supply 231 would
control the erosion rate of gaseous species from the solid source.
This would be an alternative to having the high frequency power
supply control both the density of the plasma and the rate of
erosion in the solid source.
[0051] Etching in prior art devices is usually performed in the 300
to 500 millitorr range, which range is one to two orders of
magnitude higher than the low pressures contemplated by the reactor
of the present invention. For etching of submicron features
required by state-of-the-art semiconductor devices, low pressure
operations are desirable. However, at low pressures, it is more
difficult to maintain a high density plasma.
[0052] For the embodiments of FIGS. 2 and 3, the present embodiment
contemplates a magnetic field which contains the plasma at a low
pressure (3-5 millitorrs), with a high plasma density (10.sup.11
cm.sup.3 at the wafer), and with low ion energy (less than 15 to 30
electron volts). Magnetic containment is not required for an
inductively coupled reactor or for that matter for a capacitively
coupled reactor. For such inductively coupled reactions, magnetic
coupling generally enhances plasma uniformity, but is not needed to
enhance plasma density. Generally, low pressure operation would be
at about 150 millitorr or about 100 millitorr or less and
preferably about 20 millitorr or about 10 millitorr or less. For
submicron (sub 0.5 microns) devices, the plasma source must operate
at a low pressure with a high density of activated gases at the
wafer and a low ion energy in order to deliver superior etching
results. A low pressure plasma improves the overall quality of the
etch by minimizing the undercutting of the wafer features as well
as the effect of microloading, both of which can adversely affect
overall yield. Low pressure, however, requires a high density
plasma at the wafer to increase the number of plasma particles
reacting with a film on the semiconductor wafer being etched in
order to maintain a fast etch rate. A fast etch rate is one factor
leading to a higher average throughput. Further, low ion energy
leads to improved etch selectivity and minimizes wafer damage. Both
of which improve overall yield.
[0053] The reactor 220 of the present invention can be used to etch
a variety of different substrates or films which require different
etch chemistry or recipe. Generally, this chemistry includes two or
more of the following gases: halogen gases, halogen containing
gases, noble gases, and diatomic gases.
Tri-Electrode Reactors of FIGS. 6 and 7
[0054] Referring to the figures and in particular to FIG. 6, a side
cross-sectional view of an embodiment of the plasma etch reactor
620 of the invention is depicted. This reactor 620 enhances and
improves upon the reactor depicted and described in U.S. Pat. No.
4,464,223, entitled PLASMA REACTOR APPARATUS AND METHOD, as U.S.
Pat. No. 4,579,618, entitled PLASMA REACTOR APPARATUS which patents
are incorporated herein by reference.
[0055] Reactor 620 includes a reactor chamber 622 which is bounded
by a grounded upper electrode 624, a side peripheral electrode 626,
and a bottom electrode 628. The side peripheral electrode 626 is
grounded or has a floating potential and in operation can be
charged up by the plasma. In a preferred embodiment, the bottom
electrode 628 is connected to a power supply 630 which provides
power to the bottom electrode 626 preferably at 13.56 MHz (or
multiples thereof) at a power level of preferably 900 watts and at
a voltage of preferably 1,200 volts. The high frequency power
supply can operate from 10 watts up to 2000 watts in a preferred
embodiment. It is to be understood that this is a high frequency
power supply (preferably in the radio frequency range) and that the
frequency preferably can range from 2 MHz to 40 MHz and upwards to
about 900 MHz. The power can also preferably be supplied in the
range of 100 watts to 3,000 watts with a voltage of between 200
volts to 5,000 volts.
[0056] A second power supply 632 is additionally connected to the
bottom electrode 628. The second power supply 632 is preferably
operated at 450 KHz with the power being preferably supplied at 100
watts, and at a voltage of 300 volts. This is the low frequency
power supply. It is to be understood that this power supply
(preferably in the radio frequency range) can be operated in the
range of about 100 KHz to about 950 KHz (preferably 1 MHz or less)
with a power range of 10 watts to 2,000 watts, and a voltage range
of 10 volts to 5,000 volts. Also connected to the bottom electrode
628 is a DC power supply 634. The high-frequency power supply
controls ion flux, while low-frequency power supply independently
controls ion energy.
[0057] It is the control of the power supplies and principally the
high frequency power supply which advantageously controls the
density of etch plasma in order to provide superior etch
characteristics. Further, it is the design of reactor 620 which
provides the enhanced plasma density range from which the optimal
plasma density can be selected by the control of the power
supply.
[0058] Associated with the grounded upward electrode 624 is a
central nozzle 636 which directs a jet of process gas into the
reactor chamber 622 directed at the semiconductor wafer 648. The
jets of process gas from the nozzle 636 are able to effectively
reach the surface of the semiconductor wafer 648 and provide a
fresh, uniform distribution of process gas over the entire surface
of the semiconductor wafer 648.
[0059] Immediately above the grounded upper electrode 624 and the
nozzle 636 is an exhaust stack 638, which is used to exhaust spent
gas species from the reactor chamber 622. It is to be understood
that a pump (not shown) is secured to the exhaust stack 638 in
order to evacuate the gas species from the reactor chamber 622.
[0060] As can be seen in FIG. 6, immediately below the upper
electrode 624 and nozzle 636 is a protruding, peripheral baffle
640. Baffle 640 is comprised of insulating material, and as will be
discussed below, protrudes into the exhaust path 642 between the
nozzle 636 and the housing 644 of the plasma etch reactor 620.
Protruding baffle 640 ensures that there is a good mixture of the
various gas species from the nozzle 636 and the solid source 650 in
the reactor chamber 622.
[0061] Immediately below the protruding baffle 640 and in this
embodiment incorporated into the side peripheral electrode 626 is a
magnet or plurality of magnets 646. Also preferably incorporated in
upper electrode 624 is a magnet or plurality of magnets 647. As
will be discussed below, either one or both of these magnets 646
and 647 define a magnetic confinement chamber about and coincident
with the reactor chamber 622. This magnetic confinement chamber
ensure that the charged ion species in the reactor chamber do not
leak therefrom, and that the charge ion species are concentrated
about the semiconductor wafer 648. This magnetic confinement
chamber inhibits the charged ion species from contacting on the
walls of the reactor chamber 622. Again, as discussed before, such
magnets can enhance, but are not required for, the operation of an
inductively coupled reactor or for that matter, a capacitively
coupled reactor.
[0062] Covering the side peripheral electrode 626 and the magnets
646 is a side peripheral solid source 650. Such a solid source is
not required in the preferred embodiment as there is no power
provided to the ring electrode 626. If, however, in addition to the
above power source, a high frequency power source were provided to
the solid source 650, then this solid source 650 would provide for
an innovative source of a gaseous species which can be sputtered
through the bombardment of, for example, radio frequency excited
ions which knock or erode atoms of the gas species from the solid
source 650 into the reaction chamber 622. The erosion of gaseous
species from the surface of the solid source can be affected by the
pulsing of power supplies. As a further advantage, as portions of
the surfaces of the solid source erode, no particles can be formed
on the eroding surfaces by the combination of gaseous species.
Thus, contamination from such particles formed on eroding portions
of the solid surfaces are eliminated.
[0063] Immediately below the solid source 650 is the electrostatic
wafer chuck 652 which positions the semiconductor wafer 648
relative to the reactor chamber 622. Wafer centering ring 653
centers the wafer 648 on the wafer chuck 652. In this embodiment,
the wafer chuck 652 as well as the bottom electrode 628 can be
moved vertically downward in order to insert and remove the wafer
648. As can be seen in FIGS. 6 and 7, a backside gas delivery space
655 is depicted. As described more fully with a description of the
chuck a gas such as helium can be selectively delivered to space
655 in order to selectively control the temperature of wafer
648.
[0064] In this embodiment, if desired, the side peripheral
electrode 626 and the magnets 646 can be cooled using a cooling
water manifold 654. It is further to be understood that the solid
source 650 can be heated if desired using a hot water manifold 656.
Other methods of heating the solid source 650, and particularly the
front exposed surface thereof, include resistive and inductive
heating, and radiant heat provided by lamps and other sources of
photons.
[0065] The protruding baffle 640 as well as the configuration of
the magnets and the process gas jets from the nozzle, and the gas
species eroded from the solid source (if a power supply is
connected to the peripheral ring electrode 626), provide for a high
density plasma adjacent to the surface of the semiconductor wafer.
This configuration greatly increases the range of densities that
can be achieved within the reactor chamber 622.
[0066] The above range of operation is not possible with prior
devices. It is to be understood that one or more of the above
features can be used to enlarge the plasma density range and thus
improve the etch process and fall within the spirit and scope of
the invention.
[0067] An alternative embodiment of the reactor 620 is shown in
FIG. 7. Similar components are numbered with similar numbers as
discussed hereinabove. In FIG. 7, the nozzle 636 has been modified
in order to improve the uniformity of the mixture of the gaseous
species in reactor chamber 622. As can be seen in FIG. 7, the
nozzle 636 includes a manifold 670 which can channel the process
gases in a number of directions. From manifold 670 there are
horizontal ports 672; 674 which direct jets of the process gases
horizontally and parallel to the upper electrode 624. Port 676
directs jets of the gas vertically downward directly onto the wafer
648. Ports 678 and 680 channel jets of the process gases in a
direction skewed to the horizontal, and principally toward the
periphery of the wafer 648 in order to assure a uniform
distribution of process gases and/or a good mixture of the gas
species. In this embodiment, it is also the combination of the
ports of the manifold 670 and the protruding baffle 640 which
ensures that a good mixture of (1) the gas species sputtered or
eroded from the solid source 650 (if a source of power is connected
to peripheral ring electrode 626), and (2) the process gases from
the ports of the nozzle 636, are presented to the surface of the
semiconductor wafer 648.
[0068] Etching in prior art devices is usually performed in the 300
to 500 millitorr range, which range is one to two orders of
magnitude higher than the low pressures contemplated by the reactor
of the present invention. For etching of submicron features
required by state-of-the-art semiconductor devices, low pressure
operations are desirable. However, at low pressures, it is more
difficult to maintain a high density plasma.
[0069] For the embodiments of FIGS. 6 and 7, the present invention
contemplates a magnetic field which contains the plasma at a low
pressure (3-5 millitorrs), with a high plasma density (10.sup.11
cm.sup.3 at the wafer), and with low ion energy (less than 15 to
300 electron volts). Generally, low pressure operation would be at
about 150 millitorr or about 100 millitorr or less and preferably
about 20 millitorr or about 10 millitorr or less. For submicron
(sub 0.5 microns) devices, the plasma source must operate at a low
pressure with a high density of activated gases at the wafer and a
low ion energy in order to deliver superior etching results. A low
pressure plasma improves the overall quality of the etch by
minimizing the undercutting of the wafer features as well as the
effect of microloading (etching concentrated features more rapidly
than less concentrated features), both of which can adversely
affect overall yield. Low pressure, however, requires a high
density plasma at the wafer to increase the number of plasma
particles reacting with a film on the semiconductor wafer being
etched in order to maintain a fast etch rate. A fast etch rate is
one factor leading to a higher average throughput. Further, low ion
energy leads to improved etch selectivity and minimizes wafer
damage. Both of which improve overall yield. It is contemplated
that the present embodiment can operate at about 150 millitorr or
less.
[0070] The reactor 620 of the present invention can be used to etch
a variety of different substrates or films which require different
etch chemistry or recipe. Principally, the embodiments of the
invention are used to etch the new emerging films. Generally, this
chemistry includes two or more of the following gases: halogen
gases, halogen containing gases, noble gases, and diatomic
gases.
[0071] It is to be understood that while the majority of the
embodiments for carrying out the process utilized capacitively
coupled electrodes, that inductively coupled electrodes, can be
utilized and be within the spirit and scope of the invention. Such
an inductively coupled reactor can be reviewed in U.S. Pat.
5,277,751, issued on Jan. 11, 1994, entitled METHOD AND APPARATUS
FOR PRODUCING LOW PRESSURE PLANAR PLASMA USING A COIL WITH ITS AXIS
PARALLEL TO THE SURFACE OF A COUPLING WINDOW, which patent is
incorporated herein by reference.
Reactor Chuck Configuration
[0072] The method of the present invention can be performed in an
etch reactor such as the etch reactor depicted in FIGS. 2, 3, 6,
and 7, using the chuck configuration such as the chuck
configuration shown in FIGS. 4 or 5. It is to be understood that
other reactors, including but not limited to other etch reactors
and other chuck configurations can be used and be within the scope
and spirit of the invention. Presently, chuck 446 (FIG. 4) shall be
described with respect to the reactor 220 of FIG. 2.
[0073] Turning to FIG. 4, the chuck, which is incorporated in the
bottom electrode 228, is shown in greater detail. As can be seen in
FIG. 4, the chuck configuration 446, which is preferably an
electrostatic chuck, includes a wafer centering ring 448, which
holds a wafer 426 against the lower electrode 428. The gas which
controls heat transfer from the wafer is delivered in the gas
delivery space 454 located between the wafer 426 and the lower
electrode 428. Thus the gas delivery space 454 acts as a heat
transfer controller in order to control the transfer of heat
between the chuck and the wafer. In a preferred embodiment, the
wafer centering ring 448 is made of a high purity alumina ceramic
and the configuration is set up such that when the gas contained in
gas delivery space 454 is helium, that the gas leak rate into the
reactor chamber 424 is on the order of less than 2 SCCM, in
comparison to a typical process flow rate being for example, 80
SCCM. The temperature can be measured in a preferred embodiment as
shown (FIG. 4) by using a fluoroptic probe 460 which uses infrared
to sense temperature.
[0074] As will be explained below, alternative to or in addition to
the modification of heat transfer from the wafer due to the control
of the gas pressure (wafer centering ring pressure) in the gas
delivery space 454, the chuck 446 can itself be heated in order to
heat the wafer. Such heating can be the result of, for example, a
resistive heater or cartridge heater 456 contained in the lower
electrode 428. Still alternatively, an RF power supply connected to
chuck 446 can also be used to heat said chuck. This method can be
used with or without the helium chamber 454. With the helium
chamber, the pressure in the chamber would be high on the order of
5 to 10 torr in order to conduct the heat from the chuck to the
back side of the wafer.
[0075] It is to be understood that, of the two embodiments, the
first embodiment using the helium filled chamber as opposed to the
resistive heater is capable of more rapidly affecting the
temperature of the wafer and thus is preferable for use in a
chamber which accomplishes both etching of the cobalt silicide at
an elevated temperature and the oxide and polysilicon layers at a
lower temperature. Other wafer heating apparatus can be used.
[0076] Thus, in accordance with the invention, the wafer can be
heated (i) by reducing the amount of heat transferred from the
wafer by decreasing the pressure of the backside gas or (ii) by
increasing the pressure of the gas in order to heat the wafer using
a heat source. These two configurations can be practiced separately
and be within the scope of the invention. Of course raising the
helium backside pressure without a heat source will cause a
lowering of the wafer temperature by transferring heat from the
wafer to the chuck, and the electrode pedestal if the chuck and/or
pedestal are cooler than the wafer.
[0077] The gas delivered to the gas delivery space 454 is helium,
as helium has a good heat capacity, is light and mobile, and is
efficient in transferring energy. Helium pressure from about zero
torr to about 20 torr can be effectively used to control the
temperature of the wafer. Other gases such as nitrogen and argon
could be used, and in addition any gas that has these
characteristics and which will not condense could be used. It will
be understood that at least some of these gas will leak into the
main reaction chamber 424.
[0078] In FIG. 8, four curves are plotted. The curves are for
helium pressures of approximately 0 torr, 1 torr, 3 torr, and 5
torr, in the gas delivery space 454. At 5 to 10 torr, the
temperature of the wafer would be about in the range of 80.degree.
C. or lower. As can be seen generally in FIG. 8, at about 3 torr
and greater, the wafer surface temperature goes from about
80.degree. C. to about 140.degree. C. within the first 60 seconds.
At a helium pressure of about 1 torr in the gas delivery space 454,
the wafer surface temperature goes from about a starting
temperature of about 80.degree. C. to over 200.degree. C. in the
first 60 seconds and finally levels off at around 240.degree. C.
Also as shown in FIG. 8 at close to 0 torr, the temperature of the
wafer hits approximately 300.degree. C. in the first 60 seconds and
it continues to climb due to the lack of heat transfer from the
wafer at such a low pressure for the gas in the gas delivery space
454.
[0079] An alternative embodiment of the chuck can be seen in FIG.
5. In this embodiment a second gas delivery space 462 is located
below the electrostatic chuck. This space can also be filled with
helium at pressures of below 1 torr and up to and above 20 torr in
order to effect the temperature of the wafer as described with
respect to the first space 454. It is to be understood that the
first gas delivery space 454 would offer the first order of control
and that the second order of control would be by the second gas
delivery space 462. With heater 456 removed or not in use, or with
the chuck not heated by an alternative source, the gas pressure in
space 462 would be increased to cool the wafer or decreased to
allow the reactor chamber to heat the wafer. If the chuck were
heated below the second gas delivery space 462, the opposite would
be true. That is higher pressure in space 462 would conduct heat to
the wafer and lower pressure would lessen the conduction from the
heat source. Accordingly, with space 454 at a higher pressure and
space 462 at a lower pressure, the heater 456 could heat the wafer,
and space 462 could isolate the heater and wafer from a cooler
pedestal located below space 462. If it were desired to rapidly
cool off the wafer, then the heater would be turned off and both
spaces 454 and 462 would be placed at an elevated pressure to
increase heat transfer from the wafer. It is to be understood that
chuck types other than electrostatic chucks can benefit from the
invention.
[0080] It is to be understood that the present invention can be
carried out in other types of reactors, including by way of example
only, electron cyclotron resonance reactors (ECR) and wave excited
discharge reactors such as surface wave reactors and helicon
reactors.
[0081] Industrial Applicability
[0082] The present invention is considered to be highly relevant to
methods and apparatus for the etching of silicide layers, and in
particular metal silicide layers, and further in particular to
cobalt silicide layers. Such etch processes are accomplished in a
rapid manner while maintaining selectively to the oxide layers.
Such processes and apparatus are highly advantageous for use in the
DRAM market and also in high speed logic integrated circuit
manufacturing.
[0083] Other features, aspects and objects of the invention can be
obtained from a review of the figures and the claims.
[0084] It is to be understood that other embodiments of the
invention can be developed and fall within the spirit and scope of
the invention and claims.
* * * * *