U.S. patent application number 09/747966 was filed with the patent office on 2001-06-07 for process to produce ultrathin crystalline silicon nitride on si (111 ) for advanced gate dielectrics.
Invention is credited to Hattangady, Sunil V., Wallace, Robert M., Wei, Yi, Wilk, Glen D..
Application Number | 20010002709 09/747966 |
Document ID | / |
Family ID | 23030214 |
Filed Date | 2001-06-07 |
United States Patent
Application |
20010002709 |
Kind Code |
A1 |
Wallace, Robert M. ; et
al. |
June 7, 2001 |
Process to produce ultrathin crystalline silicon nitride on Si (111
) for advanced gate dielectrics
Abstract
A method of making a semiconductor device and the device. The
device, according to a first embodiment, is fabricated by providing
a silicon (111) surface, forming on the surface a dielectric layer
of crystalline silicon nitride and forming an electrode layer on
the dielectric layer of silicon nitride. The silicon (111) surface
is cleaned and made atomically flat. The dielectric layer if formed
of crystalline silicon nitride by placing the surface in an ammonia
ambient at a pressure of from about 1.times.10.sup.-7 to about
1.times.10.sup.-5 Torr at a temperature of from about 850.degree.
C. to about 1000.degree. C. The electrode layer is heavily doped
silicon. According to a second embodiment, there is provided a
silicon (111) surface on which is formed a first dielectric layer
of crystalline silicon nitride having a thickness of about 2
monolayers. A second dielectric layer compatible with silicon
nitride and having a higher dielectric constant than silicon
nitride is formed on the first dielectric layer and an electrode
layer is formed over the second dielectric layer. A third
dielectric layer of silicon nitride having a thickness of about 2
monolayers can be formed between the second dielectric layer and
the electrode layer. The second dielectric layer is preferably
taken from the class consisting of tantalum pentoxide, titanium
dioxide and a perovskite material. Both silicon nitride layers can
be formed as in the first embodiment. The electrode layer is
preferably heavily doped silicon
Inventors: |
Wallace, Robert M.;
(Richardson, TX) ; Wilk, Glen D.; (Dallas, TX)
; Wei, Yi; (Chandler, AZ) ; Hattangady, Sunil
V.; (McKinney, TX) |
Correspondence
Address: |
BAKER & BOTTS
1299 PENNSYLVANIA AVE., N.W.
WASHINGTON
DC
20004
US
|
Family ID: |
23030214 |
Appl. No.: |
09/747966 |
Filed: |
December 27, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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09747966 |
Dec 27, 2000 |
|
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09270173 |
Mar 16, 1999 |
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Current U.S.
Class: |
257/296 ;
257/E21.193; 257/E21.274; 257/E21.293; 257/E21.396; 257/E21.647;
438/240; 438/3; 438/791 |
Current CPC
Class: |
H01L 29/517 20130101;
H01L 29/66181 20130101; H01L 21/28194 20130101; H01L 21/31604
20130101; H01L 29/518 20130101; H01L 27/1085 20130101; H01L 29/513
20130101; H01L 21/28167 20130101; H01L 21/28202 20130101 |
Class at
Publication: |
257/296 ;
438/791; 438/3; 438/240 |
International
Class: |
H01L 027/108; H01L
021/00; H01L 021/31; H01L 021/469 |
Claims
1. A method of making a semiconductor device which comprises the
steps of: (a) providing a silicon (111) surface; (b) forming on
said surface a dielectric layer of crystalline silicon nitride; and
(c) forming an electrode layer on said dielectric layer of silicon
nitride.
2. The method of claim 1 further including the step of cleaning
said surface and making said surface atomically flat.
3. The method claim 1 wherein said step of forming said dielectric
layer of crystalline silicon nitride comprises the steps of placing
said surface in an ammonia ambient at a pressure of from about
1.times.10.sup.-7 to about 1.times.1.sup.-5 Torr at a temperature
of from about 850.degree. C. to about 1000.degree. C.
4. The method claim 2 wherein said step of forming said dielectric
layer of crystalline silicon nitride comprises the steps of placing
said surface in an ammonia ambient at a pressure of from about
1.times.10.sup.-7 to about 1.times.10.sup.-5 Torr at a temperature
of from about 850.degree. C. to about 1000.degree. C.
5. The method of claim 3 wherein said electrode layer is boron
doped silicon.
6. The method of claim 4 wherein said electrode layer is boron
doped silicon.
7. A semiconductor device which comprises: (a) a silicon (111)
surface; (b) a dielectric layer of crystalline silicon nitride on
said surface; and (c) an electrode layer on said dielectric layer
of silicon nitride.
8. The device of claim 7 wherein said surface is cleaned and
atomically flat.
9. The device of claim 7 wherein said electrode layer is boron
doped silicon.
10. The device of claim 8 wherein said electrode layer is boron
doped silicon.
11. A method of making a semiconductor device which comprises the
steps of: (a) providing a silicon (111) surface; (b) forming on
said surface a first dielectric layer of crystalline silicon
nitride having a thickness of about 2 monolayers; (c) forming on
said first dielectric layer a second dielectric layer compatible
with silicon nitride and having a higher dielectric constant than
silicon nitride; and (d) forming an electrode layer over said
second dielectric layer.
12. The method of claim 11 further including the step of forming
between said second dielectric layer and said electrode layer a
third dielectric layer of silicon nitride having a thickness of
about 2 monolayers.
13. The method of claim 11 wherein said second dielectric layer is
taken from the class consisting of tantalum pentoxide, titanium
dioxide and a perovskite material.
14. The method of claim 12 wherein said second dielectric layer is
taken from the class consisting of tantalum pentoxide, titanium
dioxide and a perovskite material.
15. The method claim 11 wherein said step of forming said first
dielectric layer of crystalline silicon nitride comprises the steps
of placing said surface in an ammonia ambient at a pressure of from
about 1.times.10.sup.-7 to about 1.times.10.sup.-5 Torr at a
temperature of from about 850.degree. C. to about 1000.degree.
C.
16. The method claim 14 wherein said step of forming said
dielectric layer of crystalline silicon nitride comprises the steps
of placing said surface in an ammonia ambient at a pressure of from
about 1.times.10.sup.-7 to about 1.times.10.sup.-5 Torr at a
temperature of from about 850.degree. C. to about 1000.degree.
C.
17. The method of claim 16 wherein said electrode layer is boron
doped silicon.
18. A semiconductor device which comprises: (a) a silicon (111)
surface; (b) a first dielectric layer of crystalline silicon
nitride on said surface having a thickness of about 2 monolayers;
(c) a second dielectric layer on said first dielectric layer
compatible with silicon nitride and having a higher dielectric
constant than silicon nitride; and (d) an electrode layer over said
second dielectric layer.
19. The device of claim 18 further including, between said second
dielectric layer and said electrode layer, a third dielectric layer
of silicon nitride having a thickness of about 2 monolayers.
20. The device of claim 19 wherein said second dielectric layer is
taken from the class consisting of tantalum pentoxide, titanium
dioxide and a perovskite material an electrode layer on said
dielectric layer of silicon nitride.
21. The device of claim 20 wherein said electrode layer is boron
doped silicon.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to a method of producing ultrathin
crystalline silicon nitride on Si (111) and formation of
semiconductor devices using such ultrathin crystalline silicon
nitride.
[0003] 2. Brief Description of the Prior Art
[0004] The continued down-scaling of the geometries in VLSI
technology has involved, as a result of such down-scaling, a
reduction in component film thicknesses, examples being gate
dielectrics for FET semiconductor devices and the capacitor
dielectric for semiconductor memory devices. Thickness uniformity
requirements for such films (about 0.14 nanometers in thickeness in
present technology) requires extraordinary control over the silicon
wafer surface morphology (i.e., subsequent interfacial roughness)
to achieve necessary scaling. The acute sensitivity of interface
roughness with ultrathin films is evident when one considers the
control required over large (200 mm or 300 mm) wafers.
[0005] Conventional silicon semiconductor technology incorporates
Si (100) substrates, largely because of interface trap density
(Dit) considerations associated with oxide films on Si (100) which
has been extensively researched over the past two decades.
Moreover, it has been demonstrated that surface preparation methods
currently developed, such as HF-last treatments, can result in a Si
(100) hydrogen-terminated surface with a roughness which is
unacceptable for prospective dielectric film thickness uniformity
requirements. The use of alternative dielectric materials, such as
silicon nitride, has been considered as a means to increase the
gate dielectric constant and also to serve as a diffusion barrier
to dopants in the gate material. However, the current silicon
nitride fabrication techniques on Si (100) result in an amorphous
nitride or oxynitride layer which may exhibit deleterious interface
states (traps) which degrade ultimate device performance.
[0006] A further problem with silicon dioxide dielectrics over Si
(100) substrates is that boron from boron-doped polysilicon gate
structures can diffuse through the silicon dioxide, this problem
increasing with decreased gate oxide thickness geometries, thereby
degrading the properties of the device, particularly in the channel
region. Boron, on the other hand, does not diffuise through silicon
nitride, however, the interface between silicon nitride and Si
(100) results in an amorphous silicon nitride and provides an
inferior structure to that with silicon dioxide by causing a
disruption of the electron flow in the channel of the active
semiconductor devices.
[0007] A separate problem with silicon dioxide dielectrics is that
the extremely small thicknesses allow unacceptable leakage currents
as a result of electrons tunneling from the gate to the drain
regions of transistors. Since silicon nitride has a larger bulk
dielectric constant than silicon dioxide (.about.7 compared to
about 3.9), a thicker silicon nitride layer can be used which has
the same capacitance density as a thinner silicon dioxide layer.
Since electron tunneling currents depend exponentially on layer
thickness, even an increase in dielectric thickness of about 10 to
about 20 Angstroms could reduce leakage current by several orders
of magnitude.
SUMMARY OF THE INVENTION
[0008] Recent work has demonstrated that the Dit from oxides on Si
(111) can be made comparable to those on Si (100), thus making
devices on such substrates feasible. The silicon (111) surface can
be controlled to be made hydrogen-terminated and atomically flat
from a careful control of the surface preparation solution pH. The
resultant smooth surface can therefore result in a low roughness
(<0.1 nm, rms) interface after subsequent film deposition.
Recent research has also demonstrated the potential formation of an
ordered silicon nitride film on the Si (111 ) surface from the
reaction of NH.sub.3 with an atomically clean Si (111) surface,
i.e., where no surface impurities are detected, at temperatures
between 800.degree. C. and 1130.degree. C. under high vacuum
conditions of from about 10.sup.-7 to about 10.sup.-5 Torr NH.sub.3
partial pressures. The cleaning process could include, for example,
a standard semiconductor wet clean followed by oxidation (chemical
or thermal), then followed by HF-last stripping of the oxide for
H-termination. The hydrogen is then desorbed in the course of the
temperature ramp-up for nitride deposition. Alternatively, the
cleaning can take place by ultra high vacuum (UHV), from about
10.sup.-11 to about 10.sup.-9 Torr, "flash heating" to about
1100.degree. C. and cooling to room temperature to form a
well-ordered surface. Under the proper temperature conditions
(850.degree. C. to 1000.degree. C.), the nitride film covered Si
(111) surface is atomically flat, i.e., where only single height
steps between nitride terraces exist. The resultant crystalline
film is thus useful for an epitaxial nitride layer, or it will be
useful for the purpose of surface passivation and subsequent
crystalline or amorphous dielectric film overgrowth.
[0009] Interface state densities associated with such an epitaxial
layer are low because the dangling bonds are consumed with the
epitaxial growth process. Moreover, the smooth interface afforded
by the Si (111) surface preparation results in an atomically flat
nitride layer as well. Such sharp smooth interfaces result in
enhanced electron mobility properties (less interface scattering)
as well as a superior dopant diffuision barrier. Any residual
dangling bonds can be satiated from a H.sub.2 or D.sub.2 sintering
process.
[0010] In accordance with the present invention, the above
described problems of the prior art are therefore minimized and
there is provided an ultrathin crystalline silicon nitride layer on
Si (111) for use, primarily though not exclusively as a gate
dielectric for semiconductor devices and as a capacitor dielectric
in semiconductor memory devices.
[0011] Briefly, by growing crystalline silicon nitride on Si (111),
the barrier to boron diffusion is retained and, in addition, the
channel is not disrupted as in the case of amorphous silicon
nitride over a Si (100) substrate.
[0012] Another problem of the prior art that is minimized in
accordance with the present invention is based upon the fact that
as that the drive current is proportional to the capacitance
between the gate electrode and the substrate. Therefore, for a
given drive current as the contact area of the dielectric decreases
the dielectric thickness must also decrease. The result is that
electrons from the gate electrode are then capable of tunneling
through the dielectric and add to the channel or drain current,
resulting in lack of device control. Since the dielectric constant
of silicon dioxide is about 3.9 and the dielectric constant of
silicon nitride is about 7, a thicker layer of silicon nitride can
be provided with the same capacitance and drive current properties,
yet prevent electron tunneling through the dielectric.
[0013] To form a semiconductor device in accordance with the
present invention, there is initially provided a surface of Si
(111) which has been cleaned and is atomically flat as defined
hereinabove. The Si(111) surface is placed in a standard reaction
chamber and the chamber purged and filled with ammonia (NH.sub.3)
at an ammonia partial pressure of from about 1.times.10.sup.-7 to
about 1.times.10.sup.-5 Torr at a temperature of from about
850.degree. C. to about 1000.degree. C. for from about 5 seconds to
about 5 minutes to provide a thin layer of crystalline silicon
nitride on the Si (111) of from about 0.3 nm to about 3 nm. The
remainder of the semiconductor device is then fabricated in
standard manner by, for example, depositing a doped layer of
polysilicon or a metal layer over the silicon nitride layer. In the
case of a boron-doped polysilicon electrode, the boron will be
prevented from diffusing through the dielectric due to the use of
silicon nitride as the dielectric.
[0014] While silicon nitride has been discussed above as being the
dielectric material, it should be understood that other materials
can be used that have a higher dielectric constant than and are
compatible with silicon nitride. When there is a lack of silicon
compatibility resulting in SiO.sub.x formation at the interface,
such as, for example, with tantalum pentoxide (Ta.sub.2O.sub.5),
titanium dioxide (TiO.sub.2) or a perovskite material, a very thin
layer of silicon nitride can be used to separate the dielectric
material from the Si (111) substrate and/or the electrode over the
dielectric, such thin layer having a thickness of about 2
monolayers.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 is a cross sectional view of a semiconductor device
fabricated in accordance with a first embodiment in accordance with
the present invention; and
[0016] FIG. 2 is a cross sectional view of a semiconductor device
fabricated in accordance with a second embodiment in accordance
with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0017] Referring first to FIG. 1, there is shown a semiconductor
device fabricated in accordance with a first embodiment of the
present invention. The semiconductor device includes a Si (111)
substrate 1 over which is formed a dielectric layer of crystalline
silicon nitride (Si.sub.3N.sub.4)3. An electrode layer 5 of boron-
or phosphorous- or arsenic-doped polycrystalline silicon is formed
over the dielectric layer to form the completed semiconductor
active transistor structure.
[0018] The semiconductor device of FIG. 1 is fabricated by
providing a substrate 1 having an exposed surface which is cleaned
in a manner as described above and is atomically flat. The
substrate was placed in a reaction chamber which was purged and
then filled with ammonia gas at a pressure of 1.times.10.sup.-6
Torr at a temperature of 900.degree. C. for 4 minutes to form the
layer of crystalline silicon nitride 3 having a thickness of 0.5 nm
on the cleaned surface. The reaction chamber was then purged and
polycrystalline silicon with boron or phosphorous or arsenic was
deposited over the silicon nitride layer in standard manner to
provide the electrode layer 5.
[0019] Referring first to FIG. 2, there is shown a semiconductor
device fabricated in accordance with a second embodiment of the
present invention. The semiconductor device includes a Si (111)
substrate 11 over which is formed a first dielectric layer of
crystalline silicon nitride (Si.sub.3N.sub.4) 13 having a two
monolayer thickness. A second layer of tantalum pentoxide 15 is
then deposited over the silicon nitride having a thickness of 4 nm
followed by a third dielectric layer of silicon nitride 17 having a
two monolayer thickness An electrode layer 19 of boron- or
phorphorous- or arsenic-doped polycrystalline silicon is formed
over the third dielectric layer 17 to form the completed
semiconductor active transistor structure.
[0020] The semiconductor device of FIG. 2 is fabricated by
providing a substrate 11 having an exposed surface as in the first
embodiment. The substrate was placed in a reaction chamber which
was purged and then filled with ammonia gas at a pressure of
1.times.10.sup.-6 Torr at a temperature of 900.degree. C. for 4
minutes to form the first dielectric layer of crystalline silicon
nitride 13 having a thickness of two monolayers on the cleaned
surface. The reaction chamber was then purged and the second
dielectric layer of tantalum pentoxide 15 having a thickness of 4
nm was deposited over the first dielectric layer in standard
manner. The reaction chamber was again purged and the third
dielectric layer of crystalline silicon nitride 17 was deposited
over the second dielectric layer 15 using the same procedure as
used for the first dielectric layer. A layer of polycrystalline
silicon with boron or phosphorous or arsenic was deposited over the
silicon nitride layer in standard manner to provide the electrode
layer 5.
[0021] Though the invention has been described with reference to
specific preferred embodiments thereof, many variations and
modification will immediately become apparent to those skilled in
the art. It is therefore the intention that the appended claims be
interpreted as broadly as possible in view of the prior art to
include all such variations and modifications.
* * * * *