U.S. patent application number 09/769603 was filed with the patent office on 2001-05-31 for methods of reducing proximity effects in lithographic processes.
Invention is credited to Baggenstoss, William, Burdorf, James E., Pierrat, Christophe, Stanton, William.
Application Number | 20010002304 09/769603 |
Document ID | / |
Family ID | 22596084 |
Filed Date | 2001-05-31 |
United States Patent
Application |
20010002304 |
Kind Code |
A1 |
Pierrat, Christophe ; et
al. |
May 31, 2001 |
Methods of reducing proximity effects in lithographic processes
Abstract
Methods of reducing proximity effects in lithographic processes
wherein an integrated circuitry pattern is transferred from a mask
onto a semiconductor substrate are described. In one embodiment, a
desired spacing is defined between a main feature which is to
reside on a mask and which is to be transferred onto the substrate,
and an adjacent proximity effects-correcting feature. After the
spacing definition, the dimensions of the main feature are adjusted
relative to the proximity effects-correcting feature to achieve a
desired transferred main feature dimension. In another embodiment,
a desired spacing is defined between a main feature having an edge
and an adjacent sub-resolution feature. The edge of the main
feature is moved relative to the sub-resolution feature to achieve
a desired transferred main feature dimension.
Inventors: |
Pierrat, Christophe; (Boise,
ID) ; Burdorf, James E.; (Tualitin, OR) ;
Baggenstoss, William; (Boise, ID) ; Stanton,
William; (Boise, ID) |
Correspondence
Address: |
WELLS ST JOHN ROBERTS GREGORY AND MATKIN
SUITE 1300
601 W FIRST AVENUE
SPOKANE
WA
992013828
|
Family ID: |
22596084 |
Appl. No.: |
09/769603 |
Filed: |
January 24, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09769603 |
Jan 24, 2001 |
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09564296 |
May 3, 2000 |
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09564296 |
May 3, 2000 |
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09164786 |
Oct 1, 1998 |
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6120952 |
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Current U.S.
Class: |
430/30 ;
430/5 |
Current CPC
Class: |
G03F 1/36 20130101; G03F
7/70441 20130101 |
Class at
Publication: |
430/30 ;
430/5 |
International
Class: |
G03F 009/00 |
Claims
1. A method of reducing proximity effects in a lithographic process
wherein an integrated circuitry pattern is transferred from a mask
onto a semiconductor substrate, the method comprising: defining a
desired spacing between a main feature which is to reside on the
mask and which is to be transferred onto the substrate and an
adjacent proximity effects-correcting feature; and after said
defining, adjusting the dimensions of the main feature relative to
the proximity effects-correcting feature to achieve a desired
transferred main feature dimension.
2. The method of claim 1, wherein the defining of the desired
spacing comprises selecting a spacing to optimize the depth of
focus in the lithographic process.
3. The method of claim 1, wherein the adjusting of the dimensions
of the main feature comprises changing area size of the main
feature.
4. The method of claim 1, wherein the adjusting of the dimensions
of the main feature comprises changing the shape of the main
feature.
5. The method of claim 1, wherein the adjusting of the dimensions
of the main feature comprises increasing area size of the main
feature.
6. The method of claim 1, wherein the main feature has a plurality
of sides and the adjusting of the dimensions of the main feature
comprises moving at least a portion of one of the sides.
7. The method of claim 1, wherein the main feature has a plurality
of sides and the adjusting of the dimensions of the main feature
comprises moving at least a portion of at least one of the
sides.
8. The method of claim 1, wherein the main feature has first and
second sides which are generally parallel with one another and
laterally displaced from the proximity effects-correcting feature,
and wherein the adjusting of the dimensions of the main feature
comprises moving portions of each of the first and second
sides.
9. The method of claim 1, wherein the defining of the desired
spacing comprises defining said spacing between said main feature
and two proximity effects-correcting features.
10. The method of claim 1, wherein the defining of the desired
spacing comprises defining said spacing between said main feature
and two proximity effects-correcting features, wherein the main
feature has first and second sides which are spaced apart from one
another, and wherein a proximity effects-correcting feature is
disposed on either side of the main feature laterally spaced from a
respective one of the first and second sides, and wherein the
adjusting of the dimensions of the main feature comprises
repositioning at least a portion of one of the first and second
sides relative to its next adjacent proximity effects-correcting
feature.
11. The method of claim 1, wherein the defining of the desired
spacing comprises defining said spacing between said main feature
and two proximity effects-correcting features, wherein the main
feature has first and second sides which are spaced apart from one
another, and wherein a proximity effects-correcting feature is
disposed on either side of the main feature laterally spaced from a
respective one of the first and second sides, and wherein the
adjusting -of the dimensions of the main feature comprises
repositioning portions of each of the first and second sides
relative to its next adjacent proximity effects-correcting
feature.
12. A method of reducing proximity effects in a lithographic
process wherein an integrated circuitry pattern is transferred from
a mask onto a semiconductor substrate, the method comprising:
defining a desired spacing between a main feature which is to
reside on the mask and which is to be transferred onto the
substrate and an adjacent sub-resolution feature, the main feature
having an edge; and moving the edge of the main feature relative to
the sub-resolution feature to achieve a desired transferred main
feature dimension.
13. The method of claim 12, wherein the defining of the desired
spacing comprises selecting the spacing to achieve a desired depth
of focus.
14. The method of claim 12, wherein the moving of the edge
comprises moving said edge away from the sub-resolution
feature.
15. The method of claim 12, wherein the moving of the edge
comprises moving said edge away from the sub-resolution feature,
wherein said moving increases the dimensions of the main
feature.
16. The method of claim 12, wherein the moving of the edge
comprises moving said edge toward the sub-resolution feature.
17. The method of claim 12, wherein the moving of the edge
comprises moving said edge toward the sub-resolution feature,
wherein said moving increases the dimensions of the main
feature.
18. The method of claim 12, wherein said moving increases the
dimensions of the main feature.
19. The method of claim 12, wherein the main feature comprises a
conductive line pattern, and the desired transferred main feature
dimension is approximately equal to a minimum photolithographic
feature size from which the integrated circuitry is fabricated.
20. The method of claim 12, wherein the main feature comprises a
conductive line pattern and said moving increases the dimensions of
the main feature, and wherein the desired transferred main feature
dimension is approximately equal to a minimum photolithographic
feature size from which the integrated circuitry is fabricated.
21. A method of reducing proximity effects in a lithographic
process wherein an integrated circuitry pattern is transferred from
a mask onto a semiconductor substrate, the method comprising:
defining a plurality of main features which are to appear on the
mask and be transferred onto a substrate, the main features having
width dimensions; defining a desired spacing between a
sub-resolution feature and one of the main features; changing a
width dimension of the one main feature and not changing any
dimensions of the sub-resolution feature; and forming a plurality
of patterned main features on the substrate using the mask, said
plurality of main features having substantially common patterned
width dimensions.
22. The method of claim 21, wherein the forming of the plurality of
patterned main features comprises forming said features to have
width dimensions which are approximately equal to the minimum
photolithographic feature size from which the integrated circuitry
is formed.
23. The method of claim 21, wherein the defining of the desired
spacing comprises selecting said spacing to achieve a desired depth
of focus.
24. The method of claim 21, wherein the defining of the plurality
of main features comprises defining at least one conductive line
pattern.
25. The method of claim 21, wherein the defining of the plurality
of main features comprises defining at least one conductive line
pattern, and the forming of the plurality of patterned main
features comprises forming said features to have at least one
conductive line width which is approximately equal to the minimum
photolithographic feature size from which the integrated circuitry
is formed.
26. The method of claim 21, wherein the defining of the plurality
of main features comprises defining a plurality of conductive line
patterns.
27. The method of claim 21, wherein: the defining of the plurality
of main features comprises defining a plurality of conductive line
patterns; said one main feature has a pair of spaced-apart edges;
and wherein said changing of the width dimension of said one main
feature comprises moving one of said edges toward the
sub-resolution feature.
28. The method of claim 21, wherein: the defining of the plurality
of main features comprises defining a plurality of conductive line
patterns; said one main feature has a pair of spaced-apart edges;
and wherein said changing of the width dimension of said one main
feature comprises moving one of said edges toward the
sub-resolution feature, said one edge being the nearest of the
spaced-apart edges relative to the sub-resolution feature.
29. A method of reducing proximity effects in a lithographic
process wherein an integrated circuitry pattern is transferred from
a mask onto a semiconductor substrate, the method comprising:
defining a plurality of main features which are to appear on the
mask at least some of which having width dimensions effective to
form main feature patterns over a substrate with width dimensions
which are no greater than a minimum photolithographic feature size
from which the integrated circuitry is fabricated, one of the main
features being spaced from other main features a distance which is
effective to form a patterned main feature over the substrate which
is spaced from other patterned main features over the substrate a
distance which is greater than the minimum photolithographic
feature size, the one main feature having a pair of edges defining
a first width dimension; defining a desired spacing between the one
main feature and a proximity effects-correcting feature which is to
appear on the mask adjacent the one main feature; and after said
defining of the desired spacing, moving one of the edges of the one
main feature to define a second width dimension which is different
from the first width dimension, said moving enabling a patterned
main feature to be formed on the substrate corresponding to the one
main feature to have a width dimension which is no greater than the
minimum photolithographic feature size.
30. The method of claim 29, wherein the proximity
effects-correcting feature comprises a sub-resolution feature.
31. The method of claim 29, wherein the defining of the desired
spacing comprises defining said spacing to achieve a maximum depth
of focus.
32. The method of claim 29, wherein the moving of the one edge of
the one main feature comprises moving the edge nearest the
proximity effects-correcting feature.
33. The method of claim 29, wherein the moving of the one edge of
the one main feature comprises moving the edge nearest the
proximity effects-correcting feature toward said proximity
effects-correcting feature.
34. The method of claim 29, wherein the second width is greater
than the first width.
35. The method of claim 29, wherein the moving of the one edge of
the one main feature comprises moving the edge nearest the
proximity effects-correcting feature, and wherein the second width
is greater than the first width.
36. The method of claim 29, wherein the defining of the plurality
of main features comprises defining a plurality of conductive line
patterns.
Description
TECHNICAL FIELD
[0001] The present invention relates to methods of reducing
proximity effects in lithographic processes.
BACKGROUND OF THE INVENTION
[0002] Fabrication of integrated circuitry typically involves
lithographically transferring a pattern which is disposed on a mask
onto a layer of material such as photoresist received over a
substrate. The pattern on the mask generally defines integrated
circuitry patterns and alignment patterns. It has been observed
that differences in pattern development of circuit features can
depend upon the proximity of the features relative to one another.
So-called "proximity effects" in a lithographic process can arise
during imaging, resist pattern formation, and subsequent pattern
transfer steps such as etching. The magnitude of the proximity
effects depends on the proximity or closeness of the two features
present on the masking pattern. Proximity effects are known to
result from optical diffraction in the projection system used to
form the pattern over the substrate. This diffraction causes
adjacent features to interact with one another in such a way as to
produce pattern-dependent variations. These variations can affect
the integrity of the finished devices.
[0003] This invention arose out of concerns associated with
improving the manner in which integrated circuitry is formed. In
particular, this invention arose out of concerns associated with
reducing proximity effects.
SUMMARY OF THE INVENTION
[0004] Methods of reducing proximity effects in lithographic
processes wherein an integrated circuitry pattern is transferred
from a mask onto a semiconductor substrate are described. In one
embodiment, a desired spacing is defined between a main feature
which is to reside on a mask and which is to be transferred onto
the substrate, and an adjacent proximity effects-correcting
feature. After the spacing definition, the dimensions of the main
feature are adjusted relative to the proximity effects-correcting
feature to achieve a desired transferred main feature dimension. In
another embodiment, a desired spacing is defined between a main
feature having an edge and an adjacent sub-resolution feature. The
edge of the main feature is moved relative to the sub-resolution
feature to achieve a desired transferred main feature
dimension.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings.
[0006] FIG. 1 is a top plan view of a portion of a mask
pattern.
[0007] FIG. 2 is a top plan view of a portion of a mask pattern in
accordance with one embodiment of the invention.
[0008] FIG. 3 is a top plan view of a mask pattern in accordance
with one embodiment of the present invention.
[0009] FIG. 4 is a side elevational view of the semiconductor wafer
fragment which has been processed in accordance with one embodiment
of the invention.
[0010] FIG. 5 is a top plan view of a portion of a mask pattern in
accordance with one embodiment of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011] This disclosure of the invention is submitted in furtherance
of the constitutional purposes of the U.S. Patent Laws "to promote
the progress of science and useful arts" (Article 1, Section
8).
[0012] Referring to FIG. 1, a portion of a mask pattern on a mask
is shown generally at 10 and comprises at least one main feature 12
and at least one proximity effects-correcting feature 14. In this
example, two proximity effects-correcting features 14 are shown.
Mask 10 is to be utilized in a lithographic process wherein an
integrated circuitry pattern corresponding to main feature 12 is
transferred from the mask onto a semiconductor substrate. In the
illustrated example, main feature 12 has a plurality of sides or
edges 16, 18 which define a first width dimension. For purposes of
the ongoing discussion, side 16 comprises a first side and side 18
comprises a second side. The illustrated first and second sides are
generally parallel with one another and are laterally displaced
from proximity effects-correcting features 14. A proximity
effects-correcting feature is disposed on either side of main
feature 12. It is possible, however, for only one proximity
effects-correcting feature to be disposed on one side of main
feature 12.
[0013] In the illustrated and preferred embodiment,
proximity-effects correcting features 14 comprise sub-resolution
features which are not ultimately transferred onto the substrate.
In this example, main feature 12 comprises a conductive line
pattern which is to be transferred onto a substrate. Any number of
main features can be defined on the mask. Accordingly, a plurality
of main features comprising conductive line patterns can be defined
on the mask. Main feature 12 and proximity effects-correcting
features 14 each have respective width dimensions, with the width
dimension of the proximity effects-correcting features 14 being
shown at S, and the width of main feature 12 being shown at
CD.sub.1. The proximity effects-correcting features can have
different widths.
[0014] In accordance with one embodiment of the invention, a
desired spacing D.sub.1 is defined between main feature 12 and at
least one adjacent proximity effects-correcting feature 14. The
desired spacing between the main feature and the proximity
effects-correcting features can be the same, as is shown, or can be
different. In this example, and because there are two illustrated
proximity effects-correcting features, two such desired spacings
are defined which happen to be the same in magnitude. In one
embodiment, the definition of the desired spacing is conducted to
optimize the depth of focus (DOF) in the lithographic process.
Depth of focus is an important characteristic of an exposure tool
and is defined as the range in which the aerial image (of a near
resolution sized feature) will stay in focus. In a lithographic
process in which an image is transferred into a photoresist layer,
a minimum or optimized DOF is required. This minimum or optimized
DOF ensures that the image remains sufficiently in focus throughout
the resist layer. Thus, the minimum or optimized DOF range is
typically greater than or equal to the thickness of the resist
layer. Other parameters can, of course, be considered in the
context of defining the desired spacing between a main feature and
a proximity effects-correcting feature, e.g. exposure latitude and
image log slope.
[0015] Referring to FIG. 2, the dimensions or shape of main feature
12 are adjusted relative to the proximity effects-correcting
feature (S) to achieve a desired transferred main feature
dimension. The dimensional or shape adjustment of the main feature
can take place through a change in the area size of the main
feature. In the illustrated example, the area size of main feature
12 is adjusted by increasing the area size from that which is shown
in FIG. 1 to that which is shown in FIG. 2. Such adjustment takes
place by moving at least a portion of one or both of sides or edges
16, 18 from its previous position (shown in dashed lines), to its
illustrated position in FIG. 2. In this example, both of sides or
edges 16, 18 are moved or repositioned relative to their original
positions.
[0016] The adjustment of the main feature dimension can take place
through movement of an associated side or edge, or a portion(s)
thereof, either toward or away from an adjacent proximity
effects-correcting feature. Where only one proximity
effect-correcting feature is used, movement of the associated side
of the main feature can take place toward or away from the
proximity effects-correcting feature. In this example, each side is
repositioned by moving it closer to or toward its next adjacent
proximity effects-correcting feature; Movement of one or more of
the edges can, however, be conducted away from a proximity
effects-correcting feature or, particularly, away from a
next-adjacent proximity effects-correcting feature. Such movement
can either increase or decrease the dimensions of the main feature.
The main feature shape or dimension can also be adjusted by moving
individual portions of individual sides toward or away from the
proximity effects-correcting feature. Such can result in a
staggered construction such as is shown in FIG. 5.
[0017] In a preferred embodiment, the desired transferred main
feature dimension which is ultimately formed over a substrate is
approximately equal to a minimum photolithographic feature size
from which the integrated circuitry is fabricated. This will become
more apparent in connection with the discussion relative to FIG.
4.
[0018] In a preferred embodiment, a width dimension of main feature
12, i.e. CD.sub.1, is changed without changing any dimensions of
the proximity effects-correcting or sub-resolution features.
Specifically, and as is apparent from a comparison of FIGS. 1 and
2, CD.sub.2 of main feature 12 is different from and, in this
example greater than CD.sub.1 in FIG. 1. At the same time, the
widths of the proximity effects-correcting features 14, i.e. S, are
consistent between FIGS. 1 and 2. Such change in main feature width
also changes the spacing between the main feature and its
associated proximity effects-correcting feature. Specifically, a
spacing D.sub.2 (FIG. 2) is defined between the main feature and
each of the associated proximity effects-correcting features 14. In
this example, D.sub.2 is less than D.sub.1. The spacing D.sub.2 can
vary as between a main feature's sides and the next-adjacent
proximity effects-correcting features, or between different
portions of a main feature's side and the next-adjacent proximity
effects-correcting feature for that side.
[0019] Referring to FIG. 3, a plurality of main features 20, 22,
24, and 26, e.g. conductive line patterns, are defined on a mask.
As initially defined, however, and not specifically illustrated
here, main features 20-26 would have substantially common width
dimensions. However, due to proximity effects, the ultimately
provided patterned main features over the substrate corresponding
to the main features on a mask would not result in
uniformly-patterned main features over the substrate.
[0020] As ultimately provided on mask 10, however, main features
22, 24, and 26 would have width dimensions comparable to CD.sub.1
which is shown in FIG. 1, and main feature 20 would have a width
dimension comparable to CD.sub.2 which is shown in FIG. 2. With
these width dimensions, main feature patterns can be formed over a
substrate with width dimensions which are no greater than a minimum
photolithographic feature size from which the integrated circuitry
is fabricated. Main feature 20, and more likely a plurality of
similar main features are spaced from other main features a
distance which is effective to form one or more patterned main
features over the substrate which is (are) spaced from other
patterned main features a distance which is greater than the
minimum photolithographic feature size. This variation in spacing
is one factor which can lead to proximity effect-related
irregularities in the ultimately patterned feature.
[0021] Prior to provision of the illustrated mask in FIG. 3,
processing can take place with respect to main feature 20 as
described above in connection with FIGS. 1 and 2. Specifically, a
desired spacing is defined between main feature 20 and at least one
proximity effects-correcting features 28, 30. After definition of
the desired spacing which, in a preferred embodiment, is selected
to achieve a desired depth of focus (DOF), at least portions of one
or more of the sides or edges of main feature 20 are moved or
repositioned to define a second width dimension (corresponding to
CD.sub.2 in FIG. 2) which is different from the first
originally-defined width dimension. In the illustrated example,
both of the sides or edges have been moved or repositioned to be
closer to their next adjacent or nearest proximity
effects-correcting feature 28, 30. Accordingly, such movement
increases the area size of the main feature 20. Changing the
dimensional size, shape, or area of the main feature as just
described, relative to one or more adjacent proximity
effects-correcting features, can enable a patterned main feature to
be formed on the substrate to have a width dimension which is no
greater than a minimum photolithographic feature size which is
utilized to form the integrated circuitry.
[0022] For example, and with respect to FIG. 4, a plurality of
conductive lines 20a, 22a, 24a, and 26a are formed over a substrate
32. Lines 20a-26a have been formed through the use of a mask such
as one containing main feature patterns 20-26. As can be seen, each
formed conductive line has a width w which, in a preferred
embodiment, is no greater than the minimum photolithographic
feature size from which the integrated circuitry is formed. It will
be observed that the conductive line 20a (corresponding to main
feature 20 (FIG. 3)) has a width which is similar to, or the same
as the widths of conductive lines 22a-26a which are spaced closer
together. Accordingly, proximity effects which previously affected
the subsequently patterned main feature widths have been
substantially reduced, if not eliminated. Thus, lines 20a-26a have
substantially common patterned width dimensions.
[0023] Advantages achieved by the various embodiments of the
invention include better dimensional control of substrate features
through correction of the defined main features after placement of
the proximity effects-correcting features. This can also reduce
processing overhead through reductions in the data volume required
to implement the various methods by the various industry processors
utilized to do so.
[0024] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *