U.S. patent application number 09/759570 was filed with the patent office on 2001-05-24 for method of forming an intermetal dielectric layer.
Invention is credited to Liu, Chih-chien, Tsai, Cheng-Yuan, Yang, Ming-Sheng.
Application Number | 20010001678 09/759570 |
Document ID | / |
Family ID | 21642744 |
Filed Date | 2001-05-24 |
United States Patent
Application |
20010001678 |
Kind Code |
A1 |
Tsai, Cheng-Yuan ; et
al. |
May 24, 2001 |
Method of forming an intermetal dielectric layer
Abstract
A method is used to form an intermetal dielectric layer.
According to the invention, an unbiased-unclamped fluorinated
silicate glass layer used as a protection layer is formed by high
density plasma chemical vapor deposition on a biased-clamped
fluorinated silicate glass layer formed by high density plasma
chemical vapor deposition to prevent the biased-clamped fluorinated
silicate glass layer from being exposed in a planarization
process.
Inventors: |
Tsai, Cheng-Yuan; (Yunlin
Hsien, TW) ; Liu, Chih-chien; (Taipei, TW) ;
Yang, Ming-Sheng; (Hsinchu, TW) |
Correspondence
Address: |
THOMAS, KAYDEN, HORSTEMEYER & RISLEY, LLP
100 GALLERIA PARKWAY, NW
STE 1750
ATLANTA
GA
30339-5948
US
|
Family ID: |
21642744 |
Appl. No.: |
09/759570 |
Filed: |
January 11, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09759570 |
Jan 11, 2001 |
|
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|
09471055 |
Dec 22, 1999 |
|
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Current U.S.
Class: |
427/58 ;
257/E21.244; 257/E21.276; 257/E21.576; 427/569; 427/585 |
Current CPC
Class: |
H01L 21/02304 20130101;
H01L 21/02362 20130101; H01L 21/02274 20130101; H01L 21/76829
20130101; H01L 21/31629 20130101; H01L 21/31053 20130101; H01L
21/02131 20130101; H01L 21/76801 20130101 |
Class at
Publication: |
427/58 ; 427/585;
427/569 |
International
Class: |
B05D 005/12; C23C
008/00 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 22, 1999 |
TW |
88118307 |
Claims
What is claimed is:
1. A method for forming an intermetal dielectric layer, comprising:
providing a substrate; forming a plurality of metal conductive
lines on the substrate, wherein a tied conductive line region and a
loose conductive line region consist of the plurality of metal
conductive lines, forming an intermetal dielectric layer on the
substrate; forming a protection layer on the intermetal dielectric
layer wherein the protection layer is thinner than the intermetal
dielectric layer; forming a cap layer on the protection layer; and
performing a planarization process.
2. The method for forming the intermetal dielectric layer according
to claim 1 wherein the intermetal dielectric layer comprises
fluorinated silicon glass.
3. The method for forming the intermetal dielectric layer according
to claim 1. wherein the formation of the intermetal dielectric
layer comprises biased-clamped high density plasma chemical vapor
deposition.
4. The method for forming the intermetal dielectric layer according
to claim 3. wherein the biased-clamped high density plasma chemical
vapor deposition is performed under a bias and helium cooling is
employed.
5. The method for forming the intermetal dielectric layer according
to claim 1, wherein the protection layer comprises fluorinated
silicon glass.
6. The method for forming the intermetal dielectric layer according
to claim 1, wherein the formation of the protection dielectric
layer comprises unbiased-unclamped high density plasma chemical
vapor deposition.
7. The method for forming the intermetal dielectric layer according
to claim 6, wherein the unbiased-unclamped high density plasma
chemical vapor deposition is performed without a bias and without
helium cooling.
8. The method for forming the intermetal dielectric layer according
to claim 1, wherein the protection layer is used as a stop
layer.
9. The method for forming the intermetal dielectric layer according
to claim 1, wherein the cap layer comprises an oxide layer.
10. The method for forming the intermetal dielectric layer
according to claim 1, wherein the formation of the cap layer
comprises plasma enhanced chemical vapor deposition.
11. The method for forming the intermetal dielectric layer
according to claim 1, wherein before forming the intermetal
dielectric layer, the process further comprises forming a undoped
silicon glass layer.
12. The method for forming the intermetal dielectric layer
according to claim l wherein the planarization process comprises a
chemical mechanical polishing process.
13. A method for forming an intermetal dielectric layer,
comprising: providing a substrate; forming a plurality of metal
conductive lines on the substrate; forming a first dielectric layer
on the substrate; forming a second dielectric layer on the first
dielectric layer; forming a cap layer on the second dielectric
layer; and performing a planarization process.
14. The method for forming the intermetal dielectric layer
according to claim 13, wherein the formation of the intermetal
dielectric layer comprises biased-clamped high density plasma
chemical vapor deposition.
15. The method for forming the intermetal dielectric layer
according to claim 14, wherein the biased-clamped high density
plasma chemical vapor deposition is performed under a bias and
helium cooling is employed.
16. The method for forming the intermetal dielectric layer
according to claim 13 wherein the formation of the protection
dielectric layer comprises unbiased-unclamped high density plasma
chemical vapor deposition.
17. The method for forming the intermetal dielectric layer
according to claim 16, wherein the unbiased-unclamped high density
plasma chemical vapor deposition is performed without a bias and
without helium cooling.
18. The method for forming the intermetal dielectric layer
according to claim 13, wherein the cap layer comprises an oxide
layer.
19. The method for forming the intermetal dielectric layer
according to claim 13 wherein the second dielectric layer is used
as a stop layer.
20. The method for forming the intermetal dielectric layer
according to claim 13, wherein before forming the first dielectric
layer, the process further comprises forming an undoped silicon
glass layer.
21. A method for forming an intermetal dielectric layer, wherein
the method applies to a substrate and a plurality of metal
conductive lines is formed on the substrate, the method comprising:
forming a dielectric layer on the substrate; forming a protection
layer on the dielectric layer; forming a cap layer on the
protection layer; and performing a planarization process.
22. The method for forming the intermetal dielectric layer
according to claim 21, wherein the formation of the intermetal
dielectric layer comprises biased-clamped high density plasma
chemical vapor deposition.
23. The method for forming the intermetal dielectric layer
according to claim 22, wherein the biased-clamped high density
plasma chemical vapor deposition is performed under a bias and
helium cooling is employed.
24. The method for forming the intermetal dielectric layer
according to claim 21, wherein the protection layer comprises
fluorinated silicon glass.
25. The method for forming the intermetal dielectric layer
according to claim 21, wherein the formation of the protection
dielectric layer comprises unbiased-unclamped high density plasma
chemical vapor deposition.
26. The method for forming the intermetal dielectric layer
according to claim 25, wherein the unbiased-unclamped high density
plasma chemical vapor deposition is performed without a bias and
without helium cooling.
27. The method for forming the intermetal dielectric layer
according to claim 21, wherein the cap layer comprises an oxide
layer.
28. The method for forming the intermetal dielectric layer
according to claim 21, wherein the second dielectric layer is used
as a stop layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a method for forming an integrated
circuit, and more particularly, to a method for forming an
intermetal dielectric layer with multilevel interconnects.
[0003] 2. Description of the Related Art
[0004] In an integrated circuit with two or more levels of
interconnects, an intermetal dielectric layer must be placed
between the levels for isolation. Generally, the intermetal
dielectric layer must have characteristics such as good
reliability, good mechanical stability, good compatibility, low
water absorption capability, etc.
[0005] A typical material for the intermetal dielectric layer is
silicon oxide that has a dielectric constant of about 4. However,
since a device having a higher operation speed requires a material
having a lower dielectric constant as the intermetal dielectric
layer, fluorinated silicon glass (FSG) having a dielectric constant
of about 3.5 is replacing the silicon oxide as the intermetal
dielectric layer.
[0006] According to the prior art, the method to form the
intermetal dielectric layer is as follows. A plurality of metal
conductive lines is formed on a substrate. The plurality of metal
conductive lines is distributed in two regions, respectively, a
tied conductive line region (i.e. a dense line region) having a
higher distribution density and a loose conductive line region
(i.e. a iso line region) having a lower distribution density. A
biased-clamped FSG layer is formed on the substrate by high density
plasma chemical vapor deposition (HDPCVD), and fills gaps between
metal lines. Before the biased-clamped FSG layer is formed, the
process further comprises forming a silicon glass liner layer by
HDPCVD. The silicon glass liner layer is used to prevent the metal
lines from being attacked by fluorine. Then, an oxide layer is
formed as a cap layer on the biased-clamped FSG layer by plasma
enhanced chemical vapor deposition (PECVD). A chemical mechanical
polishing process is subsequently performed on the oxide layer.
[0007] Due to different distribution densities, the spacing between
conductive lines in different regions (the tied conductive line
region and the loose conductive line region) is different. This may
result in a large step height difference between the tied
conductive line region and the loose conductive line region after
the biased-clamped FSG layer and the cap layer are formed. Thus,
the polishing stop for chemical mechanical polishing is difficult
to control, and over-polishing easily arises. As a result, the
biased-clamped FSG layer may be exposed. Since the amount of
fluorine in the biased-clamped FSG layer is difficult to control,
and the biased-clamped FSG layer exhibits intrinsically hydrophilic
behavior, the biased-clamped FSG layer easily absorbs water when
the biased-clamped FSG layer contacts is in contact with an aqueous
base slurry during chemical mechanical polishing process. Thus, the
reaction product produced during chemical mechanical polishing
process can result in metal corrosion, oxide degradation. peeling
at the metal/intermetal dielectric layer interface, and an
increased dielectric constant. Furthermore, when a metal plug is
formed, the HF can poison the metal plug. the contact resistance is
increased and the increased contact resistance can affect the
subsequent process.
SUMMARY OF THE INVENTION
[0008] According to above, the invention provides a method for
forming an improved intermetal dielectric layer. In order to
prevent the biased-clamped FSG layer from being exposed, the method
provides an unbiased-unclamped FSG layer as a protect layer on the
biased-clamped FSG layer.
[0009] The method comprises the following steps. A plurality of
metal lines is formed on a substrate. A biased-clamped FSG layer is
formed on the substrate by HDPCVD. An unbiased-unclamped FSG layer
as a protection layer is formed on the biased-clamped FSG layer by
HDPCVD. An oxide layer as a cap layer is formed on the protection
layer. A planarization process is performed on the oxide layer.
[0010] The unbiased-unclamped FSG layer is used as a protection
layer in the invention to prevent the biased-clamped FSG layer from
being exposed during a planarization process and attacked by
water.
[0011] It is to be understood that both the foregoing general
description and the following detailed description are exemplary,
and are intended to provide further explanation of the invention as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1A through FIG. 1C are schematic, cross-sectional views
showing a process for forming an intermetal dielectric layer
according to a first preferred embodiment of the invention;
[0013] FIG. 2 shows the relationship between the penetration depth
(nm) in the unbiased-clamped FSG layer and hydrogen concentration
using Secondary Ion Mass Spectroscopy (SIMS); and
[0014] FIG. 3 shows the relationship between the penetration depth
(nm) in the unbiased-clamped FSG layer and fluorine concentration
using Secondary Ion Mass Spectroscopy.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0015] FIGS. 1A through FIG. 1C are schematic, cross-sectional
views showing a process for forming an intermetal dielectric layer
according to a first preferred embodiment of the invention.
[0016] Referring to FIG. 1A, a substrate 100 is provided. A
plurality of metal conductive lines 102a, 102b, and 102c is formed
on the substrate 100. A tied conductive line region 104a and a
loose conductive line region 104b consist of the plurality of metal
conductive lines 102a, 102b, and 102c.
[0017] Referring to FIG. 1B, a dielectric layer 106 is formed on
the substrate 100. Due to different spacings among the metal
conductive lines 102a, 102b, and 102c, the height of the dielectric
layer 106 is not uniform. The dielectric layer 106 comprises
biased-clamped fluorinated silicon glass (FSG) formed by, for
example, high density plasma chemical vapor deposition (HDPCVD).
The dielectric constant of the biased-clamped FSG is about 3.5,
which depends on the process variation. The FSG is widely used as
an intermetal dielectric material because of its low dielectric
constant, capability of decreasing capacitance between
interconnects, and good gap-filling capability.
[0018] In addition, before forming the dielectric layer 106, an
undoped silicon glass liner layer can be formed on the substrate
100 by, for example, HDPCVD. Since the undoped silicate glass liner
layer has good compatibility with the FSG layer, the undoped
silicate glass liner layer can promote adhesion between the FSG
layer and another material layer and benefit the subsequent
process.
[0019] Although the dielectric constant of the undoped silicon
glass liner layer is about 4.1, it is very thin; thus, the undoped
silicon glass liner layer does not affect the overall dielectric
constant of the internetal dielectric layer.
[0020] A protection layer 108 is formed on the dielectric layer
106. The protection layer 108 comprises unbiased-unclamped FSG
formed by, for example, HDPCVD. The dielectric constant of the
unbiased-unclamped FSG is about 3.5, which thickness depends on the
process. "Unbiased" means that no bias is applied during performing
the HDPCVD, and "unclamped" means that there is no helium cooling
device on the backside of the substrate 100 during the deposition,
or that no helium cooling process is performed on the substrate 100
during the deposition.
[0021] Since the depositing rate of the unbiased-unclamped FSG
layer (the protection layer 108) formed by HDPCVD is greater than
that of the biased-clamped FSG layer (the dielectric layer 106)
formed by HDPCVD, the throughout is not affected by the process of
first forming the dielectric layer 106 to a thinner thickness than
in the prior art and then forming the protection layer 108 to an
adequate thickness.
[0022] Since the dielectric constant of the protection layer 108 is
nearly the same as that of the dielectric layer 106, the protection
layer 108 does not affect the overall dielectric constant of the
intermetal dielectric layer.
[0023] A cap layer 110 is formed on the protection layer 108. The
cap layer 110 is, for example, an oxide layer formed by HDPCVD or
by PECVD. Referring to FIG. 1C, a planarization process such as
chemical mechanical polishing (CMP) is performed on the cap layer
110.
[0024] Since the unbiased-unclamped FSG layer has a lower water
absorption capability than the conventional FSG layer, if the
unbiased-unclamped FSG layer is exposed due to the chemical
mechanical polishing process, the unbiased-unclamped FSG layer does
not react with an aqueous slurry or water to produce hydrogen
fluoride (HF). Thus, the protection layer 108 can prevent the
dielectric layer 106 from being over-etched as occurred in the
prior art.
[0025] FIG. 2 shows the relationship between the penetration depth
(nm) in the unbiased-unclamped FSG layer and hydrogen concentration
using Secondary Ion Mass Spectroscopy (SIMS). FIG. 3 shows the
relationship between the penetration depth (nm) in the
unbiased-clamped FSG layer and fluorine concentration using
secondary ion mass spectroscopy.
[0026] Referring to FIG. 2 and Table 1, there is no obvious change
in the hydrogen concentrations before and after CMP. This indicates
that the unbiased-unclamped FSG layer efficiently prevents the HF
from being produced, and further prevents metal corrosion, oxide
degradation, peeling at the metal/intermetal dielectric layer
interface, and an increased dielectric constant.
1 TABLE 1 Fluorine concentration in Hydrogen concentration in
percentage (%)* percentage (%)** Before the 13.17 0.140 CMP After
the CMP 13.13 0.126 *obtained by Fourier Transfer Infra-Red
**obtained by Secondary Ion Mass Spectroscopy
[0027] Referring to FIG. 3 and Table 1, there is no obvious
variation in the fluorine concentrations before and after CMP. This
indicates that the unbiased-unclamped FSG layer efficiently
prevents the HF from being produced, and further prevents metal
corrosion, oxide degradation, peeling at the metal/intermetal
dielectric layer interface. and an increased dielectric
constant.
[0028] In addition, the invention not only applies to the
multilevel interconnect process, but also applies to, for example,
the metal plug process, the dual damascene process, the dielectric
layer depositing process between the conductive lines, etc.
[0029] Other embodiments of the invention will appear to those
skilled in the art from consideration of the specification and
practice of the invention disclosed herein. It is intended that the
specification and examples be considered as exemplary only, with a
true scope and spirit of the invention being indicated by the
following claims.
* * * * *