U.S. patent application number 09/745626 was filed with the patent office on 2001-05-10 for process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration.
This patent application is currently assigned to Vantis Corporation. Invention is credited to Mehta, Sunil, Ngo, Minh Van.
Application Number | 20010001075 09/745626 |
Document ID | / |
Family ID | 25240229 |
Filed Date | 2001-05-10 |
United States Patent
Application |
20010001075 |
Kind Code |
A1 |
Ngo, Minh Van ; et
al. |
May 10, 2001 |
Process for fabricating semiconductor memory device with high data
retention including silicon nitride etch stop layer formed at high
temperature with low hydrogen ion concentration
Abstract
A semiconductor memory device such as a flash Electrically
Erasable Programmable Read-Only Memory (Flash EEPROM) includes a
floating gate with high data retention. A tungsten damascene local
interconnect structure includes a silicon nitride etch stop layer
which is formed using Plasma Enhanced Chemical Vapor Deposition
(PECVD) at a temperature of at least 480.degree. C. such that the
etch stop layer has a very low concentration of hydrogen ions. The
minimization of hydrogen ions, which constitute mobile positive
charge carriers, in the etch stop layer, minimizes recombination of
the hydrogen ions with electrons on the floating gate, and thereby
maximizes data retention of the device.
Inventors: |
Ngo, Minh Van; (Union City,
CA) ; Mehta, Sunil; (San Jose, CA) |
Correspondence
Address: |
Jurgen Vollrath
ARTER & HADDEN LLP
Two Embarcadero Center, Fifth Floor
San Francisco
CA
94111
US
|
Assignee: |
Vantis Corporation
|
Family ID: |
25240229 |
Appl. No.: |
09/745626 |
Filed: |
December 20, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09745626 |
Dec 20, 2000 |
|
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|
08823953 |
Mar 25, 1997 |
|
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6190966 |
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Current U.S.
Class: |
438/257 ;
257/E21.422; 257/E21.682; 257/E29.129; 438/637; 438/792;
438/970 |
Current CPC
Class: |
Y10S 438/97 20130101;
H01L 27/11521 20130101; H01L 29/66825 20130101; H01L 29/42324
20130101 |
Class at
Publication: |
438/257 ;
438/792; 438/970; 438/637 |
International
Class: |
H01L 021/336; H01L
021/31; H01L 021/469; H01L 021/4763 |
Claims
We claim:
1. A process for fabricating a semiconductor structure having a
local interconnect, comprising the steps of: (a) providing a
semiconductor substrate; (b) forming a semiconductor device having
an interconnect area on a surface of the substrate; (c) forming a
silicon nitride etch stop layer over the surface of the substrate
and the device at a temperature of at least approximately
480.degree. C.; (d) forming an insulator layer over the etch stop
layer; (e) etching a first hole through the insulator layer to the
etch stop layer in alignment with the interconnect area; (f)
etching a second hole through the etch stop layer to the
interconnect area; and (g) filling the first and second holes with
an electrically conductive material which ohmically contacts the
interconnect area to form the local interconnect.
2. A process as in claim 1, in which step (e) comprises etching the
first hole using Reactive Ion Etching (RIE) with
octafluorobutene.
3. A process as in claim 1, in which step (f) comprises etching the
second hole using Reactive Ion Etching (RIE) with
fluoromethane.
4. A process as in claim 1, in which: step (a) comprises providing
the substrate of silicon; and step (b) comprises the substeps of:
(b1) forming a layer of a refractory metal silicide material over
the interconnect area; and (b2) reacting the silicide material with
underlying silicon to form the interconnect area as a silicide.
5. A process as in claim 1, in which step (g) comprises filling the
first and second holes with tungsten to form the local interconnect
as a tungsten damascene.
6. A process as in claim 1, in further comprising the step,
performed between steps (d) and (e), of: (h) planarizing the
insulator layer using chemical mechanical polishing.
7. A process as in claim 1, in which step (d) comprises forming the
insulator layer of tetraethylorthosilicate (TEOS) glass.
8. A process as in claim 1, in which step (c) comprises forming the
etch stop layer at a temperature of approximately 500.degree.
C.
9. A process as in claim 1, in which step (c) comprises forming the
etch stop layer at a temperature in the range of approximately
470.degree. C. to 550.degree. C.
10. A process as in claim 9, in which: step (c) comprises forming
the etch stop layer using Plasma Enhanced Chemical Vapor Deposition
(PECVD) with: an SiH.sub.4 flow rate of approximately 55.+-. 5
sccm; an NH.sub.3 flow rate of approximately 12.+-. 2 sccm; and an
RF power of approximately 375.+-. 10 watts.
11. A process as in claim 10, in which step (c) further comprises
forming the etch stop layer with an N.sub.2 flow rate of
approximately 4,000 sccm.
12. A process as in claim 10, in which step (c) further comprises
forming the etch stop layer at a pressure of approximately 3.5.+-.
0.2 torr.
13. A process as in claim 10, in which step (c) further comprises
forming the etch stop layer with a spacing between a PECVD shower
head and the surface of the substrate of approximately 9.5
millimeters.
14. A process as in claim 1, in which step (c) comprises forming
the etch stop layer to a thickness of approximately 800.+-.50
.ANG..
15. A process for fabricating a semiconductor structure, comprising
the steps of: (a) providing a semiconductor substrate; (b) forming
a semiconductor device on a surface of the substrate; and (c)
forming a silicon nitride layer over the surface of the substrate
and the device at a temperature of at least approximately
480.degree. C.
16. A process as in claim 15, in which step (c) comprises forming
the silicon nitride layer at a temperature of approximately
500.degree. C.
17. A process as in claim 15, in which step (c) comprises forming
the silicon nitride layer at a temperature in the range of
approximately 470.degree. C. to 550.degree. C.
18. A process as in claim 17, in which: step (c) comprises forming
the silicon nitride layer using Plasma Enhanced Chemical Vapor
Deposition (PECVD) with: an SiH.sub.4 flow rate of approximately
55.+-. 5 sccm; an NH.sub.3 flow rate of approximately 12.+-. 2
sccm; and an RF power of approximately 375.+-. 10 watts.
19. A process as in claim 18, in which step (c) further comprises
forming the silicon nitride layer with an N.sub.2 flow rate of
approximately 4,000 sccm.
20. A process as in claim 18, in which step (c) further comprises
forming the silicon nitride layer at a pressure of approximately
3.5.+-. 0.2 torr.
21. A process as in claim 18, in which step (c) further comprises
forming the silicon nitride layer with a spacing between a PECVD
shower head and the surface of the substrate of approximately 9.5
millimeters.
22. A process as in claim 15, in which step (c) comprises forming
the silicon nitride layer to a thickness of approximately 800.+-.
50 .ANG..
23. A semiconductor structure, comprising: a semiconductor
substrate; a semiconductor device formed on a surface of the
substrate; and a silicon nitride layer formed over the surface of
the substrate and the device at a temperature of at least
approximately 480.degree. C.
24. A structure as in claim 23, in which: the device comprises an
interconnect area; the silicon nitride layer is an etch stop layer;
and the structure further comprises: an insulating layer formed
over the etch stop layer; a first hole formed through the insulator
layer to the etch stop layer in alignment with the interconnect
area; a second hole formed through the etch stop layer to the
interconnect area; and an electrically conductive material which
fills the first and second holes and ohmically contacts the
interconnect area to form a local interconnect.
25. A structure as in claim 23, in which the device comprises a
memory cell having a floating element.
26. A structure as in claim 25, in which: the memory cell comprises
a Metal-Oxide-Semiconductor (MOS) transistor; and the floating
element comprises a floating gate.
27. A structure as in claim 23, in which the silicon nitride layer
is formed at a temperature of approximately 500.degree. C.
28. A structure as in claim 23, in which the silicon nitride layer
is formed at a temperature in the range of approximately
470.degree. C. to 550.degree. C.
29. A structure as in claim 28, in which the silicon nitride layer
is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD),
with: an SiH.sub.4 flow rate of approximately 55.+-. 5 sccm; an
NH.sub.3 flow rate of approximately 12.+-. 2 sccm; and an RF power
of approximately 375.+-.10 watts.
30. A structure as in claim 29, in which the silicon nitride layer
is formed with an N.sub.2 flow rate of approximately 4,000
sccm.
31. A structure as in claim 29, in which the silicon nitride layer
is formed at a pressure of approximately 3.5.+-. 0.2 torr.
32. A structure as in claim 29, in which the silicon nitride layer
is formed with a spacing between a PECVD shower head and the
surface of the substrate of approximately 9.5 millimeters.
33. A structure as in claim 23, in which the silicon nitride layer
has a thickness of approximately 800.+-.50 .ANG..
34. A structure as in claim 23, in which: the structure is a flash
Electrically Erasable Programmable Read-Only Memory (flash EEPROM);
and the device comprises an erasable memory cell having a floating
element.
35. A structure as in claim 34, in which: the memory cell comprises
a Metal-Oxide-Semiconductor (MOS) transistor; and the floating
element comprises a floating gate.
Description
BACKGROUND OF THE INVENTION
1. 1. Field of the Invention
2. The present invention generally relates to the art of
microelectronic integrated circuits, and more specifically to a
process for fabricating a semiconductor memory device with high
data retention including a silicon nitride etch stop layer formed
at high temperature with a low hydrogen ion concentration.
3. 2. Description of the Related Art
4. A flash or block erase Electrically Erasable Programmable
Read-Only Memory (Flash EEPROM) semiconductor memory includes an
array of cells which can be independently programmed and read. The
size of each cell and thereby the memory are made small by omitting
select transistors which would enable the cells to be erased
independently. All of the cells are erased together as a block.
5. A memory of this type includes individual
Metal-Oxide-Semiconductor (MOS) memory cells, each of which
includes a source, drain, floating gate and control gate to which
various voltages are applied to program the cell with a binary 1 or
0, or erase all of the cells as a block.
6. Tungsten damascene is a process for fabricating local
interconnects which can be advantageously applied to semiconductor
devices including flash EEPROMs. The process includes forming an
insulator layer of, for example, tetraethylorthosilicate (TEOS)
glass over the memory cells, and using Reactive Ion Etching (RIE)
to form vertical interconnect holes through the glass down to
interconnect areas (source, drain, etc.) of the cells. The holes
are filled with tungsten which ohmically contacts the interconnect
areas to form the local interconnects.
7. The TEOS etch is conventionally performed using octafluorobutene
(C.sub.4F.sub.8) etchant, which also has a high etch rate for
silicon. For this reason, a mechanism must be provided for
performing the TEOS etch without allowing the etchant to act on the
silicon of the underlying interconnect areas.
8. Such a mechanism includes forming a silicon nitride etch stop
layer underneath the TEOS layer, and performing the etch in two
stages. The first stage is the octafluorobutene etch through the
TEOS layer, which terminates at the etch stop layer since
octafluorobutene has a low etch rate for silicon nitride.
9. Then, a second RIE etch is performed using fluoromethane
(CH.sub.3F), which forms holes through the portions of the etch
stop layer that are exposed through the holes in the TEOS layer,
down to the interconnect areas of the devices. This is possible
because fluoromethane has a high etch rate for silicon nitride, but
a low etch rate for TEOS.
10. The structure can be further facilitated by using a silicide
technique to increase the conductivity of the interconnect areas of
the cells. Siliciding is a fabrication technique that enables
electrical interconnections to be made that have reduced resistance
and capacitance.
11. The silicide process comprises forming a layer of a refractory
metal silicide material such as tungsten, titanium, tantalum,
molybdenum, etc. on a silicon interconnect area (source or drain
diffusion region) or on a polysilicon gate to which ohmic contact
is to be made, and then reacting the silicide material with the
underlaying silicon material to form a silicide surface layer
having much lower resistance than heavily doped silicon or
polysilicon. A silicide surface layer formed on a polysilicon gate
is called "polycide", whereas a silicide surface layer formed on
silicon using a self-aligned process is called "salicide".
12. A problem which has remained unsolved in the fabrication of
flash EEPROM memories and other semiconductor device structures is
data retention. A flash EEPROM cell is programmed by creating a
negative charge (electrons) on the floating gate. The charge should
remain until it is deliberately removed by erasing the cell.
13. However, the charge on a conventional flash EEPROM cell which
is fabricated using a silicon nitride etch stop layer that is
conventionally formed at a temperature of approximately 350.degree.
C. has been found to decrease substantially with time. This problem
has remained unsolved in the art.
SUMMARY OF THE INVENTION
14. The present invention overcomes the drawbacks of the prior art
by overcoming the problem of unsatisfactory data retention in
semiconductor devices such as flash EEPROMs which include silicon
nitride etch stop layers.
15. In accordance with the present invention, a semiconductor
memory device such as a flash Electrically Erasable Programmable
Read-Only Memory (Flash EEPROM) includes a floating gate with high
data retention.
16. A tungsten damascene local interconnect structure includes a
silicon nitride etch stop layer which is formed using Plasma
Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at
least 480.degree. C. such that the etch stop layer has a very low
concentration of hydrogen ions.
17. The minimization of hydrogen ions, which constitute mobile
positive charge carriers, in the etch stop layer, minimizes
recombination of the hydrogen ions with electrons on the floating
gate, and thereby maximizes data retention of the device.
18. These and other features and advantages of the present
invention will be apparent to those skilled in the art from the
following detailed description, taken together with the
accompanying drawings, in which like reference numerals refer to
like parts.
DESCRIPTION OF THE DRAWINGS
19. FIGS. 1 to 10 are simplified sectional views illustrating steps
of a process for fabricating a semiconductor device according to
the present invention; and
20. FIG. 11 is a simplified diagram illustrating a Plasma Enhanced
Chemical Vapor Deposition (PECVD) apparatus for practicing the
present invention.
DETAILED DESCRIPTION OF THE INVENTION
21. The present inventors have discovered that a major cause of
poor data retention in semiconductor devices such as flash EEPROMs
as presented above is a high concentration of hydrogen ions in the
silicon nitride etch stop layers of the devices. These hydrogen
ions are highly mobile positive charge carriers which migrate to
the floating gates of memory cells to recombine with electrons
thereon and dissipate the charges on the floating gates.
22. The present invention overcomes these problems, and provides a
semiconductor structure including a silicon nitride layer having a
low concentration of hydrogen ions. Although the present invention
is especially suited to a memory device including a floating gate
in which data retention is a problem, the present invention is not
so limited, and can be advantageously applied to a large variety of
semiconductor devices which may or may not include floating gates
or other charge retention elements. For example, the invention may
be applied to semiconductor structures which include silicon
nitride encapsulation layers.
23. FIGS. 1 to 10 are simplified sectional diagrams illustrating a
process for fabricating a portion of a flash EEPROM semiconductor
memory device according to the present invention. The detailed
configuration of the device is not the particular subject matter of
the invention, and only those elements which are necessary for
understanding the invention will be described and illustrated.
24. As viewed in FIG. 1, a flash EEPROM memory 10 includes a
silicon semiconductor substrate 12. Two erasable memory cells 14
are formed on a surface 12a of the substrate 12, each including a
MOS transistor structure having a source 14a, drain 14b, gate oxide
layer 14c, and channel 14d underlying the gate oxide layer 14c. The
cells 14 are physically and electrically isolated from each other
by field oxide regions 16.
25. A polysilicon control gate 14e is formed over each gate oxide
layer 14c, and a polysilicon floating gate 14f is formed underneath
the control gate 14e in the gate oxide layer 14c.
26. Although the gate oxide layers 14c are shown as being integral,
they may comprise two or more sublayers. For example, portions of
the gate oxide layers 14c which underlie the floating gates 14f may
be separate tunnel oxide layers. Further shown in the drawing are
electrically insulating gate sidewall spacers 14g.
27. The construction and operation of the memory 10 are not the
particular subject matter of the invention and will not be
described in detail. Furthermore, the reference numerals
designating the individual elements of the memory cells will be
omitted in FIGS. 2 to 10 except as required for understanding the
invention to avoid cluttering of the drawings.
28. FIG. 1 illustrates the initial steps of the present process,
which consist of providing the substrate 12, and forming
semiconductor devices such as the erasable memory cells 14 on the
surface 12a of the substrate 12.
29. FIG. 2 shows how interconnect areas are formed for the elements
of the cells using a silicide technique to increase the electrical
conductivity. The process comprises forming a layer of a refractory
metal silicide material such as tungsten, titanium, tantalum,
molybdenum, etc. on the source, 14a, drain 14b, and control gate
14e to which ohmic contact is to be made, and then reacting the
silicide material with the underlaying silicon material to form
silicide source interconnect areas 18a, drain interconnect areas
18b, and control gate interconnect areas 18c respectively.
30. FIG. 3 illustrates how a silicon nitride (S.sub.3N.sub.4) etch
stop layer 20 is formed over the surface 12a of the substrate 12
and the devices 14 in accordance with the present invention. The
etch stop layer 20 is preferably formed using Plasma Enhanced
Chemical Vapor Deposition (PECVD) at a temperature of at least
approximately 480.degree. C. to a thickness of approximately
800.+-. 50 .ANG..
31. Basic Chemical Vapor Deposition (CVD) is a technique which
normally requires a substrate temperature of at least 600.degree.
C. to achieve epitaxial deposition of a silicon nitride layer.
PECVD improves on basic CVD by creating a glow discharge or plasma
in the reaction chamber which enables a silicon nitride layer to be
formed at a much lower temperature on the order of 350.degree. C.
to 400.degree. C.
32. Conventional silicon nitride etch stop layers are typically
formed at about 350.degree. C.-400.degree. C., and have high
concentrations of hydrogen ions which migrate to the floating gates
of EEPROM cells to recombine with electrons thereon and thereby
dissipate charge. This causes poor data retention as discussed
above.
33. The present step of forming the silicon nitride etch stop layer
20 at a higher temperature of at least approximately 480.degree. C.
results in a substantially lower concentration of hydrogen ions in
the layer 20 than in a conventional silicon nitride etch stop layer
which is formed at low temperature, thereby providing substantially
improved data retention.
34. A PECVD reaction chamber 22 for forming the silicon nitride
layer 20 is illustrated in FIG. 11, and includes a container 24. An
electrically grounded susceptor 26 is suspended in the container
24. A silicon wafer 30 including one or more dies on which
semiconductor structures such as the memories 10 as illustrated in
FIG. 2 are formed is supported on the susceptor 26. Lift pins 28
are provided for placing the wafer 30 on the susceptor 26. The
wafer 30 is heated to a temperature of approximately 470.degree. C.
to 550.degree. C., preferably 500.degree. C., by a heater 32.
35. A gas discharge nozzle which is known in the art as a shower
head 34 is mounted in the container 24 above the wafer 30. A gas
mixture 36 which is used to form the silicon nitride layer 20 is
fed into the shower head 34 through an inlet conduit 38 and
discharged downwardly toward the wafer 30 through orifices 34a. The
gas 36 preferably includes NH.sub.3, SiH.sub.4, and N.sub.2.
36. Radio Frequency (RF) power is applied to the shower head 34
through a power lead 40. A blocker plate 34b is provided at the
upper end of the shower head 34 to prevent gas from escaping
upwardly.
37. The RF power applied to the shower head 34 creates an
alternating electrical field between the shower head 34 and the
grounded susceptor 26 which forms a glow or plasma discharge in the
gas 36 therebetween. The plasma discharge enables the silicon
nitride layer 20 to be formed at the temperature specified
above.
38. In addition to a deposition temperature of at least
approximately 480.degree. C., other process conditions enhance the
formation of a silicon nitride layer 20 with low hydrogen
concentration. The present inventors have discovered that the
qualities of the silicon nitride layer 20 are improved if the layer
has relatively high density and is formed at a relatively low
deposition rate.
39. This is achieved by performing deposition with low flow rates
of NH.sub.3 and SiH.sub.4 in the gas 36, and low RF power.
Preferred values for these conditions are an SiH.sub.4 flow rate of
approximately 55.+-. 5 sccm, an NH.sub.3 flow rate of approximately
12.+-. 2 sccm, and an RF power of approximately 375.+-. 10
watts.
40. The preferred conditions also include an N.sub.2 flow rate of
approximately 4,000 sccm, a pressure of 3.5.+-. 0.2 torr, and a
spacing S of approximately 375 mils (9.5 millimeters) between the
shower head 34 and the surface of the wafer 30.
41. Referring now to FIG. 4, the next step of the process is to
form an insulator layer 42', preferably of tetraethylorthosilicate
(TEOS) glass, over the silicon nitride etch stop layer 20. The TEOS
layer 42' is planarized as illustrated in FIG. 5 using, preferably,
chemical-mechanical polishing, and redesignated as 42.
42. The remaining steps result in the formation of a tungsten
damascene local interconnect structure for the memory 10. In FIG.
6, a layer of photoresist 44 is formed on the TEOS layer 42, and
patterned using photolithography such that holes 44a, 44b and 44c
are formed above the silicide interconnect areas 18a, 18b and 18c
respectively.
43. In FIGS. 7 and 8, holes are etched through the TEOS layer 42
and silicon nitride layer 20 down to the interconnect areas 18a,
18b and 18c, preferably using a two stage Reactive Ion Etching
(RIE) process.
44. In FIG. 7, an RIE etch is performed using octafluorobutene
(C.sub.4F.sub.8) which has a selectively high etch rate for TEOS
and a low etch rate for silicon nitride. This results in the
formation of vertical holes 46a, 46b and 46c which extend
downwardly from the holes 44a, 44b and 44c of the photoresist layer
44 through the TEOS layer 42 and stop on the silicon nitride etch
stop layer 20 in alignment with the interconnect areas 18a, 18b and
18c respectively.
45. In FIG. 8, the photoresist layer 44 is stripped away, and a
second RIE etch is performed using fluoromethane (CH.sub.3F), which
has a selectively high etch rate for silicon nitride and a low etch
rate for TEOS. This results in the formation of holes 48a, 48b and
48c through the silicon nitride layer 20. The holes 48a, 48b and
48c are extensions of the holes 46a, 46b and 46c through the TEOS
layer 42, and terminate at the interconnect areas 18a, 18b and 18c
respectively.
46. In FIG. 9, tungsten 50 is deposited over the structure of FIG.
8. The tungsten fills the holes through the TEOS layer 42 and the
silicon nitride layer 20 as indicated at 50a', 50b' and 50c', and
ohmically contacts the interconnect areas 18a, 18b and 18c
respectively. The tungsten further forms on the top of the TEOS
layer 42 as indicated at 50d.
47. In FIG. 10, the top of the structure is planarized, preferably
using chemical-mechanical polishing, to remove the tungsten 50d
from the TEOS layer 42. The result is independent local
interconnects 50a, 50b and 50c which are formed of tungsten inlaid
in the TEOS layer 42 and the silicon nitride layer 20. The local
interconnects 50a, 50b and 50c enable the sources 14a, drains 14b,
and control gates 14e respectively of the transistors 14 to be
electrically accessed from the upper surface of the structure.
48. In summary, the present invention overcomes the drawbacks of
the prior art and provides a semiconductor structure including a
silicon nitride layer etch stop layer with substantially improved
data retention characteristics.
49. Various modifications will become possible for those skilled in
the art after receiving the teachings of the present disclosure
without departing from the scope thereof.
* * * * *