| Patent | Date |
|---|
Methods for configuring FPGA ' S having viriable grain components for providing time-shared access to interconnect resources
App 20020196809 - Agrawal, Om P. ; et al. | 2002-12-26 |
Variable grain architecture for FPGA integrated circuits
App 20020186044 - Agrawal, Om P. ; et al. | 2002-12-12 |
Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress
Grant 6,455,912 - Kim , et al. September 24, 2 | 2002-09-24 |
Variable grain architecture for FPGA integrated circuits
Grant 6,380,759 - Agrawal , et al. April 30, 2 | 2002-04-30 |
Circuitry to provide fast carry
Grant 6,359,466 - Sharpe-Geisler March 19, 2 | 2002-03-19 |
Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources
App 20010056570 - Agrawal, Om P. ; et al. | 2001-12-27 |
Inversion of product term line before or logic in a programmable logic device (PLD)
Grant 6,326,808 - Fisk , et al. December 4, 2 | 2001-12-04 |
Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress
Grant 6,297,128 - Kim , et al. October 2, 2 | 2001-10-02 |
Two transistor EEPROM cell
Grant 6,294,811 - Fong , et al. September 25, 2 | 2001-09-25 |
EEPROM cell with tunneling at separate edge and channel regions
Grant 6,294,810 - Li , et al. September 25, 2 | 2001-09-25 |
Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
Grant 6,284,626 - Kim September 4, 2 | 2001-09-04 |
Semiconductor - oxide - semiconductor capacitor formed in intergtated circuit
App 20010015449 - Niguyen, Bai ; et al. | 2001-08-23 |
Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits
Grant 6,275,064 - Agrawal , et al. August 14, 2 | 2001-08-14 |
Triple-well EEPROM cell using P-well for tunneling across a channel
Grant 6,274,898 - Mehta , et al. August 14, 2 | 2001-08-14 |
Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect
Grant 6,261,944 - Mehta , et al. July 17, 2 | 2001-07-17 |
Process for fabricating a high-endurance non-volatile memory device
Grant 6,255,169 - Li , et al. July 3, 2 | 2001-07-03 |
Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources
Grant 6,249,144 - Agrawal , et al. June 19, 2 | 2001-06-19 |
Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration
App 20010001075 - Ngo, Minh Van ; et al. | 2001-05-10 |
FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks
Grant 6,216,257 - Agrawal , et al. April 10, 2 | 2001-04-10 |
Method of forming a non-volatile memory device
Grant 6,214,666 - Mehta April 10, 2 | 2001-04-10 |
FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections
Grant 6,211,695 - Agrawal , et al. April 3, 2 | 2001-04-03 |
Enhanced I/O control flexibility for generating control signals
Grant 6,191,612 - Agrawal , et al. February 20, 2 | 2001-02-20 |
Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration
Grant 6,190,966 - Ngo , et al. February 20, 2 | 2001-02-20 |
FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals
Grant 6,181,163 - Agrawal , et al. January 30, 2 | 2001-01-30 |
Operational amplifier with CMOS transistors made using 2.5 volt process transistors
Grant 6,175,266 - Sharpe-Geisler January 16, 2 | 2001-01-16 |
Boron doped silicon capacitor plate
Grant 6,172,392 - Schmidt , et al. January 9, 2 | 2001-01-09 |
High voltage switch for providing voltages higher than 2.5 volts with transistors made using a 2.5 volt process
Grant 6,169,432 - Sharpe-Geisler January 2, 2 | 2001-01-02 |
Efficient interconnect network for use in FPGA device having variable grain architecture
Grant 6,163,168 - Nguyen , et al. December 19, 2 | 2000-12-19 |
High voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process device
Grant 6,163,175 - Sharpe-Geisler December 19, 2 | 2000-12-19 |
Tileable and compact layout for super variable grain blocks within FPGA device
Grant 6,154,051 - Nguyen , et al. November 28, 2 | 2000-11-28 |
Fabrication of oxide regions having multiple thicknesses using minimized number of thermal cycles
Grant 6,133,164 - Kim October 17, 2 | 2000-10-17 |
Phase locked loop with a lock detector
Grant 6,133,769 - Fontana , et al. October 17, 2 | 2000-10-17 |
Dual port SRAM memory for run time use in FPGA integrated circuits
Grant 6,127,843 - Agrawal , et al. October 3, 2 | 2000-10-03 |
Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)
Grant 6,128,770 - Agrawal , et al. October 3, 2 | 2000-10-03 |
Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources
Grant 6,124,730 - Agrawal , et al. September 26, 2 | 2000-09-26 |
Programmable control multiplexing for input/output blocks (IOBs) in FPGA integrated circuits
Grant 6,107,823 - Agrawal , et al. August 22, 2 | 2000-08-22 |
Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's
Grant 6,102,963 - Agrawal August 15, 2 | 2000-08-15 |
Methods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resources
Grant 6,100,715 - Agrawal , et al. August 8, 2 | 2000-08-08 |
Electrostatic discharge (ESD) protection for NMOS pull up transistors of a 5.0 volt compatible output buffer using 2.5 volt process transistors
Grant 6,091,595 - Sharpe-Geisler July 18, 2 | 2000-07-18 |
Method for sorting semiconductor devices having a plurality of non-volatile memory cells
Grant 6,075,724 - Li , et al. June 13, 2 | 2000-06-13 |
Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide
Grant 6,064,105 - Li , et al. May 16, 2 | 2000-05-16 |
Non-volatile memory cell having dual avalanche injection elements
Grant 6,034,893 - Mehta March 7, 2 | 2000-03-07 |
Band gap reference using a low voltage power supply
Grant 6,031,365 - Sharpe-Geisler February 29, 2 | 2000-02-29 |
Electrostatic discharge (ESD) protection for a 5.0 volt compatible input/output (I/O) in a 2.5 volt semiconductor process
Grant 6,028,758 - Sharpe-Geisler February 22, 2 | 2000-02-22 |
Zero-power CMOS non-volatile memory cell having an avalanche injection element
Grant 6,028,789 - Mehta , et al. February 22, 2 | 2000-02-22 |
Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuits
Grant 5,990,702 - Agrawal , et al. November 23, 1 | 1999-11-23 |
Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits
Grant 5,982,193 - Agrawal , et al. November 9, 1 | 1999-11-09 |
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