| Patent | Date |
|---|
Digital Current Measurement For In-situ Device Monitoring
App 20190107569 - Kidd; David ; et al. | 2019-04-11 |
Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates
Grant 9,123,570 - Pinto , et al. September 1, 2 | 2015-09-01 |
Integrated circuits with aligned (100) NMOS and (110) PMOS finFET sidewall channels
Grant 9,053,966 - Xiong , et al. June 9, 2 | 2015-06-09 |
Integrated Circuits With Aligned (100) Nmos And (110) Pmos Finfet Sidewall Channels
App 20150014789 - Xiong; Weize W. ; et al. | 2015-01-15 |
Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels
Grant 8,872,220 - Xiong , et al. October 28, 2 | 2014-10-28 |
Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology
Grant 8,846,487 - Pinto , et al. September 30, 2 | 2014-09-30 |
Advanced CMOS using super steep retrograde wells
Grant 8,703,568 - Babcock , et al. April 22, 2 | 2014-04-22 |
Integrated Circuits With Aligned (100) Nmos And (110) Pmos Finfet Sidewall Channels
App 20140035057 - Xiong; Weize W. ; et al. | 2014-02-06 |
Integration Scheme For Changing Crystal Orientation In Hybrid Orientation Technology (hot) Using Direct Silicon Bonded (dsb) Substrates
App 20130292780 - PINTO; Angelo ; et al. | 2013-11-07 |
Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates
Grant 8,558,318 - Pinto , et al. October 15, 2 | 2013-10-15 |
Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels
Grant 8,410,519 - Xiong , et al. April 2, 2 | 2013-04-02 |
Reduction Of Sti Corner Defects During Spe In Semiconductor Device Fabrication Using Dsb Substrate And Hot Technology
App 20130029471 - Pinto; Angelo ; et al. | 2013-01-31 |
Circuit And Method For Testing Insulating Material
App 20120212245 - Pinto; Angelo ; et al. | 2012-08-23 |
Control of dopant diffusion from buried layers in bipolar integrated circuits
Grant 8,247,300 - Babcock , et al. August 21, 2 | 2012-08-21 |
Integrated Circuits With Aligned (100) Nmos And (110) Pmos Finfet Sidewall Channels
App 20120175710 - Xiong; Weize ; et al. | 2012-07-12 |
Advanced Cmos Using Super Steep Retrograde Wells
App 20120164802 - Babcock; Jeffrey A. ; et al. | 2012-06-28 |
Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels
Grant 8,138,035 - Xiong , et al. March 20, 2 | 2012-03-20 |
Advanced CMOS using super steep retrograde wells
Grant 8,129,246 - Babcock , et al. March 6, 2 | 2012-03-06 |
Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate
Grant 8,043,947 - Pinto , et al. October 25, 2 | 2011-10-25 |
Integration Scheme For Reducing Border Region Morphology In Hybrid Orientation Technology (hot) Using Direct Silicon Bonded (dsb) Substrates
App 20110180881 - Pinto; Angelo ; et al. | 2011-07-28 |
Method For Forming Integrated Circuits With Aligned (100) Nmos And (110) Pmos Finfet Sidewall Channels
App 20110151651 - Xiong; Weize ; et al. | 2011-06-23 |
Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow
Grant 7,943,479 - Pinto , et al. May 17, 2 | 2011-05-17 |
Integration scheme for reducing border region morphology in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates
Grant 7,943,451 - Pinto , et al. May 17, 2 | 2011-05-17 |
Integration Scheme For Changing Crystal Orientation In Hybrid Orientation Technology (hot) Using Direct Silicon Bonded (dsb) Substrates
App 20110108893 - Pinto; Angelo ; et al. | 2011-05-12 |
Advanced Cmos Using Super Steep Retrograde Wells
App 20110111553 - Babcock; Jeffrey A. ; et al. | 2011-05-12 |
Use of in-situ HCL etch to eliminate by oxidation recrystallization border defects generated during solid phase epitaxy (SPE) in the fabrication of nano-scale CMOS transistors using direct silicon bond substrate (DSB) and hybrid orientation technology (HOT)
Grant 7,897,447 - Pinto March 1, 2 | 2011-03-01 |
Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate
Grant 7,897,994 - Xiong , et al. March 1, 2 | 2011-03-01 |
Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates
Grant 7,892,908 - Pinto , et al. February 22, 2 | 2011-02-22 |
Advanced CMOS using super steep retrograde wells
Grant 7,883,977 - Babcock , et al. February 8, 2 | 2011-02-08 |
Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates
Grant 7,855,111 - Bu , et al. December 21, 2 | 2010-12-21 |
Reduction Of Sti Corner Defects During Spe In Semicondcutor Device Fabrication Using Dsb Substrate And Hot Technology
App 20100304547 - Pinto; Angelo ; et al. | 2010-12-02 |
Control Of Dopant Diffusion From Buried Layers In Bipolar Integrated Circuits
App 20100279481 - Babcock; Jeffrey A. ; et al. | 2010-11-04 |
Use Of In-situ Hcl Etch To Eliminate By Oxidation Recrystallization Border Defects Generated During Solid Phase Epitaxy (spe) In The Fabrication Of Nano-scale Cmos Transistors Using Direct Silicon Bond Substrate (dsb) And Hybrid Orientation Technology (hot)
App 20100216286 - Pinto; Angelo | 2010-08-26 |
Semiconductor device made by the method of producing hybrid orientnation (100) strained silicon with (110) silicon
Grant 7,767,510 - Wise , et al. August 3, 2 | 2010-08-03 |
Integration Of High-k Metal-gate Stack Into Direct Silicon Bonding (dsb) Hybrid Orientation Technology (hot) Pmos Process Flow
App 20100047993 - Pinto; Angelo ; et al. | 2010-02-25 |
Border Region Defect Reduction In Hybrid Orientation Technology (hot) Direct Silicon Bonded (dsb) Substrates
App 20100032727 - Bu; Haowen ; et al. | 2010-02-11 |
Advanced CMOS using super steep retrograde wells
Grant 7,655,523 - Babcock , et al. February 2, 2 | 2010-02-02 |
Method to improve performance of secondary active components in an esige CMOS technology
Grant 7,642,197 - Chidambaram , et al. January 5, 2 | 2010-01-05 |
Integration Scheme For Changing Crystal Orientation In Hybrid Orientation Technology (hot) Using Direct Silicon Bonded (dsb) Substrates
App 20090159933 - Pinto; Angelo ; et al. | 2009-06-25 |
Integration Scheme For Reducing Border Region Morpphology In Hybrid Orientation Technology (hot) Using Direct Silicon Bonded (dsb) Substrates
App 20090159932 - Pinto; Angelo ; et al. | 2009-06-25 |
Advanced Cmos Using Super Steep Retrograde Wells
App 20090130805 - Babcock; Jeffrey A. ; et al. | 2009-05-21 |
Method To Eliminate Re-crystallization Border Defects Generated During Solid Phase Epitaxy Of A Dsb Substrate
App 20090130817 - Pinto; Angelo ; et al. | 2009-05-21 |
Advanced CMOS using super steep retrograde wells
Grant 7,501,324 - Babcock , et al. March 10, 2 | 2009-03-10 |
Method To Reduce Residual Sti Corner Defects Generated During Spe In The Fabrication Of Nano-scale Cmos Transistors Using Dsb Substrate And Hot Technology
App 20090057816 - Pinto; Angelo ; et al. | 2009-03-05 |
Method To Improve Performance Of Secondary Active Components In An Esige Cmos Technology
App 20090014805 - Chidambaram; Periannan ; et al. | 2009-01-15 |
Method Of Making (100) Nmos And (110) Pmos Sidewall Surface On The Same Fin Orientation For Multiple Gate Mosfet With Dsb Substrate
App 20080308847 - XIONG; Weize ; et al. | 2008-12-18 |
Semiconductor Device Made by the Method of Producing Hybrid Orientnation (100) Strained Silicon with (110) Silicon
App 20080303027 - Wise; Rick L. ; et al. | 2008-12-11 |
On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits
Grant 7,422,972 - Babcock , et al. September 9, 2 | 2008-09-09 |
Advanced CMOS Using Super Steep Retrograde Wells
App 20080132012 - Babcock; Jeffrey A. ; et al. | 2008-06-05 |
Semiconductor Device Manufactured Using Passivation of Crystal Domain Interfaces in Hybrid Orientation Technology
App 20080128821 - Pinto; Angelo ; et al. | 2008-06-05 |
Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer
Grant 7,217,322 - Babcock , et al. May 15, 2 | 2007-05-15 |
Advanced CMOS using super steep retrograde wells
Grant 7,199,430 - Babcock , et al. April 3, 2 | 2007-04-03 |
Structure of semiconductor device with sinker contact region
Grant 7,164,186 - Pinto , et al. January 16, 2 | 2007-01-16 |
Advanced CMOS using Super Steep Retrograde Wells
App 20060197158 - Babcock; Jeffrey A. ; et al. | 2006-09-07 |
Advanced CMOS using super steep retrograde wells
App 20060175657 - Babcock; Jeffrey A. ; et al. | 2006-08-10 |
Advanced CMOS using super steep retrograde wells
Grant 7,064,399 - Babcock , et al. June 20, 2 | 2006-06-20 |
On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits
App 20050258990 - Babcock, Jeffrey A. ; et al. | 2005-11-24 |
Control of dopant diffusion from buried layers in bipolar integrated circuits
App 20050250289 - Babcock, Jeffrey A. ; et al. | 2005-11-10 |
On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits
Grant 6,958,523 - Babcock , et al. October 25, 2 | 2005-10-25 |
Lateral heterojunction bipolar transistor
Grant 6,927,428 - Babcock , et al. August 9, 2 | 2005-08-09 |
Method for constructing a metal oxide semiconductor field effect transistor
Grant 6,905,932 - Howard , et al. June 14, 2 | 2005-06-14 |
Bipolar junction transistor with a counterdoped collector region
Grant 6,894,366 - Howard , et al. May 17, 2 | 2005-05-17 |
Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer
App 20050098093 - Babcock, Jeffrey A. ; et al. | 2005-05-12 |
Method for manufacturing a bipolar junction transistor
Grant 6,887,765 - Howard , et al. May 3, 2 | 2005-05-03 |
Method for manufacturing and structure of semiconductor device with sinker contact region
App 20050037588 - Pinto, Angelo ; et al. | 2005-02-17 |
Integrated process for high voltage and high performance silicon-on-insulator bipolar devices
Grant 6,838,348 - Babcock , et al. January 4, 2 | 2005-01-04 |
Integrated process for high voltage and high performance silicon-on-insulator bipolar devices
App 20040207046 - Babcock, Jeffrey A. ; et al. | 2004-10-21 |
Method for manufacturing and structure of semiconductor device with shallow trench collector contact region
App 20040209433 - Babcock, Jeffrey A. ; et al. | 2004-10-21 |
Method for manufacturing a semiconductor device with sinker contact region
Grant 6,806,159 - Pinto , et al. October 19, 2 | 2004-10-19 |
Lateral heterojunction bipolar transistor
App 20040188802 - Babcock, Jeffrey A. ; et al. | 2004-09-30 |
Lateral heterojunction bipolar transistor
Grant 6,794,237 - Babcock , et al. September 21, 2 | 2004-09-21 |
Semiconductor device with a collector contact in a depressed well-region
Grant 6,774,455 - Babcock , et al. August 10, 2 | 2004-08-10 |
Integrated process for high voltage and high performance silicon-on-insulator bipolar devices
Grant 6,770,952 - Babcock , et al. August 3, 2 | 2004-08-03 |
Method for constructing a metal oxide semiconductor field effect transistor
App 20040106270 - Howard, Gregory E. ; et al. | 2004-06-03 |
Method for manufacturing a bipolar junction transistor
Grant 6,734,073 - Howard , et al. May 11, 2 | 2004-05-11 |
Method for constructing a metal oxide semiconductor field effect transistor
Grant 6,680,504 - Howard , et al. January 20, 2 | 2004-01-20 |
Germanium implanted HBT bipolar
App 20040004270 - Lombardo, Salvatore ; et al. | 2004-01-08 |
Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device
Grant 6,667,226 - Pinto , et al. December 23, 2 | 2003-12-23 |
P-i-n transit time silicon-on-insulator device
Grant 6,660,616 - Babcock , et al. December 9, 2 | 2003-12-09 |
PNP lateral bipolar electronic device and corresponding manufacturing process
Grant 6,657,279 - Pinto , et al. December 2, 2 | 2003-12-02 |
Zero mask high density metal/insulator/metal capacitor
Grant 6,646,323 - Dirnecker , et al. November 11, 2 | 2003-11-11 |
Manufacturing process of a germanium implanted HBT bipolar transistor
Grant 6,624,017 - Lombardo , et al. September 23, 2 | 2003-09-23 |
Lateral heterojunction bipolar transistor
App 20030122154 - Babcock, Jeffrey A. ; et al. | 2003-07-03 |
Control of dopant diffusion from buried layers in bipolar integrated circuits
App 20030082882 - Babcock, Jeffrey A. ; et al. | 2003-05-01 |
Control of dopant diffusion from polysilicon emitters in bipolar integrated circuits
App 20030080394 - Babcock, Jeffrey A. ; et al. | 2003-05-01 |
Method for manufacturing and structure of semiconductor device with sinker contact region
App 20030062598 - Pinto, Angelo ; et al. | 2003-04-03 |
Method for manufacturing and structure of semiconductor device with shallow trench collector contact region
App 20030062589 - Babcock, Jeffrey A. ; et al. | 2003-04-03 |
Zero mask high density metal/insulator/metal capacitor
App 20020163029 - Dirnecker, Christoph ; et al. | 2002-11-07 |
Integrated process for high voltage and high performance silicon-on-insulator bipolar devices
App 20020160562 - Babcock, Jeffrey A. ; et al. | 2002-10-31 |
P-i-n transit time silicon-on-insulator device
App 20020100950 - Babcock, Jeffrey A. ; et al. | 2002-08-01 |
Method for constructing a metal oxide semiconductor field effect transistor
App 20020081792 - Howard, Gregory E. ; et al. | 2002-06-27 |
Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device
App 20020081809 - Pinto, Angelo ; et al. | 2002-06-27 |
Method for manufacturing a bipolar junction transistor
App 20020076893 - Howard, Gregory E. ; et al. | 2002-06-20 |
Method for manufacturing a bipolar junction transistor
App 20020076892 - Howard, Gregory E. ; et al. | 2002-06-20 |
Programmable neuron MOSFET on SOI
Grant 6,407,425 - Babcock , et al. June 18, 2 | 2002-06-18 |
Method of manufacturing a zero mask high density metal/insulator/metal capacitor
Grant 6,391,707 - Dirnecker , et al. May 21, 2 | 2002-05-21 |
Programmable neuron MOSFET on SOI
App 20020047155 - Babcock, Jeffrey A. ; et al. | 2002-04-25 |
Bipolar junction transistor
App 20020041008 - Howard, Gregory E. ; et al. | 2002-04-11 |
Method of manufacturing a vertical-channel MOSFET
Grant 6,362,025 - Patti , et al. March 26, 2 | 2002-03-26 |
On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits
App 20020033519 - Babcock, Jeffrey A. ; et al. | 2002-03-21 |
Advanced CMOS using super steep retrograde wells
App 20020033511 - Babcock, Jeffrey A. ; et al. | 2002-03-21 |
RF voltage controlled capacitor on thick-film SOI
App 20020008268 - Babcock, Jeffrey A. ; et al. | 2002-01-24 |
Method and apparatus for the selective doping of semiconductor material by ion implantation
Grant 6,284,615 - Pinto , et al. September 4, 2 | 2001-09-04 |
PNP lateral bipolar electronic device
App 20010000413 - Pinto, Angelo ; et al. | 2001-04-26 |
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