loadpatents
name:-0.06326699256897
name:-0.050519943237305
name:-0.028010129928589
Pan; Shing-Chyang Patent Filings

Pan; Shing-Chyang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pan; Shing-Chyang.The latest application filed is for "etch stop layer for semiconductor devices".

Company Profile
27.43.55
  • Pan; Shing-Chyang - Hsinchu County TW
  • Pan; Shing-Chyang - Jhudong Township TW
  • Pan; Shing-Chyang - Hsinchu City TW
  • Pan; Shing-Chyang - Hsinchu TW
  • Pan; Shing-Chyang - Hsinchu County 310 TW
  • Pan; Shing-Chyang - Jhudong TW
  • Pan; Shing-Chyang - Hsin-Chu TW
  • Pan; Shing-Chyang - Tainan TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Etch Stop Layer for Semiconductor Devices
App 20220254680 - Tung; Szu-Ping ;   et al.
2022-08-11
Etch stop layer for semiconductor devices
Grant 11,322,396 - Tung , et al. May 3, 2
2022-05-03
Structure For Microelectromechanical Systems (mems) Devices To Control Pressure At High Temperature
App 20220089434 - Wang; Yi-Ren ;   et al.
2022-03-24
Structure for microelectromechanical systems (MEMS) devices to control pressure at high temperature
Grant 11,198,606 - Wang , et al. December 14, 2
2021-12-14
Microelectromechanical Systems Device Having A Mechanically Robust Anti-stiction/outgassing Structure
App 20210309508 - Chang; Kuei-Sung ;   et al.
2021-10-07
Diffusion Barrier Layer In Programmable Metallization Cell
App 20210280780 - Zhong; Albert ;   et al.
2021-09-09
Metal-Based Etch-Stop Layer
App 20210280460 - Tung; Szu-Ping ;   et al.
2021-09-09
Multi-patterning to form vias with straight profiles
Grant 11,049,763 - Chen , et al. June 29, 2
2021-06-29
Microelectromechanical systems device having a mechanically robust anti-stiction/outgassing structure
Grant 11,040,870 - Chang , et al. June 22, 2
2021-06-22
Metal-based etch-stop layer
Grant 11,004,734 - Tung , et al. May 11, 2
2021-05-11
Patterning Methods for Semiconductor Devices
App 20210134656 - Wang; Wei-Ren ;   et al.
2021-05-06
Memory Device And Method For Fabricating The Same
App 20210119120 - WU; Jung-Tang ;   et al.
2021-04-22
Morphology of resist mask prior to etching
Grant 10,978,301 - Chang , et al. April 13, 2
2021-04-13
Structure For Microelectromechanical Systems (mems) Devices To Control Pressure At High Temperature
App 20210087055 - Wang; Yi-Ren ;   et al.
2021-03-25
Microelectromechanical Systems Device Having A Mechanically Robust Anti-stiction/outgassing Structure
App 20210024348 - Chang; Kuei-Sung ;   et al.
2021-01-28
Patterning methods for semiconductor devices
Grant 10,867,839 - Wang , et al. December 15, 2
2020-12-15
Memory device
Grant 10,862,026 - Wu , et al. December 8, 2
2020-12-08
Physical Vapor Deposition Chamber With Target Surface Morphology Monitor
App 20200377997 - Trinh; Hai-Dang ;   et al.
2020-12-03
Method for Manufacturing a Semiconductor Device
App 20200357634 - Tsai; Wan-Lin ;   et al.
2020-11-12
Method for forming semiconductor device structure with etch stop layer
Grant 10,811,263 - Lee , et al. October 20, 2
2020-10-20
Etch Stop Layer for Semiconductor Devices
App 20200279770 - Tung; Szu-Ping ;   et al.
2020-09-03
Method for manufacturing a semiconductor device
Grant 10,727,045 - Tsai , et al.
2020-07-28
Etch stop layer for semiconductor devices
Grant 10,685,873 - Tung , et al.
2020-06-16
Memory Device
App 20200152864 - WU; Jung-Tang ;   et al.
2020-05-14
Method For Forming Semiconductor Device Structure With Etch Stop Layer
App 20200144063 - LEE; Ya-Ling ;   et al.
2020-05-07
Multi-Patterning to Form Vias with Straight Profiles
App 20200090984 - Chen; Chun-Kai ;   et al.
2020-03-19
Morphology of Resist Mask Prior to Etching
App 20200075319 - Chang; Ching-Yu ;   et al.
2020-03-05
Metal-Based Etch-Stop Layer
App 20200066581 - Tung; Szu-Ping ;   et al.
2020-02-27
Via structure, MRAM device using the via structure and method for fabricating the MRAM device
Grant 10,535,816 - Wu , et al. Ja
2020-01-14
Method for forming semiconductor device structure with etch stop layer
Grant 10,522,360 - Lee , et al. Dec
2019-12-31
Systems and methods for integrated resputtering in a physical vapor deposition chamber
Grant 10,515,788 - Pan , et al. Dec
2019-12-24
Patterning Methods for Semiconductor Devices
App 20190385902 - Wang; Wei-Ren ;   et al.
2019-12-19
Multi-patterning to form vias with straight profiles
Grant 10,510,585 - Chen , et al. Dec
2019-12-17
Metal-based etch-stop layer
Grant 10,468,297 - Tung , et al. No
2019-11-05
Metal-Based Etch-Stop Layer
App 20190333807 - Tung; Szu-Ping ;   et al.
2019-10-31
High aspect ratio gap fill
Grant 10,361,112 - Tsai , et al.
2019-07-23
Forming interconnect structure using plasma treated metal hard mask
Grant 10,312,107 - Ko , et al.
2019-06-04
Via Structure, Mram Device Using The Via Structure And Method For Fabricating The Mram Device
App 20190157548 - WU; Jung-Tang ;   et al.
2019-05-23
Method for Manufacturing a Semiconductor Device
App 20190103272 - Tsai; Wan-Lin ;   et al.
2019-04-04
High Aspect Ratio Gap Fill
App 20190006227 - TSAI; Wan-Lin ;   et al.
2019-01-03
Etch Stop Layer for Semiconductor Devices
App 20180350666 - Tung; Szu-Ping ;   et al.
2018-12-06
Method For Forming Semiconductor Device Structure With Etch Stop Layer
App 20180166285 - LEE; Ya-Ling ;   et al.
2018-06-14
Systems and Methods for Integrated Resputtering in a Physical Vapor Deposition Chamber
App 20180158658 - Pan; Shing-Chyang ;   et al.
2018-06-07
Systems and methods for integrated resputtering in a physical vapor deposition chamber
Grant 9,887,072 - Pan , et al. February 6, 2
2018-02-06
Multi-Patterning to Form Vias with Straight Profiles
App 20180033685 - Chen; Chun-Kai ;   et al.
2018-02-01
Etch Stop Layer for Semiconductor Devices
App 20180005876 - Tung; Szu-Ping ;   et al.
2018-01-04
Manufacturing method of semiconductor device
Grant 9,818,638 - Peng , et al. November 14, 2
2017-11-14
Multi-patterning to form vias with straight profiles
Grant 9,679,804 - Chen , et al. June 13, 2
2017-06-13
Manufacturing method of semiconductor device
Grant 9,659,811 - Peng , et al. May 23, 2
2017-05-23
Plasma apparatus, magnetic-field controlling method, and semiconductor manufacturing method
Grant 9,567,668 - Chi , et al. February 14, 2
2017-02-14
Semiconductor structure with inlaid capping layer and method of manufacturing the same
Grant 9,472,449 - Chen , et al. October 18, 2
2016-10-18
Bi-layer hard mask for robust metallization profile
Grant 9,385,086 - Pan , et al. July 5, 2
2016-07-05
Surface pre-treatment for hard mask fabrication
Grant 9,330,915 - Pan , et al. May 3, 2
2016-05-03
Plasma Apparatus, Magnetic-field Controlling Method, And Semiconductor Manufacturing Method
App 20150235823 - CHI; Chih-Chien ;   et al.
2015-08-20
Systems and Methods for Integrated Resputtering in a Physical Vapor Deposition Chamber
App 20150206724 - Pan; Shing-Chyang ;   et al.
2015-07-23
Semiconductor Structure With Inlaid Capping Layer And Method Of Manufacturing The Same
App 20150200126 - Chen; Kuan-Chia ;   et al.
2015-07-16
Bi-layer Hard Mask For Robust Metallization Profile
App 20150162282 - Pan; Shing-Chyang ;   et al.
2015-06-11
Surface Pre-Treatment for Hard Mask Fabrication
App 20150162280 - Pan; Shing-Chyang ;   et al.
2015-06-11
Semiconductor Device and Method for Forming the Same
App 20130062774 - Ko; Chung-Chi ;   et al.
2013-03-14
Barrier layer for copper interconnect
Grant 8,361,900 - Pan , et al. January 29, 2
2013-01-29
In situ Cu seed layer formation for improving sidewall coverage
Grant 8,252,690 - Su , et al. August 28, 2
2012-08-28
Barrier Layer For Copper Interconnect
App 20110256715 - PAN; Shing-Chyang ;   et al.
2011-10-20
Method for forming composite barrier layer
Grant 8,034,709 - Huang , et al. October 11, 2
2011-10-11
Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers
Grant RE41,935 - Pan , et al. November 16, 2
2010-11-16
System and method for film stress and curvature gradient mapping for screening problematic wafers
Grant 7,805,258 - Fu , et al. September 28, 2
2010-09-28
Multi-step Cu seed layer formation for improving sidewall coverage
Grant 7,704,886 - Su , et al. April 27, 2
2010-04-27
In Situ Cu Seed Layer Formation for Improving Sidewall Coverage
App 20090209106 - Su; Li-Lin ;   et al.
2009-08-20
Multi-Step Cu Seed Layer Formation for Improving Sidewall Coverage
App 20090209098 - Su; Li-Lin ;   et al.
2009-08-20
Method for forming composite barrier layer
App 20090047780 - Huang; Cheng-Lin ;   et al.
2009-02-19
Composite barrier layer
Grant 7,453,149 - Huang , et al. November 18, 2
2008-11-18
System and method for film stress and curvature gradient mapping for screening problematic wafers
App 20080199978 - Fu; Hsueh-Hung ;   et al.
2008-08-21
Method and apparatus for fabricating metal layer
App 20070181434 - Lee; Hsien-Ming ;   et al.
2007-08-09
High performance metallization cap layer
Grant 7,253,501 - Lee , et al. August 7, 2
2007-08-07
Method of avoiding plasma arcing during RIE etching
Grant 7,247,252 - Pan , et al. July 24, 2
2007-07-24
Method and apparatus for fabricating metal layer
Grant 7,226,860 - Lee , et al. June 5, 2
2007-06-05
Barrier structure for semiconductor devices
Grant 7,193,327 - Yu , et al. March 20, 2
2007-03-20
Oblique Recess For Interconnecting Conductors In A Semiconductor Device
App 20060244151 - YU; CHEN-HUA ;   et al.
2006-11-02
Barrier structure for semiconductor devices
App 20060163746 - Yu; Chen-Hua ;   et al.
2006-07-27
Method for simultaneous degas and baking in copper damascene process
Grant 7,030,023 - Pan , et al. April 18, 2
2006-04-18
High performance metallization cap layer
App 20060027922 - Lee; Hsien-Ming ;   et al.
2006-02-09
Composite barrier layer
App 20060027925 - Huang; Cheng-Lin ;   et al.
2006-02-09
Diffusion barrier for damascene structures
App 20050263891 - Lee, Bih-Huey ;   et al.
2005-12-01
Method and apparatus for fabricating metal layer
App 20050245072 - Lee, Hsien-Ming ;   et al.
2005-11-03
Pre-clean chamber with wafer heating apparatus and method of use
App 20050189075 - Pan, Shing-Chyang ;   et al.
2005-09-01
Refractory metal nitride barrier layer with gradient nitrogen concentration
App 20050156316 - Lee, Hsien-Ming ;   et al.
2005-07-21
Loadlock
App 20050097769 - Lin, Jing-Cheng ;   et al.
2005-05-12
Method for simultaneous degas and baking in copper damascene process
App 20050054202 - Pan, Shing-Chyang ;   et al.
2005-03-10
Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers
Grant 6,846,756 - Pan , et al. January 25, 2
2005-01-25
Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer
Grant 6,821,905 - Pan , et al. November 23, 2
2004-11-23
Refractory metal nitride barrier layer with gradient nitrogen concentration
App 20040029377 - Lee, Hsien-Ming ;   et al.
2004-02-12
Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer
App 20040023497 - Pan, Shing-Chyang ;   et al.
2004-02-05
Method for preventing cracking and improving barrier layer adhesion in multi- layered low-k semiconductor devices
App 20040023485 - Pan, Shing-Chyang ;   et al.
2004-02-05
Method of avoiding plasma arcing during RIE etching
App 20030235994 - Pan, Shing-Chyang ;   et al.
2003-12-25
Plasma treatment method for fabricating microelectronic fabrication having formed therein conductor layer with enhanced electrical properties
Grant 6,656,832 - Pan , et al. December 2, 2
2003-12-02
Low-strength plasma treatment for interconnects
App 20030205822 - Lin, Keng-Chu ;   et al.
2003-11-06

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed