loadpatents
name:-0.024566888809204
name:-0.024296998977661
name:-0.00059795379638672
Jost; Mark E. Patent Filings

Jost; Mark E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jost; Mark E..The latest application filed is for "methods of forming semiconductor structures".

Company Profile
0.18.13
  • Jost; Mark E. - Boise ID
  • Jost; Mark E. - Fishkill NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods Of Forming Semiconductor Structures
App 20100087060 - Yin; Zhiping ;   et al.
2010-04-08
Interconnect structures with interlayer dielectric
Grant 7,659,630 - Yin , et al. February 9, 2
2010-02-09
Dry etching process to form a conductive layer within an opening without use of a mask during the formation of a semiconductor device
Grant 7,326,647 - Schrinksy , et al. February 5, 2
2008-02-05
Interconnect Structures
App 20070278695 - Yin; Zhiping ;   et al.
2007-12-06
Dry etching process to form a conductive layer within an opening without use of a mask during the formation of a semiconductor device
App 20070049038 - Schrinksy; Alex J. ;   et al.
2007-03-01
Methods of etching a contact opening over a node location on a semiconductor substrate
App 20060024973 - Jost; Mark E. ;   et al.
2006-02-02
Methods of etching a contact opening over a node location on a semiconductor substrate
Grant 6,982,228 - Jost , et al. January 3, 2
2006-01-03
Method of etching a contact opening
Grant 6,828,252 - Jost , et al. December 7, 2
2004-12-07
Method of etching a contact opening
App 20040198061 - Jost, Mark E. ;   et al.
2004-10-07
Utilization of disappearing silicon hard mask for fabrication of semiconductor structures
Grant 6,787,472 - Givens , et al. September 7, 2
2004-09-07
Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures
Grant 6,689,693 - Givens , et al. February 10, 2
2004-02-10
Methods of forming protective segments of material, and etch stops
Grant 6,653,241 - Jost , et al. November 25, 2
2003-11-25
Methods Of Forming Protective Seqments Of Material, And Etch Stops
App 20030176070 - Jost, Mark E. ;   et al.
2003-09-18
Methods Of Forming Protective Segments Of Material, And Etch Stops
App 20030176076 - Jost, Mark E. ;   et al.
2003-09-18
Methods of forming protective segments of material, and etch stops
Grant 6,620,734 - Jost , et al. September 16, 2
2003-09-16
Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns
Grant 6,605,516 - Jost , et al. August 12, 2
2003-08-12
Utilization of disappearing silicon hard mask for fabrication of semiconductor structures
App 20030143856 - Givens, John H. ;   et al.
2003-07-31
Chemical vapor deposition methods
Grant 6,596,641 - Jost , et al. July 22, 2
2003-07-22
Methods of etching a contact opening over a node location on a semiconductor substrate
App 20030045111 - Jost, Mark E. ;   et al.
2003-03-06
Utilization of disappearing silicon hard mask for fabrication of semiconductor structures
App 20030036271 - Givens, John H. ;   et al.
2003-02-20
Chemical vapor deposition methods and methods of etching a contact opening over a node location on a semiconductor substrate
App 20020123221 - Jost, Mark E. ;   et al.
2002-09-05
Utilization of disappearing silicon hard mask for fabrication of semiconductor structures
App 20020102854 - Givens, John H. ;   et al.
2002-08-01
Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns
App 20010007786 - Jost, Mark E. ;   et al.
2001-07-12
Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material
Grant 6,153,527 - Jost , et al. November 28, 2
2000-11-28
Semiconductor processing methods, and methods of forming capacitors
Grant 6,127,239 - Jost , et al. October 3, 2
2000-10-03
Method of forming wafer alignment patterns
Grant 6,046,094 - Jost , et al. April 4, 2
2000-04-04
Method of forming recessed container cells
Grant 5,888,877 - Dennison , et al. March 30, 1
1999-03-30
Semiconductor processing methods of forming a contact opening to a semiconductor substrate
Grant 5,869,403 - Becker , et al. February 9, 1
1999-02-09
Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material
Grant 5,739,068 - Jost , et al. April 14, 1
1998-04-14
Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns
Grant 5,700,732 - Jost , et al. December 23, 1
1997-12-23
Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
Grant 5,258,318 - Buti , et al. November 2, 1
1993-11-02

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