U.S. patent number RE41,774 [Application Number 11/604,190] was granted by the patent office on 2010-09-28 for data transmission process with auto-synchronized correcting code, auto-synchronized coder and decoder, corresponding transmitter and receiver.
This patent grant is currently assigned to Commissariat a l'Energie Atomique. Invention is credited to Mathieu Bouvier des Noes, Didier Lattard, Marc Laugeois, Jean-Remy Savel.
United States Patent |
RE41,774 |
Laugeois , et al. |
September 28, 2010 |
Data transmission process with auto-synchronized correcting code,
auto-synchronized coder and decoder, corresponding transmitter and
receiver
Abstract
A data transmission process with auto-synchronised correcting
code, auto-synchronised coder and decoder, corresponding
transmitter and receiver. According to the invention,
synchronisation management signals (HS, SS, ID) are formed and,
under the control of these signals, a header is inserted before a
data group and after it a correcting code. At receive end, these
synchronisation management signals are reconstituted, the presence
of a header is detected and any erroneous symbols are corrected.
The invention also provides for an auto-synchronised coder and a
decoder and for a transmitter and a receiver using them.
Inventors: |
Laugeois; Marc (Grenoble,
FR), Lattard; Didier (Recurel, FR), Savel;
Jean-Remy (La Tronche, FR), Bouvier des Noes;
Mathieu (Grenoble, FR) |
Assignee: |
Commissariat a l'Energie
Atomique (Paris, FR)
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Family
ID: |
8851241 |
Appl.
No.: |
11/604,190 |
Filed: |
November 22, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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Reissue of: |
09878343 |
Jun 12, 2001 |
07095818 |
Aug 22, 2006 |
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Foreign Application Priority Data
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Jun 14, 2000 [FR] |
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0007563 |
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Current U.S.
Class: |
375/365; 375/356;
455/502; 375/354; 370/509; 375/359 |
Current CPC
Class: |
H04L
7/041 (20130101); H04L 7/048 (20130101); H04L
1/0041 (20130101); H04L 1/0045 (20130101); H04L
1/0057 (20130101) |
Current International
Class: |
H04L
7/00 (20060101) |
Field of
Search: |
;375/365,359,356,354
;455/502 ;370/509 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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0 758 168 |
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Feb 1997 |
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EP |
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0758168 |
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Feb 1997 |
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EP |
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0 847 169 |
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Jun 1998 |
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EP |
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0847169 |
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Jun 1998 |
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EP |
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Primary Examiner: Wang; Ted M
Attorney, Agent or Firm: Connolly Bove Lodge & Hutz
LLP
Parent Case Text
.Iadd.Notice: More than one reissue application has been filed for
the reissue of U.S. Pat. No. 7,095,818. The reissue applications
are the present application and a divisional application based on
the present application (U.S. patent application Ser. No.
12/558,250) on Sep. 11, 2009..Iaddend.
Claims
What is claimed is:
1. A data transmission process with auto-synchronized correcting
code, comprising: defining a timing of bits of the data, to be
transmitted, by a clock signal and forming synchronization
management signals comprising: a symbol clock signal m number of
times less fast than the clock signal, where m is an integer, and m
bits constituting an information symbol, a symbol synchronization
signal capable of designating the first symbol of a packet, and a
data acquisition interruption signal intervening every K number of
symbols, where K is a pre-set integer; inserting a header before a
first group of K symbols and inserting a second group of R symbols
after said first group, the second group of R symbols comprising a
correcting code corresponding to the K symbols of the first group,
R being a pre-set integer dependent on a correcting code type used,
the first and second groups of(R+K) symbols forming a packet, and
the header being a header specific to this packet, under control of
the data acquisition interrupting signal; and modulating and
transmitting each packet with its header; demodulating the signal
received and extracting the clock signal; implementing a header
search process in the demodulated signal and, when the header is
detected, inhibiting the header search process and generating a
symbol synchronization symbol; processing the received packet so as
to correct any erroneous symbols of the first group by the
correcting code of the second group and reactivating the header
search process after each packet processing, under the control of
the symbol clock and symbol synchronization signals; and
retrieving, from the corrected symbols, the transmitted data.
2. The process according to claim 1, wherein: at transmission, said
modulating is effected by spread spectrum by means of pseudo-random
sequences; and correlating with the pseudo-random sequences at
transmission.
3. The process according to claim 1, wherein the correcting code is
a Reed-Solomon type code.
4. An auto-synchronized coder, comprising: means for forming
synchronization management signals, wherein the synchronization
management signals comprise: a symbol clock signal m times less
fast as a clock signal timing the data bits, where m is an integer,
and m bits constitute an information symbol, a symbol
synchronization signal locating the start of each symbol, a data
acquisition interruption signal intervening every K number of
symbols, where K is a pre-set integer; and means for inserting,
under control of the acquisition interruption signal, a packet
header before a first group of K symbols, and a second group of R
symbols after said first group, the second group of R symbols
constituting a correcting code assigned to the K symbols of the
first group, R being a pre-set integer based at least in part upon
the correcting code type used, the first and second group of (R+K)
symbols forming a packet, and the header being a header specific to
this packet.
5. A transmitter, comprising: a transmission module configured to
modulate the data and to spread the spectrum of the data by a
pseudo-random sequence; and an auto-synchronized coda, before said
transmission module, comprising: means for forming synchronization
management signals, the synchronization management signals
comprising: a symbol clock signal m times less fast than a clock
signal timing the data bits, where m is an integer, m bits
constituting an information symbol, a symbol synchronization signal
locating the start of each symbol, and a data acquisition
interruption signal intervening every K number of symbols, where K
is a pre-set integer; means for inserting, under control of the
acquisition interruption signal, a packet header before a first
group of K symbols and a second group of R symbols after said first
group, the second group of R symbols constituting a correcting code
assigned to the K symbols of the first group, R being a pre-sent
integer dependent on the correcting code type used, the first and
second group of(R+K) symbols forming a packet, and the header being
a header specific to this packet.
.Iadd.6. A method of auto-synchronizing a correcting code for a
data stream of information symbols, comprising: inserting a packet
header into the data stream before a group of K information symbols
in the data stream, the packet header being associated with and
being specific to the group of K information symbols: inserting a
group of R correction code symbols in the data stream after the
group of K information symbols, the group of R correction code
symbols comprising a correcting code for the group of K information
symbols, and R comprising an integer value that is based at least
in part on the correcting code; transmitting the data stream
containing the packet header and the correcting code; and,
generating a data acquisition interruption signal based at least in
part on a timing of bits in an information symbol the data
acquisition interruption signal indicating K number of information
symbols, wherein a symbol has m bits, and wherein inserting a
packet header into the data stream before a group of K information
symbols in the data stream includes interrupting the data stream
and inserting the packet header into the data stream based at least
in part on the data acquisition interruption signal..Iaddend.
.Iadd.7. The method according to claim 6 wherein transmitting the
data stream including the correcting code further comprises:
modulating the data stream including the correcting code based at
least in part on a spread-spectrum modulation technique; and
transmitting the modulated data stream..Iaddend.
.Iadd.8. The method according to claim 6 further comprising:
receiving the data stream including the correcting code; detecting
a packet header in the received data stream including the
correcting code; and extracting from the received data stream the
group of K information symbols associated with the detected packet
header using the corresponding group of R correction code symbols
to correct one or more symbols in the group of K
symbols..Iaddend.
.Iadd.9. The method according to claim 8, wherein a symbol has m
bits, the method further comprising generating a symbol clock
signal and a symbol synchronization signal based at least in part
on a timing of bits in an information symbol, the symbol clock
signal including a frequency that is m times less than the timing
of bits of an information symbol and the symbol synchronization
signal capable of designating a first symbol of a group of K
information symbols, and wherein extracting from the received data
stream the group of K information symbols associated with the
detected packet header is based at least in part on a timing
provided by the symbol clock signal and the symbol synchronization
signal..Iaddend.
.Iadd.10. The method according to claim 8, wherein the received
data stream has been modulated based at least in part on a
spread-spectrum modulation technique, and wherein receiving the
data stream includes the correcting code further comprises
demodulating the modulated received data stream..Iaddend.
.Iadd.11. The method according to claim 8, wherein the correcting
code comprises a Reed-Solomon-based correcting code..Iaddend.
.Iadd.12. The method according to claim 6, wherein the correcting
code comprises a Reed-Solomon-based correcting code..Iaddend.
.Iadd.13. A coder, comprising: a synchronization signal generator
adapted to generate a data acquisition interruption signal
indicating K number of information symbols of a data stream
including information symbols; and a packet-header inserter adapted
to insert a packet header into the data stream before a group of K
information symbols based at least in part on the data acquisition
interruption signal, the packet header being specific to the group
of K information symbols, the inserter further inserting into the
data stream a group of R correcting-code symbols after the group of
K information symbols, the group of R correcting-code symbols being
associated with the group of K information symbols, R comprising an
integer based at least in part upon a correcting-code type of the
correcting-code symbols, the packet header, the group of K
information symbols and the group of R correcting-code symbols
forming a packet..Iaddend.
.Iadd.14. A coder according to claim 13, wherein the correcting
code symbols comprise a Reed-Solomon-based correcting
code..Iaddend.
.Iadd.15. The coder according to claim 13, further comprising: a
modulator adapted to modulate the data stream including the
correcting code symbols based at least in part on a spread-spectrum
modulation technique; and a transmitter adapted to transmit the
modulated data stream..Iaddend.
.Iadd.16. A coder, comprising: means for generating a data
acquisition interruption signal indicating K number of information
symbols of a data stream including information symbols; and
packet-header inserter means for inserting a packet header into the
data stream before a group of K information symbols based at least
in part on the data acquisition interruption signal the packet
header being specific to the group of K information symbols the
packet-header inserter means further adapted to insert into the
data stream a group of R correcting code symbols after the group of
K information symbols the group of R correcting code symbols being
associated with the group of K information symbols R comprising an
integer based at least in part upon a correcting-code type of the
correcting-code symbols the packet header, the group of K
information symbols and the group of R correcting-code symbols
forming a packet..Iaddend.
.Iadd.17. A coder according to claim 16, wherein the correcting
code symbols comprise a Reed-Solomon-based correcting
code..Iaddend.
.Iadd.18. The coder according to claim 16, further comprising:
modulator means for modulating the data stream including the
correcting code symbols based at least in part on a spread-spectrum
modulation technique; and transmitter means for transmitting the
modulated data stream..Iaddend.
.Iadd.19. A transmitter, comprising: a coder adapted to form a data
stream including a correcting-code, the coder comprising: a
synchronization signal generator adapted to generate a data
acquisition interruption signal indicating K number of information
symbols of a data stream including information symbols, and a
packet-header inserter adapted to insert a packet header into the
data stream before a group of K information symbols based at least
in part on the data acquisition interruption signal, the packet
header being specific to the group of K information symbols, the
inserter further inserting into the data stream a group of R
correcting-code symbols after the -group of K information symbols,
the group of R correcting-code symbols being associated with the
group of K information symbols, R comprising an integer based at
least in part upon a correcting-code type of the correcting-code
symbols, the packet header, the group of K information symbols and
the group of R correcting-code symbols forming a packet; and a
transmission module adapted to modulate the data stream including a
correcting-code using a spread-spectrum modulation
technique..Iaddend.
.Iadd.20. A transmitter according to claim 19, wherein the
correcting code comprises a Reed-Solomon-based correcting
code..Iaddend.
.Iadd.21. A transmitter according to claim 19, wherein the
transmission module is further adapted to transmit the modulated
data stream..Iaddend.
Description
TECHNICAL FIELD
The object of the present invention is a data transmission process
with auto-synchronised correcting code, an auto-synchronised coder
and decoder, and a corresponding transmitter and receiver.
The invention finds an application in telecommunications.
PRIOR ART
When a digital signal is disturbed during its propagation, it is
useful to provide a redundancy in the transmitted message so as to
correct the errors made. This redundancy may be obtained by an
error correcting code. Introducing such a code requires the data to
be framed, this framing being provided in a communication protocol.
It is not generally executed in what is called the physical layer
(which includes baseband modulation devices) but in a particular
link layer.
The appended FIGS. 1 to 5 show this technique. They correspond to
information symbols constituted by bytes of m bits, where m is an
integer dependent on the code selected, for example a power of 2,
like 8 (in which case the byte is an octet).
In FIG. 1, first of all, a coded frame format can be seen, at the
output from a coding circuit. The frame shown includes a header 10
(which is a frame synchronisation word) constituted by n symbols
each of m bits, a first group 12 of K symbols of m bits and lastly
a second group 14 of R symbols of m bits. This second group 14 is
the correcting code associated with the first group 12. Only the
first group 12 shows the information to be transmitted, the second
14, constituting a redundancy. The numbers K and R are
characteristic of the correcting code used. For example, for a
Reed-Solomon code, the total length of the message in bytes (i.e.
K+R) and the number of coding bytes (R) is shown.
FIG. 2 shows a coding circuit (or coder) allowing such a frame to
be constituted. As shown, this circuit 20 includes a
serial-to-parallel converter 22, a coder 24 and a
parallel-to-serial converter 26 (the converters 22 and 26 are
optional). A synchronisation signal S controls the circuits 22 and
24. The data to be coded D is introduced into the converter 22 and
the coded data Dc is extracted from the converter 26.
FIG. 3 shows the corresponding decoding circuit (or decoder). As
shown, this circuit 30 includes a serial-to-parallel converter 32,
a decoder 34 and a parallel-to-serial converter 36. The
synchronisation signal S controls the circuits 32 and 34. The coded
data Dc is applied to the converter 32 and the decoded data D is
extracted from the converter 36.
FIG. 4 shows interfacing means between the coding means and the
modulation means. This interfacing 40 includes a buffer memory 42
containing the data to be coded, a coder 44, a buffer memory 46,
for example of the FIFO (First In First Out) type, and a modulation
interface 48 the output 49 of which is connected to the modulation
means not shown. Synchronisation of the coder 44 is provided by the
synchronisation signal S.
FIG. 5 shows the corresponding demodulation-decoding interfacing.
As shown, this interfacing 50 includes an input 51 connected to the
demodulation means not shown, a circuit 52 for separating the
frames and interfacing with the demodulation means, a buffer memory
54, for example of the FIFO type, a decoder 56, and a data buffer
memory 58. The decoder is controlled by the synchronisation signal
S.
In the circuits in FIGS. 4 and 5, the FIFO memories 46 and 54 are
used to adapt the data rates between the coder and the modulation
or between the demodulation and the decoder.
In short, in this prior art, the use of a correcting code requires
special means. If a connection is used without such means and if it
is desired, in order to improve transmission performance, to
benefit from the correcting code, it will be essential to put in
management circuits.
The precise purpose of the present invention is to overcome this
drawback.
DISCLOSURE OF THE INVENTION
To this end, the invention proposes a process wherein the
correcting code is auto-synchronised and does not require any
addition of management circuits. Everything occurs in the physical
layer (coding and modulation or demodulation and decoding). The
upper layers of the protocol no longer have to format the frames
since the data to be transmitted is automatically associated with a
header and with a correcting code. The user does not have access to
the packet constituted and does not therefore have to manage the
synchronisation problems linked to the presence of the code. On the
decoder side, this effects a header search in the bit stream
provided by the demodulation stage. A synchronisation algorithm
allows reliable auto-synchronisation. No external interfacing is
necessary between the modulation (or demodulation) and the coding
(decoding). Adding a correcting code to a connection which does not
have one initially is therefore a totally transparent operation for
the user. The initial hardware configuration does not need to be
reviewed. The coder and decoder circuit are wired directly before
the baseband modulation circuit and after the demodulation circuit
respectively.
To be exact, the object of the invention is a data transmission
process with auto-synchronised correcting code, characterised in
that:
a) at transmission:
i) the data to be transmitted being constituted by bits having a
timing defined by a clock signal (H), synchronisation management
signals are formed including:
a symbol clock signal (HS) m times less fast than the clock signal
(H) where m is an integer, m bits constituting an information
symbol (S),
a synchronisation signal (SS) designating the first symbol of the
packet,
a data acquisition interruption signal (ID) intervening every K
symbols, where K is a pre-set integer,
ii) under the control of the data acquisition interruption signal
(ID), before a first group of K symbols is inserted a header and,
after said first group, is inserted a second group of R symbols
constituting a correcting code corresponding to the K symbols of
the first group, R being a pre-set integer dependent on the
correcting code type used, the first and second groups of (R+K)
symbols forming a packet, and the header a header specific to this
packet,
iii) each packet is modulated and transmitted in an appropriate way
with its header,
b) at the receive end:
i) the signal received is demodulated, and the bit clock signal (H)
is extracted from it,
ii) from the demodulated signal, a header search process is
implemented in the demodulated signals and, when a header is
detected, the header search process is inhibited, and the
synchronisation control (SS) is generated designating the first
packet signal;
iii) under the control of the symbol clock (HS) and symbol
synchronisation (SS) signals, the received packet is processed, so
as to correct any erroneous symbols of the first group by means of
the correcting code of the second group, and the header search
process is reactivated after each packet processing,
iv) from the corrected symbols the transmitted data is
retrieved.
In a particular embodiment,
a) at transmission, modulation is effected by spread spectrum by
means of pseudo-random sequences,
b) at the receive end, demodulation is effected by correlation with
the pseudo-random sequences used at transmission.
Another object of the present invention is an auto-synchronised
coder for the implementation of the process which has just been
defined. This coder is characterised in that it includes:
i) means for forming synchronisation management signals
including:
a symbol clock signal (HS) m times less fast than a clock signal
(H) timing the data bits, where m is an integer, m bits
constituting an information symbol (S),
a synchronisation signal (SS) designating the first symbol of the
packet,
a data acquisition interruption signal (ID) intervening every K
symbols, where K is a pre-set integer,
ii) means for inserting, under the control of the acquisition
interruption signal (ID), before a first group of K symbols a
packet header and, after said first group, a second group of R
symbols constituting a correcting code assigned to the K symbols of
the first group, R being a pre-set integer dependent on the
correcting code type used, the first and second groups of (R+K)
symbols forming a packet, and the header a header specific to this
packet.
Another object of this invention is an auto-synchronised decoder
for implementing the process which has just been defined. This
coder is characterised in that it includes:
i) means for constituting, from a data packet, a clock signal (H),
a symbol clock signal (HS) and a symbol synchronisation signal
(SS);
ii) means for implementing a header search process in the
demodulated packet and, when a header is detected, for inhibiting
the header search and for, under the control of the symbol clock
(HS) signals and the synchronisation signal (SS) designating the
first packet symbol, processing the packet received and for
correcting any erroneous symbols of the first group by means of the
correcting code of the second group and, for reactivating the
header search process after each packet processing.
Yet another object of the invention is a transmitter including a
transmission module able to modulate the data and to spread the
spectrum of this data by a pseudo-random sequence, this transmitter
being characterised in that it additionally includes, before said
transmission module, an auto-synchronised coder.
A final object of this invention is a receiver including a receive
module able to demodulate the data and to despread the spectrum of
this data by a pseudo-random sequence, this receiver being
characterised in that it additionally includes, after said receive
module, an auto-synchronised decoder.
All known correcting codes may be used in the invention, and in
particular the so-called Reed-Solomon code.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1, already described, shows a data packet including K
information symbols of m bits each, R correcting code symbols of m
bits each, a packet header;
FIG. 2, already described, shows a coding circuit according to the
prior art;
FIG. 3, already described, shows an decoding circuit according to
the prior art;
FIG. 4, already described, shows an already known interfacing
between the coding means and the modulation means;
FIG. 5, already described, shows an already known interfacing
between the demodulation means and the correcting code processing
means;
FIG. 6 shows a particular embodiment of an auto-synchronised coder
according to the invention;
FIG. 7 shows a particular embodiment of an auto-synchronised
decoder according to the invention;
FIG. 8 is a state diagram relating to the header search
process;
FIG. 9 shows an embodiment example of a circuit made by the
Applicant, working in transmission and/or in reception, with a
Reed-Solomon code and a modulation by direct sequence spread
spectrum.
DESCRIPTION OF PARTICULAR EMBODIMENTS
FIG. 6 shows the architecture of an auto-synchronised coder
according to the invention with an upstream interface. The upstream
interface 60 includes a buffer memory 61 containing data to be
transmitted D and a flip-flop 62 with three inputs P, En and CK,
and an output Q. The coder 63 itself includes a data processing
circuit 64 the function of which is to insert a header in the data
stream, an automatic synchronisation management circuit 65, this
circuit delivering three signals: a data acquisition interruption
signal ID, a symbol clock signal HS, m times less fast than the
clock signal H and a symbol synchronisation signal SS locating the
start of each symbol. The circuit 63 further includes a coder 66
operating on bytes (m bits, with, for example, m=8 if it is a
question of octets). This coder receives the symbols S from a
serial-to-parallel converter 67 (optional) and the symbol clock HS.
The coder 66 delivers a data stream organised into symbols with a
header, information symbols and redundancy symbols defined by the
correcting code used. The circuit 63 may further include a
parallel-to-serial converter 68 the output 69 of which delivers the
data which will then be processed by the modulation means not
shown.
The input En of the flip-flop 62 allows the data stream D to be
interrupted by means of the signal ID delivered by the circuit 65.
This interruption allows the header to be inserted and the coding
symbols to be added. The serial-to-parallel converter 67 allows m
bit symbols to be constituted from the data (if m=1, this converter
serves no purpose).
The clock H timing the bits is provided by the modulation
stage.
FIG. 7 shows the architecture of an auto-synchronised decoder
according to the invention. As shown, this decoder 70 includes a
header deletion circuit 71, receiving the bit stream coming from
the modulation means not shown, a circuit 72 implementing a header
detection algorithm and receiving the bit stream coming from the
demodulation means and delivering a symbol clock signal HS and a
synchronisation signal SS designating the first packet symbol. The
circuit 70 further includes a serial-to-parallel converter 74
(optional) receiving the symbol clock signal HS, a decoder 73
correcting any erroneous symbols and delivering corrected
information symbols, and lastly a parallel-to-serial converter 75
delivering the finally transmitted data. The bit clock H is
provided by the demodulation means.
FIG. 8 is a state diagram showing the header search algorithm in
the data stream. The blocks shown each correspond to a phase with
the following correspondence:
block 80: Phase 0 (header search initialisation),
block 81: Phase 1 (search for a new pattern in a time less than or
equal to a header time).
block 82: Phase 2 (transmission of a packet; inhibition of the
header search during a packet),
block 83: Phase 3 (search for a header pattern following the
processed packet),
block 84: Phase 4 (header search directly following the first bit
after the packet).
The operation of the process is then as follows. At the start of
the process, the inhibition signal is inactive. This means that
header search phase is operative (phase 0).
The bit stream provided by the demodulation stage is correlated by
the pseudo-random binary sequence of the header. If the correlation
exceeds a certain threshold, a flag is activated (phase
0.fwdarw.phase 1). When a sequence of patterns in the bit stream
appears as a header in a time less than or equal to the header
time, the flag will be activated several times (m.times.n.times.H)
(phase 1). Synchronisation is then effected on the last pattern
(i.e. the last pattern activating the flag) (transfer from phase 1
to phase 2).
The header search is then inhibited during a packet transmission
time (correcting code included). The flag cannot be activated
(phase 2). At the end of the packet, the inhibition signal returns
to the. inactive state, and a new header search begins (transfer
from phase 2 to phase 3 or 4).
If the flag is activated from the first bit following the packet
(phase 4), then synchronisation takes place on this pattern and the
header search inhibition is again activated. In the opposite case,
the search is effected as at the algorithm start (phase 3).
Transfer from phase 3 to phase 1 is effected in exactly the same
way as the transfer from phase 0 to phase 1.
A header sequence may be assumed to be present if the correlator
several times exceeds the threshold with a time between two
overshoots less than or equal to the header time. For this reason,
a header time window is open (phase 1). If no overshoot has
occurred during this time, the system is synchronised (transfer
from phase 1 to phase 2). If an overshoot has occurred, the window
is again initialised (you stay in phase 1).
During continuous transmission, a "quality assurance counter" may
be added. It demonstrates the reliability of the synchronisation.
Its operation is as follows: when a header is detected immediately
after the inhibition signal, the counter is incremented. The
threshold on the header search correlator may then be reduced.
In the opposite case, it is decreased. This means that the
previously detected header was not reliable, therefore that the
threshold was placed too low. The threshold must therefore be
increased.
FIG. 9, lastly, shows an example of an implementation of the
invention in the case of a Reed-Solomon coder defined by K=25 and
R=6 (it is therefore a code (31, 35), with m=8 (the symbols are
therefore octets). The modulation uses the direct sequence spread
spectrum technique. The circuit 90 corresponds to a transmitter and
the circuit 100 to a receiver. The whole corresponds to the circuit
which the Applicant denotes by "ICARE".
The transmitter 90 receives the data symbolised by the signal D and
includes a data generator 91, a correcting code synchronisation
module 92 including a Reed-Solomon coder 93 and a synchronisation
management circuit 94. It further includes a modulation module 95
including a modulator 96 of the DQPSK (Differential Quaternary
Phase Shift Keying) type, a block 97 phasing the pseudo-random
sequence with the datum and a circuit 98 for spreading the data
modulated by 96 by the sequence produced by 97.
This transmitter 90 produces baseband signals I and Q respectively
in phase and in phase opposition with a carrier and which will come
to modulate a carrier RF symbolised by the block 99. The
transmitter 90 also produces clock signals H symbolised in the
block 85.
The receiver 100 receives the baseband signals I and Q symbolised
by the block 86 and synchronisation signals symbolised by the block
87. It includes a reception module 102 including a filter 103
adapted to the pseudo-random sequence used at transmission, a
differential demodulation (DQPSK) circuit 104, a circuit 105 for
evaluating the transmission channel, detecting the correlation
peaks (PC), for retrieving data D, for forming a synchronisation
signal (S) and a clock (H), all signals shown diagrammatically in
the block 110. The receiver 100 further includes an
auto-synchronised decoder module 107, including a Reed-Solomon
decoder 108 and a header detection and auto-synchronisation circuit
109. In the embodiment shown, the module is preceded by a data
tester generator 106.
In the transmitter, the module 92 corresponds to the circuit 63 in
FIG. 6 and, in the receiver, the module 107 corresponds to the
circuit 70 in FIG. 7. The other means are conventional in direct
sequence spread spectrum technology and are well known to the man
skilled in the art.
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