U.S. patent number RE39,918 [Application Number 09/616,821] was granted by the patent office on 2007-11-13 for direct current sum bandgap voltage comparator.
This patent grant is currently assigned to STMicroelectronics, Inc.. Invention is credited to William Carl Slemmer.
United States Patent |
RE39,918 |
Slemmer |
November 13, 2007 |
Direct current sum bandgap voltage comparator
Abstract
A direct current sum bandgap voltage comparator for detecting
voltage changes in a power supply. The direct current sum bandgap
voltage comparator includes a summing node, current sources
connected to the summing node and the power supply, and an
indicator circuit connected to the summing node. Each current
source supplies a current to the summing node wherein the summing
node voltage level is responsive to the currents supplied. The
indicator circuit is responsive to changes in the summing node
voltage level and generates at an output a logical signal at one
state when the summing node voltage level is greater than a
predetermined value and generates the logical signal at the output
at another state when the summing node voltage level is less than
the predetermined value, the predetermined value corresponding to a
preselected power supply voltage.
Inventors: |
Slemmer; William Carl (Celina,
TX) |
Assignee: |
STMicroelectronics, Inc.
(Carrollton, TX)
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Family
ID: |
22003501 |
Appl.
No.: |
09/616,821 |
Filed: |
July 14, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
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08606233 |
Feb 23, 1996 |
|
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08056301 |
Apr 30, 1993 |
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Reissue of: |
08932930 |
Sep 18, 1997 |
05781043 |
Jul 14, 1998 |
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Current U.S.
Class: |
327/78; 327/361;
327/539; 327/541; 327/542; 327/543; 327/77 |
Current CPC
Class: |
G01R
19/16538 (20130101); G05F 3/24 (20130101); G05F
3/30 (20130101); G11C 5/141 (20130101); G11C
5/143 (20130101); G05F 3/262 (20130101) |
Current International
Class: |
H03K
5/22 (20060101) |
Field of
Search: |
;327/77,78,361,539,541,542,543 ;323/312,314,315 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Cunningham; Terry D.
Attorney, Agent or Firm: Jorgenson; Lisa K. Santarelli;
Bryan A.
Parent Case Text
This is a Continuation of application Ser. No. 08/606,233, filed
Feb. 23, 1996, now abandoned, which is a Continuation of
application Ser. No. 08/056,301, filed Apr. 30, 1993, now
abandoned.
Claims
What is claimed is:
1. A direct current sum bandgap voltage comparator comprising: a
summing node; a plurality of current sources connected to the
summing node, each current source further comprising at least one
transistor, and each current source supplying a current to the
summing node and being connected to a power supply voltage, wherein
the currents sources supply currents according to a bandgap
equation:
K.sub.1(V.sub.CC-V.sub.T)+K.sub.1V.sub.T=K.sub.2V.sub.BE+K.sub.3(kT/q)
where V.sub.CC is the power supply voltage, V.sub.T is a
predetermined threshold voltage of a transistor in a first current
source within the plurality of current sources, V.sub.BE is a base
emitter voltage of a transistor in a second current source within
the plurality of current sources, k is Boltzman's constant, T is a
temperature in kelvin of a transistor in a third current source
within the plurality of current sources, q is an electronic charge
constant, and K.sub.1, K.sub.2, and K.sub.3 are constants
determined by a resistance and a transistor length in the first,
second, and third current sources, respectively; and an indicator
circuit having an input connected to the summing node and
generating a logical signal at an output, responsive to voltage
changes in the summing node.
2. The direct current sum bandgap voltage comparator of claim 1,
wherein the plurality of current sources are current mirrors.
3. A direct current sum bandgap voltage comparator comprising: a
summing node; a plurality of current sources connected to the
summing node, each current source further comprising at least one
transistor, and each current source supplying a current to the
summing node and being connected to a power supply voltage; and an
indicator circuit having an input connected to the summing node and
generating a logical signal at an output, responsive to voltage
changes in the summing node, wherein the currents sources supply
currents according to a bandgap equation:
K.sub.1(V.sub.CC-V.sub.T)+K.sub.1V.sub.T=K.sub.2V.sub.BE+K.sub.3(kT/q)
where V.sub.CC is the power supply voltage, V.sub.T is a
predetermined threshold voltage of a transistor in a first current
source within the plurality of current sources, V.sub.BE is a base
emitter voltage of a transistor in a second current source within
the plurality of current sources, k is Boltzman's constant, T is a
temperature in kelvin of a transistor in a third current source
within the plurality of current sources, q is an electronic charge
constant, and K.sub.1, K.sub.2, and K.sub.3 are constants
determined by a resistance and a transistor length in the first,
second, and third current sources, respectively, and wherein the
plurality of current sources comprises four current mirrors.
4. The direct current sum bandgap voltage comparator of claim 3,
wherein the first current mirror includes a plurality of
transistors and supplies a current to the summing node defined by
K.sub.1(V.sub.CC-V.sub.T).
5. The direct current sum bandgap voltage comparator of claim 4,
wherein the second current mirror includes a plurality of
transistors and supplies a current to the summing node defined by
K.sub.1V.sub.T.
6. The direct current sum bandgap voltage comparator of claim 5,
wherein the third current mirror includes a plurality of
transistors and supplies a current to the summing node defined by
K.sub.2V.sub.BE.
7. The direct current sum bandgap voltage comparator of claim 6,
wherein the fourth current mirror supplies a current to the summing
node defined by K.sub.3(kT/q).
8. The direct current sum bandgap voltage comparator of claim 7
further comprising a clamping circuit connected to the summing
node, wherein a voltage swing for the summing node, responsive to
changes in current supplied by the current mirrors, may be set
between predetermined voltages.
9. The direct current sum bandgap voltage comparator of claim 7
further comprising a cascode stage having at least a first and
second connections, the first connection is connected to the
summing node and the second connection is connected to one of the
four current mirrors.
10. The direct current sum bandgap voltage comparator of claim 7
further comprising a hysteresis circuit connected to the indicator
circuit to reduce noise.
11. The direct current sum bandgap voltage comparator of claim 7,
wherein the indicator circuit includes a pair of inverters
connected in series, wherein an input in the first inverter is the
input of the indicator circuit connected to the summing node and an
output of the second inverter is the output of the indicator
circuit.
12. The direct current sum bandgap voltage comparator of claim 11,
wherein the indicator circuit provides a logic one output if the
power supply is equal to or greater than a preselected voltage.
13. A zero power circuit comprising: a first circuit; a direct
current sum bandgap voltage comparator comprising: a summing node;
a plurality of current sources connected to the summing node, each
current source further comprising at least one transistor, and each
current source supplying a current to the summing node and being
connected to a power supply voltage, wherein the current sources
supply according to a bandgap equation:
K.sub.1(V.sub.CC-V.sub.T)+K.sub.1V.sub.T=K.sub.2V.sub.BE+K.sub.3(kT/q)
where V.sub.CC is the power supply voltage, V.sub.T is a
predetermined threshold voltage of a transistor in a first current
source within the plurality of current sources, V.sub.BE is a base
emitter voltage of a transistor in a second current source within
the plurality of current sources, k is Boltzman's constant, T is a
temperature in kelvin of a transistor in a third current source
within the plurality of current sources, q is an electronic charge
constant, and K.sub.1, K.sub.2, and K.sub.3 are constants
determined by a resistance and a transistor length in the first,
second, and third current sources, respectively; an indicator
circuit having an input connected to the summing node and
generating a logical signal at an output, responsive to changes in
the summing node; and a switching circuit for providing power to
the first circuit from a primary power supply and a secondary power
supply, the switching circuit being connected to the output of the
indicator circuit, wherein power from the primary power supply is
supplied to the first circuit if the logical signal indicates that
the power supply voltage is equal to or greater than the
predetermined threshold voltage and power from the secondary power
supply is supplied to the first circuit if the power supply voltage
is less than the predetermined threshold voltage.
14. A zero power circuit comprising: a first circuit; a direct
current sum bandgap voltage comparator comprising: a summing node;
a plurality of current sources connected to the summing node, each
current source further comprising at least one transistor, and each
current source supplying a current to the summing node and being
connected to a power supply voltage; an indicator circuit having an
input connected to the summing node and generating a logical signal
at an output, responsive to changes in the summing node; and a
switching circuit for providing power to the first circuit from a
primary power supply and a secondary power supply, the switching
circuit being connected to the output of the indicator circuit,
wherein power from the primary power supply is supplied to the
first circuit if the logical signal indicates that the power supply
voltage is equal to or greater than the preselected voltage and
power from the secondary power supply is supplied to the first
circuit if the power supply voltage is less than the preselected
voltage, wherein the current sources supply according to a bandgap
equation:
K.sub.1(V.sub.CC-V.sub.T)+K.sub.1V.sub.T=K.sub.2V.sub.BE+K.sub.3(kT/q)
where V.sub.CC is the power supply voltage, V.sub.T is a
predetermined threshold voltage of a transistor in a first current
source within the plurality of current sources, V.sub.BE is a base
emitter voltage of a transistor in a second current source within
the plurality of current sources, k is Boltzman's constant, T is a
temperature in kelvin of a transistor in a third current source
within the plurality of current sources, q is an electronic charge
constant, and K.sub.1, K.sub.2, and K.sub.3 are constants
determined by a resistance and a transistor length in the first,
second, and third current sources, respectively, and wherein the
plurality of current sources comprises four current mirrors.
15. The zero power circuit of claim 14, wherein the secondary power
supply is a battery.
16. The zero power circuit of claim 14, wherein the first current
mirror includes a plurality of transistors and supplies a current
to the summing node defined by K.sub.1(V.sub.CC-V.sub.T).
17. The zero power circuit of claim 14, wherein the second current
mirror includes a plurality of transistors and supplies a current
to the summing node defined by K.sub.1V.sub.T.
18. The zero power circuit of claim 17, wherein the third current
mirror includes a plurality of transistors and supplies a current
to the summing node defined by K.sub.2V.sub.BE.
19. The zero power circuit of claim 18, wherein the fourth current
mirror supplies a current to the summing node defined by
K.sub.3(kT/q).
20. The zero power circuit of claim 19 further comprising a
clamping circuit connected to the summing node, wherein a voltage
swing for the summing node, responsive to changes in current
supplied by the current mirrors, may be set between selected
voltages.
21. The zero power circuit of claim 19 further comprising a cascode
stage located between the summing node and the current mirrors.
22. The zero power circuit of claim 19 further comprising a
hysteresis circuit connected to the indicator circuit to reduce
noise.
23. The direct current sum bandgap voltage comparator of claim 19,
wherein the indicator circuit provides a logic one output if the
power supply is equal to or greater than a preselected voltage.
.Iadd.24. A method, comprising: generating a first current that
changes with temperature according to a first polarity; generating
a second current that changes with temperature according to a
second polarity; combining the first and second currents to
generate a reference current; and comparing the reference current
to a third current that is dependent on a power-supply
voltage..Iaddend.
.Iadd.25. The method of claim 24 wherein: the first current changes
with temperature according to a positive polarity; and the second
current changes with temperature according to a negative
polarity..Iaddend.
.Iadd.26. The method of claim 24 wherein: the first current is
proportional to temperature; and the second current is inversely
proportional to temperature..Iaddend.
.Iadd.27. The method of claim 24 wherein: the first current
increases as temperature increases and decreases as temperature
decreases; and the second current decreases as temperature
increases and increases as temperature decreases..Iaddend.
.Iadd.28. The method of claim 24 wherein combining the first and
second currents comprises summing the first and second
currents..Iaddend.
.Iadd.29. The method of claim 24 wherein combining the first and
second currents comprises sinking the first and second currents
from a node..Iaddend.
.Iadd.30. The method of claim 24 wherein combining the first and
second currents comprises sourcing the first and second currents to
a node..Iaddend.
.Iadd.31. The method of claim 24 wherein comparing the reference
current comprises summing the reference current and the third
current at a node..Iaddend.
.Iadd.32. The method of claim 24 wherein comparing the reference
current comprises: sinking the reference current from a node; and
sourcing the third current to the node..Iaddend.
.Iadd.33. A method, comprising: generating a first current that
increases as temperature increases and that decreases as
temperature decreases; generating a second current that decreases
as temperature increases and that increases as temperature
decreases; generating a third current that is dependent on a first
voltage; and combining the first, second, and third currents at a
node to generate a second voltage on the node..Iaddend.
.Iadd.34. The method of claim 33 wherein combining the currents
comprises: sinking the first and second currents from the node; and
sourcing the third current to the node..Iaddend.
.Iadd.35. The method of claim 33 wherein: the first current is
related to a thermal voltage; and the second current is related to
a voltage across a forward-biased p-n junction..Iaddend.
.Iadd.36. The method of claim 33 wherein: the first current is
related to a thermal voltage; and the second current is related to
a base-emitter voltage of a bipolar transistor..Iaddend.
.Iadd.37. The method of claim 33 wherein the second current is
related to the natural logarithm of a current through a bipolar
transistor..Iaddend.
.Iadd.38. A method, comprising: generating a first current that is
related to temperature according to a first polarity; generating a
second current that is related to temperature according to a second
polarity; combining the first and second currents into a reference
current; generating a third current that is dependent on a first
voltage; and comparing the third current to the reference
current..Iaddend.
.Iadd.39. The method of claim 38 wherein: the first current is
related to a thermal voltage; the second current is related to a
voltage across a forward-biased p-n junction; and the third current
is dependent on a power-supply voltage..Iaddend.
.Iadd.40. The method of claim 38 wherein: combining the first and
second currents comprises sinking the first and second currents
from a node; and comparing the third current to the reference
current comprises, sourcing the third current to the node, and
comparing a second voltage on the node to a reference
voltage..Iaddend.
.Iadd.41. A method, comprising: generating a first current that is
proportional to a threshold voltage of a field-effect transistor;
generating a second current that is proportional to a difference
between a supply voltage and a threshold voltage of a second
field-effect transistor; generating a third current that is
proportional to a base-emitter voltage of a first bipolar
transistor; generating a fourth current that is proportional to
absolute temperature; and driving a node with the first, second,
third, and fourth currents..Iaddend.
.Iadd.42. The method of claim 41 wherein driving the node
comprises: sourcing the first and second currents to the node; and
sinking the third and fourth currents from the node..Iaddend.
.Iadd.43. The method of claim 41, further comprising comparing a
voltage on the node with a reference voltage..Iaddend.
.Iadd.44. The method of claim 41 wherein the first field-effect
transistor is matched to the second field-effect
transistor..Iaddend.
.Iadd.45. The method of claim 41 wherein the threshold voltage of
the first field-effect transistor is equal or approximately equal
to the threshold voltage of the second field-effect
transistor..Iaddend.
.Iadd.46. A method, comprising: generating a first current that
equals a product of a first constant and a threshold voltage of a
first field-effect transistor; generating a second current that
equals a product of a second constant and a difference between a
supply voltage and a threshold voltage of a second field-effect
transistor; generating a third current that equals a product of a
third constant and a base-emitter voltage of a bipolar transistor;
generating a fourth current that equals a product of a fourth
constant and a thermal voltage; and driving a node with the first,
second, third, and fourth currents..Iaddend.
.Iadd.47. The method of claim 46 wherein the first constant equals
the second constant..Iaddend.
.Iadd.48. The method of claim 46 wherein driving the node
comprises: sourcing the first and second currents to the node; and
sinking the third and fourth currents from the node..Iaddend.
.Iadd.49. A method, comprising: generating a first current that
changes with temperature according to a first polarity; generating
a second current that changes with temperature according to a
second polarity; combining the first and second currents to
generate a reference current; and comparing the reference current
to a third current that is proportional to a power-supply
voltage..Iaddend.
.Iadd.50. A method, comprising: generating with a first current
source that is powered by a supply voltage a reference current that
has a temperature coefficient and that is independent of the supply
voltage; providing the reference current at a node; generating with
a second current source that is powered by the supply voltage a
supply-related current having approximately the temperature
coefficient and being related to the supply voltage; providing the
supply-related current at the node; and comparing the reference
current to the supply-related current at the node..Iaddend.
.Iadd.51. The method of claim 50 wherein: providing the reference
current at the node comprises sinking the reference current from
the node; and providing the supply-related current at the node
comprises sourcing the supply-related current to the
node..Iaddend.
.Iadd.52. The method of claim 50 wherein comparing the reference
current comprises summing the reference current and the
supply-related current at the node to generate a
voltage..Iaddend.
.Iadd.53. A method, comprising: generating a reference current
having a first temperature coefficient; comparing the reference
current to a supply-related current that is related to a
power-supply voltage and that has or has approximately the first
temperature coefficient; wherein comparing the reference current
comprises summing the reference current and the supply-related
current at a node to generate a voltage; connecting the
power-supply voltage to a load if the voltage is greater than a
predetermined level; and connecting a secondary supply to the load
if the voltage is less than the predetermined level..Iaddend.
.Iadd.54. A method, comprising: generating a first current that is
related to temperature according to a first polarity; generating a
second current that is related to temperature according to a second
polarity; combining the first and second currents into a reference
current; generating a third current that is related to temperature
according to the first polarity; generating a fourth current that
is related to a supply voltage and that is related to temperature
according to the second polarity; combining the third and fourth
currents into a supply-related current; and comparing the reference
current to the supply-related current..Iaddend.
.Iadd.55. The method of claim 54 wherein the fourth current is
proportional to the supply voltage..Iaddend.
.Iadd.56. The method of claim 54 wherein the supply-related current
is proportional to the supply voltage..Iaddend.
.Iadd.57. The method of claim 54 wherein: the first and third
currents are inversely proportional to temperature; and the second
and fourth currents are proportional to temperature..Iaddend.
.Iadd.58. A method, comprising: generating with a first current
source that is powered by a supply voltage a reference current that
has a temperature coefficient and that is independent of the supply
voltage; providing the reference current at a node; generating with
a second current source that is powered by the supply voltage a
supply-related current having approximately the temperature
coefficient and being related to the supply voltage; providing the
supply-related current at the node; and neither sourcing to nor
sinking from the node a current other than the reference and
supply-related currents..Iaddend.
.Iadd.59. The method of claim 58 wherein: providing the reference
current at the node comprises sinking the reference current from
the node; and providing the supply-related current at the node
comprises sourcing the supply-related current to the
node..Iaddend.
.Iadd.60. A method comprising: generating with a first current
source that is powered by a supply voltage a reference current that
has a temperature coefficient and that is independent of the supply
voltage; providing the reference current at a comparison node;
generating with a second current source that is powered by the
supply voltage a supply-related current having approximately the
temperature coefficient and being related to the supply voltage;
providing the supply-related current at the comparison node; and
comparing a voltage on the comparison node to a reference
voltage..Iaddend.
.Iadd.61. The method of claim 60 wherein: providing the reference
current at the comparison node comprises sinking the reference
current from the comparison node; and providing the supply-related
current at the comparison node comprises sourcing the
supply-related current to the comparison node..Iaddend.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits and in
particular to MOS integrated circuits. Still more particularly, the
present invention relates to bandgap reference circuits in
insulated gate FET semiconductor integrated circuits.
2. Description of the Prior Art
In some situations it is desirable to provide retention of data in
integrated circuits such as memory devices. A number of circuits
are commercially available for retaining data in SRAMS when power
is removed. These devices are often known as "zero power circuits".
Typically, in a zero power circuit, the contents of the circuit are
protected in the event that the power supply voltage to that
circuit drops below some predetermined or preselected threshold
voltage. This protection may be accomplished by switching the
circuit from the primary power supply to a secondary power supply,
typically an integral battery, when the voltage of the primary
power supply drops below the selected threshold voltage. Secondary
or backup power supplies are well known, as may be seen in U.S.
Pat. Nos. 4,381,458 and 4,645,943.
Power controller circuits exist, which provide automatic sensing of
a primary power source voltage. These power controller circuits
provide automatic switching to a secondary power source when the
primary power source voltage drops below a predetermined threshold
voltage. An example of one such system may be found in U.S. Pat.
No. 5,121,359, which describes a programmable logic device with a
backup power supply that is automatically provided when a power
loss at an input pin is detected. U.S. Pat. No. 4,654,829 discloses
a portable non-volatile memory module, using a comparator and
switching circuitry to switch between a primary power supply and a
secondary power supply, such as a battery power supply.
Past approaches in setting or selecting the voltage level in a zero
power circuit has involved the use of many bipolar devices, large
resistors, oscillators, switched capacitors, autozero devices, etc.
A bandgap reference circuit is one circuit that may be used to set
that voltage level. One drawback with a typical bandgap reference
circuit is that a large number of devices are needed for
implementation. As a result, a large amount of area on a
semiconductor chip is required. In addition to the area problem,
typical bandgap reference circuits also are fairly sensitive to
noise within the circuit. For example, active memory circuits are
usually noisy and known bandgap circuits used with active memories
circuits are usually sensitive to the noise generated.
Therefore it would be desirable to have a circuit that is smaller,
simpler, and less sensitive to noise.
SUMMARY OF THE INVENTION
The present invention provides a direct current sum bandgap voltage
comparator for detecting voltage changes in a power supply. The
direct current sum bandgap voltage comparator includes a summing
node, current sources, and an indicator circuit. The current
sources are connected to the summing node and each current source
supplies a current to the summing node, wherein the voltage at the
summing node is responsive to the current supplied to the summing
node. The indicator circuit has an input connected to the summing
node and generates a logical signal at an output that is responsive
to voltage changes in the summing node.
The direct current sum bandgap voltage comparator may be used in a
zero power circuit also including a circuit, in which power is to
be maintained, and a switching circuit for providing power to the
first circuit from a primary power supply and a secondary power
supply. The switching circuit is connected to the output of the
indicator circuit, wherein power from the primary power supply is
supplied to the first circuit if the logical signal indicates that
the power supply voltage is equal to or greater than the
preselected voltage, and power from the secondary power supply is
supplied to the first circuit if the power supply voltage is less
than the preselected voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
The novel features believed characteristic of the invention are set
forth in the appended claims. The invention itself however, as well
as a preferred mode of use, and further objects and advantages
thereof, will best be understood by reference to the following
detailed description of an illustrative embodiment when read in
conjunction with the accompanying drawings, wherein:
FIG. 1 is a block diagram of a zero power circuit according to the
present invention;
FIG. 2 is a schematic diagram of a direct current sum bandgap
voltage comparator according to the present invention; and
FIG. 3 is a schematic diagram of an alternative direct current sum
bandgap voltage comparator according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to FIG. 1, a block diagram of a zero power circuit 2
on a chip is illustrated. Zero power circuit 2 is connected to a
primary power supply 4 and has a secondary power supply 6, located
within an integral package. Secondary power supply 6 is typically a
battery constructed in the plastic package housing the chip. Other
secondary power supplies, such as, for example, a battery located
outside the package may also be used.
Zero power circuit 2 includes a switching circuit 8, a memory 10,
and a direct current sum bandgap voltage (DCSBV) comparator 12
constructed according to the present invention. Switching circuit 8
is connected to primary power supply 4 and secondary power supply
6. This circuit controls the power supplied to memory 10 and may
include logic to provide for continuous supply of power to memory
10 during switching back and forth between primary power supply 4
and secondary power supply 6.
DCSBV comparator 12 has an input connected to primary power supply
4 and output connected to switching circuit 8. DCSBV comparator 12
has an output connected to switching circuit 8 to indicate when the
primary power supply voltage is at or above a preselected voltage
or drops below the preselected voltage.
Those of ordinary skill in the art will realize that the zero power
circuit 2 may include additional circuits and that various circuits
may be used in place of memory 10. Switching circuit 8 may be
implemented with a number different designs known to those of
ordinary skill in the art.
A DCSBV comparator may be constructed using four current sources
each of which generates a current representing one of the terms of
a bandgap equation:
K.sub.1(V.sub.CC-V.sub.T)+K.sub.1V.sub.T=K.sub.2V.sub.BE+K.sub.-
3(kT/q) (1) where V.sub.CC is the power supply voltage, V.sub.T is
the absolute value of the threshold voltage, and V.sub.BE is the
base emitter voltage, kT/q is equal to the thermal voltage, where k
is Boltzman's constant, T is the temperature in kelvin, and q is
the electronic charge. Voltages (V.sub.CC-V.sub.T). V.sub.T,
V.sub.BE, and kT/q are converted to currents in four current mirror
circuits. Other equivalent forms of this equation may be
implemented according to other embodiments of the present
invention.
The four current sources may be provided using current mirrors A-D,
as illustrated in the schematic diagram of a current sum bandgap
voltage (DCSBV) comparator in FIG. 2. Current mirror A generates a
current: .varies..times. ##EQU00001## Current mirror B generates a
current: .varies..times. ##EQU00002## Current mirror C generates a
current: .varies..times. ##EQU00003## while current mirror D
generates a current: .varies..times. ##EQU00004## The constants
K.sub.1-K.sub.3 from equation (1) may be set by resistors and
scaled transistors in the current mirrors.
The currents contributed by each of the current mirrors, A-D, are
summed at a summing node, referred to as node VSUM. The node will
swing to the edge of saturation corresponding to the mirror or
current mirrors supplying the larger current or currents. Node VSUM
is connected to two complementary metal-oxide semiconductor (CMOS)
inverters 20 and 22 formed by transistors C1-C4, where transistors
C1 and C3 are p-channel metal-oxide semiconductor field effect
transistors (MOSFETs) and transistors C2 and C4 are n-channel
MOSFETs. Inverters 20 and 22 are used as detectors for node VSUM
and provide for a rail-to-rail voltage swing at output 24 of the
DCSBV comparator.
Current mirror circuit A is constructed from sized transistors
M1-M4, T1, B1, and B2 and resistor R.sub.1. Transistors M1-M4, and
T1 are MOSFETs. Transistors M1 and M2 are p-channel MOSFETs, while
transistors M3, M4, and T1 are n-channel MOSFETs. Transistors B1
and B2 are bipolar junction transistors. The collectors and bases
of transistors B1 and B2 are connected to power supply voltage
V.sub.CC; the sources of transistors M3 and M4 are connected to
power supply voltage GND, which is connected to ground. Resistor
R.sub.1 has a one end connected to the emitter of transistor B2 and
the other end connected to the source of transistor M2.
Transistors M1-M4, T1, B1, and B2 are sized transistors and are
employed to obtain different current densities in different parts
of current mirror circuit A. Transistors M1 and M3 are sized to
provide a current flow that is ten times the current generated by
transistors M2 and M4. The emitter area of transistor B2 is twice
that of transistors B1. The voltage across resistor R.sub.1
provides a current. The sizing of the transistors and the resistor
R.sub.1 is selected to generate a current of: .times..function.
##EQU00005## through transistor M4, where J.sub.1 is the current
density of transistor B1 and J.sub.2 is the current density of
transistor B2.
Transistor T1 is designed to generate a current that is N times the
current flowing through transistor M4. As a result, the current
contributed by current mirror A is: .times.
.times..rho..times..times..function. ##EQU00006## where R.sub.1 has
been replaced by sheet resistance .rho..sub.s and the number of
squares r.sub.1. In the preferred embodiment, the sheet resistance
.rho..sub.s for all of the resistors in the circuit will be the
same. Therefore, the constant K.sub.3 in equation (1) is as
follows: .times..function. ##EQU00007## By scaling the current in
the left and right legs of current mirror A, the need for a large
number of bipolar structures (i.e., 30 or more) is eliminated.
Current mirror circuit B includes transistors M5-M8, transistor B3,
and resistor R.sub.2. Transistors M5 and M6 are p-channel MOSFETs,
while transistors M7 and M8 are n-channel MOSFETs. Transistor B3 is
a bipolar junction transistor.
Resistor R.sub.2 has one end connected to the drain of transistor
M5 and a second end connected to power supply voltage V.sub.CC. The
base and collector of transistor B3 also are connected to power
supply voltage V.sub.CC, while the sources of transistors M7 and M8
are connected to power supply voltage GND.
Transistors M5-M8 and T2 are sized MOSFETs. Transistors M6 and M8
are scaled to generate a current flow that is one tenth of the
current flowing through transistors M5 and M7. The current flowing
through transistors M5 and M7 is equal to the current flowing
through transistors M2 and M4 in current mirror A. Transistor T2 is
constructed to provide a current flow that is M times the current
flowing through transistor M7. The voltage V.sub.BE is set up by
transistor B3 (that is, V.sub.BE is the base-emitter voltage of
transistor B3), and resistor R.sub.2 sets up the current; the
voltage drop across R.sub.2 is V.sub.BE. As a result, current
mirror B generates a current: .rho..times. ##EQU00008## where
.rho..sub.s is the sheet resistance of resistor R.sub.2 and r.sub.2
is the number of squares in resistor R.sub.2. The constant K.sub.2
from equation (1) is defined as: ##EQU00009##
Next, current mirror C includes transistors M9-M15, and T3 and
resistor R.sub.3. Resistor R.sub.3 has one end connected to the
source of transistor M11 and another end connected to power supply
voltage V.sub.CC. Transistor M9 has its source connected to power
supply voltage V.sub.CC, while the sources of transistors M12, M13,
and M14 are connected to ground power supply voltage GND. The
voltage V.sub.T is set up by transistor M9 (that is, V.sub.T is the
absolute value of the threshold voltage of transistor M9), while
resistor R.sub.3 sets up the current. The voltage drop across
R.sub.3 is V.sub.T
Transistors M9-M11, M15, and T3 are p-channel MOSFETS, while
transistors M12-M14 are n-channel MOSFETs. These transistors are
sized transistors. The current flowing through transistors M11 and
M13 is the same as the current flowing through transistors M14 and
M15. The current flowing through transistors M11 and M13-M15 is the
same as the current flowing through transistor M5 and M7 in current
mirror B. Transistors M9, M10, and M12 are sized to provide a
current flow that is one tenth of the current flowing through
transistors, M11, M13, M14, and M15. Transistor T3 is designed to
provide a current flow that is L times the current flowing through
transistor M14. Thus, current mirror C generates a current:
.rho..times. ##EQU00010## where .rho. is the sheet resistance of
resistor R.sub.3 and r.sub.3 is the number of squares in resistor
R.sub.3. The coefficient K.sub.1 in equation (1) is defined as:
##EQU00011## for current mirror C.
Current mirror D includes transistor M16, transistor T4, and
resistor R.sub.4. Both transistors M16 and T4 are p-channel MOSFETs
with their sources connected power supply voltage V.sub.CC.
Resistor R.sub.4 has one end connected to the drain of transistor
M16 and a second end connected to power supply voltage GND.
Transistor M16 sets up the voltage V.sub.CC-V.sub.T, while resistor
R.sub.4 sets up the current. The voltage drop across R.sub.4 is
V.sub.CC-V.sub.T.
Transistors M16 and T4 are scaled transistors. Transistor M16 is
designed to provide a current flow that is equal to the current
flowing through transistors M14 and M15; transistor T4 is
constructed to generate a current that is J times the current
flowing through transistor M16. Thus, the current generated by
current mirror D is: .times..rho..times. ##EQU00012## where the
coefficient K.sub.1 in the current mirror is set as: ##EQU00013##
Since both current mirrors C and D create current contributions
that are related to the coefficient K.sub.1, the current mirrors
must be sized according the following relationship:
##EQU00014##
As a result, the voltage level of node VSUM is set by the selection
of the sizes and properties of the devices involved in constants
K.sub.1-K.sub.3. The voltage at node OUT is set to V.sub.CC/2 in
the depicted circuit when the voltage at VSUM is equal to
V.sub.CC/2, and the power supply voltage V.sub.CC is equal to the
selected or threshold voltage. If the current from transistors T1
and T2 is less than the current from transistors T3 and T4, the
voltage at node OUT will swing up to that of power supply voltage
V.sub.CC. This situation occurs when the power supply voltage
V.sub.CC is greater than the selected voltage. On the other hand,
if the current from transistors T1 and T2 is greater than the
current from transistors T3 and T4, the voltage at node OUT will
swing down to that of power supply voltage GND. This situation
occurs when the power supply voltage V.sub.CC is less than the
selected or threshold voltage.
The threshold voltage may be set at a value slightly less than the
desired power supply voltage according to the present invention.
For example, in a five volt power supply system, the threshold
voltage may be set at 4.8 volts such that when the power supply is
at 5 volts, the output at node OUT will swing up to power supply
voltage V.sub.CC, 5 volts. If the power supply voltage drops below
4.8 volts, the output node OUT will swing down to the ground power
supply voltage. Thus, through the selection of constants
K.sub.1-K.sub.3, a voltage may be selected, wherein fluctuations of
the power supply voltage V.sub.CC below the selected voltage will
cause the comparator to indicate that a secondary or backup power
supply should be switched to the circuit associated with the
comparator.
The MOSFETs used in the current mirrors in the depicted circuit may
have longer channels than the base technology. For example, in a
0.8 micron device, the transistors used in the current mirrors may
have channel lengths from 3 to 6 microns. These longer channels may
be used improve the precision of the current supplied by the
current mirrors.
The scaling of currents in current mirrors A-D may be done in a
variety of ways. In accordance with a preferred embodiment of the
present invention, one of the transistors is selected as unity. A
transistor that is to provide a current N times the current of the
unity transistor is replaced with N unity transistors connected in
parallel. Those of ordinary skill in the art will realize other
methods of scaling currents may be employed.
Next, the value of the resistors must match preset ratios when
specified, but the actual magnitude of the resistors affects only
the power consumption of the circuit.
Current mirrors A-D in FIG. 1 are an example of one layout of a
DCSBV comparator in accordance with a preferred embodiment of the
present invention. Other configurations for the current mirrors
will be apparent to those of ordinary skill in the art. Other
numbers of current mirror layouts may be employed to satisfy
equation (1).
Referring next to FIG. 3, a schematic diagram of a DCSBV comparator
is illustrated. This comparator is similar to the comparator
depicted in FIG. 1 with a few additional circuits. Drain impedance
of the current sources may limit the voltage swing in some cases in
which the current is limited to low or small changes. Additionally,
small current changes may have problems in driving the node
capacitance at node VSUM, resulting in a slow response.
To solve these problems, a cascode stage 24, well known to those of
ordinary skill in the art, may be added the DCSBV comparator
between the current sources and node VSUM, as depicted in FIG. 2,
to improve the switching speed of the circuit. Cascode stage 24
includes transistors E1-E6 and resistor R.sub.x. Transistors E1-E3
are p-channel MOSFETs, while transistors E4-E6 are n-channel
MOSFETs. Transistor E2 has its source connected to power supply
voltage V.sub.CC, while transistor E6 has its source connected to
power supply voltage GND. Transistor E1 has its source connected to
the drains of transistors T3 and T4; transistor E4 has its source
connected to the drains of transistor T1 and T2. Transistors E1 and
E4 have their drains connected to node VSUM.
In some instances, a selected voltage swing having a range other
than that between the power supply voltage V.sub.CC and power
supply voltage GND may be desired. A clamping circuit 26, well
known to those of ordinary skill in the art, may be added to
provide a bias to set the voltage swing at node VSUM between
selected or preset voltages. Clamping circuit 26 includes
transistors D1-D4 and inverter 30. Transistors D1 and D2 are
n-channel MOSFETs, while transistors D3 and D4 are p-channel
MOSFETs. Transistors D1 and D2 have their drains connected to power
supply voltage V.sub.CC; transistors D3 and D4 have their drains
connected to ground power supply voltage GND. The sources of
transistors D2 and D3 are connected to node VBUM. Other clamping
circuits other than the one depicted also may be used with the
comparator of the present invention.
In addition, a hysteresis circuit 28, known to those of ordinary
skill in the art, may be used to reduce the susceptibility of the
comparator to noise from other components. Hysteresis circuit 28
includes transistors H1-H3. Transistors H1 and H2 are p-channel
MOSFETs, and transistor H3 is an n-channel MOSFET. Transistor H1
has its source connected to power supply voltage V.sub.CC. The gate
of transistor H1 is connected to the gate and source of transistor
M16. The gate of transistor H2 is controlled by the output of
inverter 34; the gate of transistor H3 is controlled by the output
of inverter 32. Inverters 32 and 33 are the same as inverters 10
and 12.
As a result, a DCSBV comparator provides an indicator for switching
between a primary and secondary power supply without requiring a
large number of devices for implementation as compared to a typical
bandgap reference circuit. The present invention eliminates the
need for using a large number of bipolar devices, large resistors,
oscillators, switch capacitors, auto zero devices, etc. Through the
use of current mirrors, the number of bipolar devices required are
reduced. Additionally, sensitivity to noise also may be reduced by
using a DCSBV comparator according to the present invention.
Although the depicted embodiment employs for current mirrors, other
numbers of current mirrors and current mirrors of other designs may
be used as long as the implementation of the current mirrors
performs the function of summing currents at a node. Additionally,
more than one node may be used for summing currents.
An example of typical values which can be used to fabricate an
operational device are as follows. These numbers assume a typical
processing technology, and a desired trip point for the comparator
of approximately 4.4 volts. The constants K.sub.1, K.sub.2, and
K.sub.3, respectively, can be set to the values 2, 7, and 46 by
proper selection of the various components and transistor sizes.
Transistor design to give current densities of J.sub.1=1.0
A/cm.sup.2 and J.sub.2=0.05 A/cm.sup.2 provides for operation as
described above.
While the invention has been particularly shown and described with
reference to a preferred embodiment, it will be understood by those
skilled in the art that various changes in form and detail may be
made therein without departing from the spirit and scope of the
invention.
* * * * *