U.S. patent number RE36,916 [Application Number 09/064,348] was granted by the patent office on 2000-10-17 for apparatus for stacking semiconductor chips.
This patent grant is currently assigned to Simple Technology Incorporated. Invention is credited to Mark Moshayedi.
United States Patent |
RE36,916 |
Moshayedi |
October 17, 2000 |
Apparatus for stacking semiconductor chips
Abstract
A multi-chip memory module comprises multiple standard,
surface-mount-type memory chips stacked on top of each other, and a
pair of printed circuit boards mounted on opposite sides of the
memory chips to electrically interconnect the memory chips. Each
printed circuit board has vias that are positioned to form multiple
rows, with each row of vias used to connect the printed circuit
board to a respective memory chip. The vias falling along the
bottom-most row of each printed circuit board are also exposed and
are used to surface mount the multi-chip module to pads of a memory
board.
Inventors: |
Moshayedi; Mark (Orange,
CA) |
Assignee: |
Simple Technology Incorporated
(Santa Ana, CA)
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Family
ID: |
23616743 |
Appl.
No.: |
09/064,348 |
Filed: |
April 22, 1998 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
Reissue of: |
408552 |
Mar 21, 1995 |
05514907 |
May 7, 1996 |
|
|
Current U.S.
Class: |
257/723; 174/541;
257/685; 257/686; 257/698; 257/724; 361/735; 361/744; 361/760;
361/790; 439/65; 439/83 |
Current CPC
Class: |
H01L
25/10 (20130101); H01L 25/105 (20130101); H05K
1/145 (20130101); H05K 7/023 (20130101); H01L
2225/1029 (20130101); H01L 2225/107 (20130101); H01L
2225/1005 (20130101); H01L 2924/0002 (20130101); H01L
2924/0002 (20130101); H01L 2924/00 (20130101) |
Current International
Class: |
H01L
25/10 (20060101); H05K 7/02 (20060101); H05K
1/14 (20060101); H01L 023/34 (); H01L 023/02 ();
H01L 023/04 (); H05K 007/00 () |
Field of
Search: |
;257/685,686,723,724
;174/17R ;361/788,790,811,760 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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2 645 681 |
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Oct 1990 |
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FR |
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58-219757 |
|
Dec 1983 |
|
JP |
|
60-160641 |
|
Aug 1985 |
|
JP |
|
60-194548 |
|
Oct 1985 |
|
JP |
|
60-254762 |
|
Dec 1985 |
|
JP |
|
61-63048 |
|
Apr 1986 |
|
JP |
|
61-75558 |
|
Apr 1986 |
|
JP |
|
61-137335 |
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Jun 1986 |
|
JP |
|
2-260448 |
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Oct 1990 |
|
JP |
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3-96266 |
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Apr 1991 |
|
JP |
|
4-209562 |
|
Jul 1992 |
|
JP |
|
7-122842 |
|
May 1995 |
|
JP |
|
Other References
Patent Abstract of Japan, Publication No. 05029534, Published May
2, 1993, Inventor: Nakamura Shigemi, entitled "Memory Module",
European Patent Office. .
"Alternative assembly for memory ICs," XP-002093051, Electronic
Engineering, Jan. 1987, p. 22. .
International Electronic Device Meeting, IEDM Technical Digest,
Washington, D.C., Dec. 6-9, 1987. .
3-D Integrated Packging and Interconnect Technology, Wescon/90
Conference Record, held Nov. 13-15, 1990, Anaheim, CA. .
Tuckerman, D.B. et al., "Laminated Memory: A New 3-Dimensional
Packaging Technology for MCMs" article, nCHIP, Inc., IEEE, 1994.
.
1992 Proceedings, 42nd Electronic Components & Technology
Conference, May 18-20, 1992. .
Dense-Pac Microsystems, 16-Megabit High Speed CMOS SRAM. .
Dense-Pac Microsystems, 128-Megabyte SDRAM Sodimm. .
Dense-Pac Microsystems, 256-Megabyte CMOS DRAM. .
Dense-Pac Microsystems, "While others are still defining it . . .
Our customers are cashing in!" flyer. .
IBM Technical Disclosure Bulletin, Vertical Chip Packaging, vol.
20, No. 11A, Apr. 1978. .
IBM Technical Disclosure Bulletin, Edge-Mounted MLC Packaging
Scheme, vol. 23, No. 12, May 1981. .
IBM Technical Disclosure Bulletin, Process for Producing Lateral
Chip Connectors, vol. 32, No. 3B, Aug. 1989. .
Research Disclosure, Organic Card Device Carrier, 31318, May 1990,
No. 313. .
Dense-Pac Microsystems, "3-D Technology," 1993, 15 pages. .
Dense-Pac MicroSystems, Inc., "Short Form Catalog," 1991, 20 pages.
.
"New levels of hybrid IC density are provided by Three-Dimensional
Packaging" article, 2 pages. .
Dense-Pac MicroSystems, Inc., "Short Order Catalog," 1990, 12
pages. .
Dense-Pac MicroSystems, Inc., "Memory Products--Short Form--Q4,"
1994, 5 pages. .
"Electronic Packaging & Production" article, A Cahners
Publication, Jan. 1992, 2 pages. .
"Introducing a Revolutionary 3 Dimensional Package Type--The SLCC,"
John Forthun, Advancement In Technology, Feb. 26, 1992, 12
pages..
|
Primary Examiner: Saadat; Mahshid
Assistant Examiner: Clark; Jhihan B.
Attorney, Agent or Firm: Knobbe, Martens, Olson & Bear,
LLP
Claims
What is claimed is:
1. A multi-chip memory module, comprising:
a plurality of memory chips stacked on top of one another, each
memory chip of said plurality having conductive surface mount pins;
and
first and second side boards mounted to said memory chips such that
said side boards are substantially parallel to one another, each
side board having:
vias for receiving said surface mount pins of said memory chips,
said vias arranged in rows such that each row corresponds to a
respective memory chip of said plurality, vias of a bottom-most row
receiving surface mount pins of a bottom-most memory chip of said
plurality, said bottom-most row falling along a lower side board
edge such that vias of said bottom-most row serve as surface mount
terminals for surface mounting the multi-chip memory module to pads
of a printed circuit board; and
conductive traces for interconnecting said vias.
2. A multi-chip memory module as defined in claim 1, wherein said
vias of said bottom-most row are exposed along said lower side
board edge.
3. A multi-chip memory module as defined in claim 1, wherein all
memory chips of said plurality are functionally identical.
4. A multi-chip memory module as defined in claim 1, wherein the
total number of surface mount terminals on said first and second
side boards is greater than the number of said surface mount pins
on any one of said plurality memory chips.
5. A multi-chip memory module as defined in claim 1, wherein said
memory chips of said plurality are interconnected by said traces
such that all memory chips of said plurality are selected
simultaneously.
6. A multi-chip memory module as defined in claim 1, in combination
with a memory board having surface mount pads thereon, said vias of
said bottom-most row soldered to said surface mount pads. .[.7. A
module that includes at least one multi-chip module, said module
comprising:
a circuit board having at least first and second sets of surface
mount pads;
a first plane side board including a plurality of surface mount
contacts positioned along an edge of said first side board which
abuts said circuit board, said plurality of surface mount contacts
of said first side board being surface-mounted to said first set of
surface mount pads of said circuit board such that said first side
board is substantially perpendicular to said circuit board;
a second planar side board including a plurality of surface mount
contacts positioned along an edge of said second side board which
abuts said circuit board, said plurality of surface mount contacts
of said second side board being surface-mounted to said second set
of surface mount pads of said circuit board such that said second
side board is substantially perpendicular to said circuit board and
substantially parallel to said first side board; and
a plurality of standard surface mount chips stacked between said
side boards, each chip including a plurality of pins, a portion of
each pin extending beyond a chip surface which lies generally
parallel to said circuit board with said chip positioned between
said side boards, each chip of said plurality conductively
connected to said first side board and
said second side board..].8. A module as defined in claim .[.7.].
.Iadd.12.Iaddend., wherein said first and second sets of surface
mount
pads are arranged in respective first and second rows. 9. A module
as defined in claim .[.7.]. .Iadd.12.Iaddend., wherein a surface
area of a region between said first and second side boards on said
circuit board is generally equal to a surface area occupied by one
of said chips of said
plurality. 10. A module as defined in claim .[.7.].
.Iadd.12.Iaddend., wherein said standard surface mount chips of
said plurality are stacked on
top of one another. 11. A module as defined in claim .[.7.].
.Iadd.12.Iaddend., wherein all chips of said plurality are
functionally
identical. 12. A module .[.as defined in claim 7,.]. .Iadd.that
includes
at least one multi-chip module, said module comprising:
a circuit board having at least first and second sets of surface
mount pads;
a first planar side board including a plurality of surface mount
contacts positioned along an edge of said first side board which
abuts said circuit board, said plurality of surface mount contacts
of said first side boards being surface-mounted to said first set
of surface mount pads of said circuit board such that said first
side board is substantially perpendicular to said circuit
board;
a second planar side board including a plurality of surface mount
contacts positioned along an edge of said second side board which
abuts said circuit board, said plurality of surface mount contacts
of said second side board being surface-mounted to said second set
of surface mount pads of said circuit board such that said second
side board is substantially perpendicular to said circuit board and
substantially parallel to said first side board; and
a plurality of standard surface mount chips stacked between said
side boards, each chip including a plurality of pins, a portion of
each pin extending beyond a chip surface which lies generally
parallel to said circuit board with said chip positioned between
said side boards, each chip of said plurality conductively
connected to said first side board and said second board,
.Iaddend.wherein a lower-most chip of said plurality is
soldered to said first and second sets of surface mount pads. 13. A
module as defined in claim .[.7.]. .Iadd.12.Iaddend., wherein each
chip of said
plurality is a memory chip. 14. A module as defined in claim 12,
wherein said lower-most chip is additionally soldered to vias of
said first and
second side boards. 15. A module as defined in claim 14, wherein
said lower-most chip is soldered to said vias with a first solder
that has a first melting point, and is soldered to said first and
second sets of surface mount pads with a second solder that has a
second melting point, said second melting point lower than said
first melting point. .Iadd.16. A module as defined in claim 12,
wherein each surface mount contact of the first and second side
boards is formed by a solder joint, and at least a portion of each
solder joint extends below a lower edge of the respective side
board. .Iaddend..Iadd.17. A low profile multi-chip module for
mounting on a circuit board substrate, comprising:
first and second support structures, each support structure
including a plurality of electrically conductive paths and a
plurality of surface mount contacts positioned along an edge
thereof, the plurality of surface mount contacts arranged to align
with corresponding surface mount pads on the circuit board
substrate to electrically couple the first and second support
structures to the circuit board substrate; and
at least first and second juxtaposed standard surface mount chips,
the first and second chips being identical to each other, each chip
having planar surfaces extending between at least a pair of
opposing sides of the chip, the planar surfaces arranged generally
between the support structures with the planar surfaces of adjacent
chips positioned face to face, the opposite sides of each chip
having a respective set of identical pins extending beyond the side
of the chip toward respective ones of the support structures, at
least some of each set of pins being electrically connected to
respective ones of the support structures, the pins of the
lower-most chip being disposed relative to the edges of the first
and second support structures such that when the multi-chip module
is surface mounted to the circuit board substrate the two sets of
pins of the lower-most chip are soldered directly to the surface
mount contacts of the first and second support structures,
respectively, and to the circuit board substrate.
.Iaddend..Iadd.18. The multi-chip module of claim 17, wherein the
juxtaposed standard surface mount chips are interconnected by the
plurality of electrically conductive paths such that all of the
juxtaposed standard surface mount chips may be selected
simultaneously. .Iaddend..Iadd.19. The multi-chip module of claim
17, wherein the electrical conductive paths are electrically
coupled to at least some of the pins of the juxtaposed standard
surface mount chips and are arranged so as to individually select
at least one the juxtaposed standard surface mount chips.
.Iaddend..Iadd.20. The multi-chip module of claim 17, wherein a
total number of the surface mount contacts is greater than the
total number of pins of the first chip. .Iaddend..Iadd.21. The
multi-chip module of claim 17, wherein at least some of the pins of
the juxtaposed standard surface mount chips are mechanically
connected to one of the support structures. .Iaddend..Iadd.22. The
multi-chip module of claim 17, wherein at least some of the pins of
the juxtaposed standard surface mount chips are solder connected to
one of the support structures so as to mechanically and
electrically connect the pins to the support structures.
.Iaddend..Iadd.23. The multi-chip module of claim 17, wherein all
of the juxtaposed standard surface mount chips of the module are
positioned to lie entirely between the first and second support
structures. .Iaddend..Iadd.24. The multi-chip module of claim 17,
wherein at least corresponding portions of the first and second
support structures lie generally parallel to each other.
.Iaddend..Iadd.25. The multi-chip module of claim 17, wherein the
first standard surface mount chip is aligned above the second
standard surface mount chip. .Iaddend..Iadd.26. The multi-chip
module of claim 17, wherein the first and second support structures
comprise opposing inner surfaces, and the pins of the juxtaposed
standard surface mount chips extend outward beyond the inner
surfaces of the first and second support structures.
.Iaddend..Iadd.27. The multi-chip module of claim 17, wherein the
first and second support structures are spaced apart from each
other by a distance less than a distance between an outer end of a
first pin on one side of the first standard surface mount chip and
an outer end of a second pin on an opposite side of the first
standard surface mount chip.
.Iaddend..Iadd. The multi-chip module of claim 17, wherein said
planar surfaces of each chip lie generally within respective
parallel planes, and each pin of at least one of the chips connects
to the corresponding support structure at a location outside the
space between the plane. .Iaddend..Iadd.29. The multi-chip module
of claim 24, wherein the first and second support structures
comprise planar side boards. .Iaddend..Iadd.30. The multi-chip
module of claim 24, wherein each of the first and second support
structures extends along at least a side of one of the plurality of
juxtaposed standard surface mount chips. .Iaddend..Iadd.31. The
multi-chip module of claim 30, wherein each support structure is
formed of a unitary piece of printed circuit board material.
.Iaddend..Iadd.32. The multi-chip module of claim 30, wherein the
planar surfaces of each chip lie generally normal to the parallel
corresponding portions of the first and second support structures.
.Iaddend..Iadd.33. The multi-chip module of claim 26, wherein said
first and second support structures each include a plurality of
vias that are arranged to receive
at least outer ends of at least some of the pins.
.Iaddend..Iadd.34. A low profile memory module comprising:
a memory board having at least a pair of surface mount pads;
and
at least one multi-chip module comprising a circuit board structure
on the memory board and at least two identical, standard surface
mount memory chips, each chip having a plurality of substantially
identical pins extending outwardly from the respective chip, the
chips being stacked one above the other with corresponding pins of
two chips positioned above each other generally in vertical
alignment, the corresponding pins which are in general vertical
alignment being separated by solder, metal contacts and a portion
of the circuit board structure, the portion of the circuit board
structure having metal contacts on each side and the solder
connecting each metal contact to an adjacent pin of a corresponding
one of the chips, the pins of a lower-most one of the chips being
soldered to the surface mount pads of the memory board and being
soldered to metal contacts along a bottom side of the circuit board
structure such that with the multi-chip module surface mounted onto
the memory board the pins of the lower-most one of the chips are
disposed between the circuit board structure and the
memory board. .Iaddend..Iadd.35. A module as defined in claim 34,
wherein the circuit board structure includes an interconnecting
conductive path electrically connecting together the metal
contacts. .Iaddend..Iadd.36. A module as defined in claim 34,
wherein the portion of the circuit board structure between the
metal contacts has a generally rectangular cross-sectional shape.
.Iaddend..Iadd.37. A low profile multi-chip memory module having
surface mount contacts for surface mounting to surface mount pads
of a memory board, the memory module comprising:
at least two identical, standard surface mount memory chips stacked
one above the other, each chip having a plurality of identical pins
extending outwardly from the respective chip; and
at least one circuit board structure including a plurality of
electrically conductive paths and a plurality of surface mount
contacts positioned along a bottom edge of the circuit board
structure, the plurality of surface mount contacts aligned to align
with corresponding surface mount pads on the memory board to
electrically couple the circuit board structure to the memory
board, the circuit board structure being electrically connected to
at least some of the pins of the chips, each surface mount contact
being formed by solder and one of the pins of a bottom one of the
memory chips, said surface mount contacts extending below the
bottom edge of the circuit board structure. .Iaddend..Iadd.38. A
module as defined in claim 37, wherein each chip includes a pair of
opposing sides with the pins extending from both sides, and the
circuit board structure supports the pins on both sides of the
chips.
.Iaddend..Iadd.39. A module as defined in claim 37, wherein the
circuit board structure includes a first circuit board side element
and a second circuit board side element, each side element
extending along a side of at least the bottom one of the chips and
supporting a set of pins that extend from the respective side of an
upper one of the chips, and each side element includes some of the
plurality of electrically conductive paths and some of the
plurality of surface mount contacts that are arranged along a lower
edge of the respective side element. .Iaddend..Iadd.40. A module as
defined in claim 39, wherein each side element has a generally
uniform rectangular cross-sectional shape. .Iaddend..Iadd.41. A
module as defined in claim 37, wherein the total number of surface
mount contacts on the circuit board structure is greater than the
number of the plurality of pins on any one of the standard surface
mount chips. .Iaddend..Iadd.42. A module as defined in claim 37,
wherein the circuit board structure is formed of a unitary piece of
printed circuit board material. .Iaddend..Iadd.43. A module as
defined in claim 37, additionally comprising a second circuit board
structure including a plurality of electrically conductive paths
and a plurality of surface mount contacts positioned along at least
one edge of the second circuit board structure, the plurality of
surface mount contacts arranged to align with corresponding surface
mount pads on the memory board to electrically couple the second
circuit board structure to the memory board, the second circuit
board structure being electrically connected to at least some
of
the pins of the chips. .Iaddend..Iadd.44. A module as defined in
claim 37, wherein each chip has planar surfaces that extend between
at least a pair of opposing sides of the chip, and the chips are
arranged in the module with the planar surfaces of adjacent chips
positioned face to face. .Iaddend..Iadd.45. A module as defined in
claim 42, wherein the circuit board structure has a generally
uniform rectangular cross-sectional shape. .Iaddend.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the vertical stacking of
conventional integrated circuit packages to increase the density of
components on a printed circuit board. More particularly, the
present invention relates to the vertical stacking of conventional
memory integrated circuits packages on a surface mount printed
circuit board.
2. Description of the Related Art
An integrated circuit or "IC" is a microcircuit formed from active
and passive electrical components interconnected on or within a
single semiconductor substrate. To protect the IC and to facilitate
connection of the IC to a printed circuit board, off-the-shelf ICs
are commonly packaged within a ceramic, plastic or epoxy IC package
having multiple external terminals or "pins." The full integrated
circuit package, including the IC, is commonly referred to (and
will be referred to herein) as a "chip."
As a result of the continuously increasing demand for large random
access computer memories, and the demand for smaller computers,
various techniques have been developed to increase densities of
memory chips on printed circuit boards. In addition to the inherent
size advantages provided, increased chip densities enable shorter
circuit paths between components, allowing the components to
operate at higher speeds while reducing radio-frequency
interference (RFI) and electromagnetic interference (EMI) emitted
from the printed circuit board.
One development that has led to a significant increase in memory
chip densities has been the advent of surface mount technology.
With surface mount technology, conventional plated through holes on
printed circuit boards are replaced with conductive pads, and
through-hole pins of conventional chips are replaced with smaller
surface mount pins. Because the pitch or spacing between centers of
adjacent surface mount pins is significantly less than the
conventional 0.10-inch spacing for conventional through-hole
components, surface mount chips tend to be considerably smaller
than corresponding conventional chips, and thus take up less space
on the printed circuit board. Surface mount technology additionally
facilitates the mounting of components on both sides of the printed
circuit board.
Various techniques have been developed for increasing chip
densities on printed circuit boards by vertically stacking or
"piggybacking" two or more chips. See, for example, U.S. Pat. No.
4,996,583 to Hatada, U.S. Pat. No. 4,398,235 to Lutz et al., U.S.
Pat. No. 4,953,005 to Carlson et al., Japanese Patent Publication
No. 61-63048 to Toshiba Corp., Japanese Patent Publication No.
58-219757 to Tokyo Shibaura Denki K. K., Japanese Patent
Publication No. 61-75558 to NEC Corp., and Japanese Patent
Publication No. 60-254762 to Fujitsu. These techniques, however,
tend to suffer from a number of defects. For instance, many of the
techniques require the manufacture of custom chips that are
specifically designed for stacking, or else require special
modifications to the pins of standard memory chips. Further, many
of the techniques do not make use of the various advantages of
surface mount technology, such as the ability to maintain a
low-profile when memory chips are mounted to the printed circuit
board. Further, many proposed techniques for stacking memory chips
are not cost effective.
SUMMARY OF THE INVENTION
The present invention involves a multi-chip memory module having
two or more vertically stacked memory chips that are interconnected
using a pair of printed circuit boards or "side boards." The
multi-chip memory module can be constructed using standard,
off-the-shelf memory chips, without modification to the pins of the
memory chips. The multi-chip memory module is constructed such that
pins of the lower-most memory chip in the stack are
surface-mountable directly to pads of a memory board, permitting
the multi-chip memory module to be mounted with a low profile
relative to the memory board.
In accordance with one aspect of the invention, the multi-chip
memory module comprises a plurality of memory chips that are
stacked on top of one another, with each memory chip having
conductive surface mount pins. First and second side boards are
mounted to the stacked memory chips such that the side boards are
substantially parallel to one another. Each of the two side boards
has vias for receiving the surface mount pins of the memory chips,
with the vias arranged in rows such that each row corresponds to a
respective memory chip. Vias of a bottom-most row of each side
board fall along a lower side board edge, so that vias of the
bottom-most row serve as surface mount terminals for surface
mounting the multi-chip memory module to pads of a printed circuit
board. Conductive traces are provided on or within each side board
for interconnecting the surface mount pins of the memory chips.
In accordance with another aspect of the invention, there is
provided a memory module that includes at least one multi-chip
module. The memory module includes a circuit board having at least
first and second sets of surface mount pads. The memory module
further includes a first side board that is surface-mounted to the
first set of surface mount pads such that the first side board is
substantially perpendicular to the circuit board, and a second side
board that is surface-mounted to the second set of surface mount
pads such that the second side board is substantially perpendicular
to the circuit board and substantially parallel to the first side
board. The memory module further includes a plurality of chips
stacked on top of one another between the side boards, with each
chip conductively connected to the first and second side
boards.
In accordance with an additional aspect of the invention, there is
provided a method of increasing the density of memory chips on a
memory board. The method includes the step of providing first and
second side boards, with each side board comprising a printed
circuit board having vias thereon, and with vias along bottom edges
of the side boards forming surface mount terminals. The method
further includes the step of stacking a plurality of memory chips
on top of one another to generate a stack of memory chips. The
method further includes the steps of positioning the first and
second side boards relative to the stack of memory chips such that
terminals of the memory chips extend within the vias, and attaching
the first and second side boards to the stack of memory chips by
filling the vias with solder.
In accordance with another aspect of the invention, there is
provided a method of interconnecting circuit board components to
increase component density. The method includes the step of
constructing a first printed circuit board that has a plurality of
vias formed along a row. The method further includes the step of
cutting the first printed circuit board along the row to expose the
vias along an edge of the printed circuit board. The method further
includes the steps of soldering the vias to respective pins of a
semiconductor chip, and soldering the vias to pads of a second
printed circuit board such that the first printed circuit board is
substantially perpendicular to the second printed circuit
board.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other features of the invention will now be described
with reference to the drawings of a preferred embodiment, which is
intended to illustrate and not to limit the invention, and in
which:
FIG. 1 is a perspective view illustrating a multi-chip memory
module in accordance with a preferred embodiment of the present
invention, illustrated above a portion of a printed circuit board
to which the multi-chip memory module may be surface mounted.
Solder plugs and circuit board traces are omitted to show the
construction of the multi-chip memory module;
FIG. 2 is an exploded perspective view of the multi-chip memory
module of FIG. 1;
FIG. 3 is a top plan view of the multi-chip memory module of FIG.
1, with terminal numbers for the multi-chip memory module shown in
brackets;
FIG. 4 is a cross sectional view taken along the line 4--4 of FIG.
1;
FIGS. 5a and 5b are top and bottom plan views of a portion of a
circuit board panel, illustrating a process of manufacturing side
boards in accordance with the present invention, and further
illustrating conductive traces on first and second sides of the
side boards of FIG 1;
FIG. 6a is an enlarged view in partial cross section, showing a
bottom portion of a side board of the multi-chip memory module of
FIG. 1 with partially cut-away vias filled with solder to form
surface mount terminals, and further showing the printed circuit
board and pads of FIG. 1;
FIG. 6b is an enlarged view in partial cross section of a side
board and a printed circuit board with pads, illustrating an
alternative configuration that results when conductive cylinders of
vias are pushed inward during a routing process;
FIG. 7 is a schematic diagram illustrating the electrical
interconnections of memory chip pins and side board terminals for
the multi-chip memory module of FIG. 1, with chip pin numbers shown
in parenthesis and multi-chip memory module terminal numbers shown
in brackets; and
FIG. 8 is a plan view of a single in-line memory module having
eight multi-chip memory modules surface mounted to one side
thereof.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
In accordance with one embodiment of the present invention, one
multi-chip memory module design is described herein. In order to
fully specify this
preferred design, various embodiment-specific details are set
forth, such as the number of memory chips in the module, the
layouts of the printed circuit boards of the module, and the
capacity, number of data bits and pin-outs of the memory chips. It
should be understood, however, that these details are provided only
to illustrate this single preferred embodiment, and are not
intended to limit the scope of the present invention.
With reference to FIGS. 1-4, a 28-terminal multi-chip memory module
30 (hereinafter "multi-chip module") comprises four
functionally-identical, vertically-stacked memory chips 32, 34, 36,
38. The memory chips 32-38 are conventional 24-pin surface mount
TSOP ("thin small outline package") chips, available from Toshiba,
Mitsubishi, and the like. Each memory chip 32-38 has a capacity of
16M.times.1-bit.
The vertically-stacked memory chips 32-38 are held together and
electrically interconnected by a pair of printed circuit boards 42,
44, referred to herein as "side boards." The side boards 42, 44 are
positioned in parallel to each other, and perpendicular to the top
surfaces of the chips 32-38. The multi-chip module 30 is configured
to be surface-mounted to a memory board 70 (FIG. 1) that has
surface mount pads 66 thereon.
As used herein to describe the multi-chip module 30, the term
"bottom" refers generally to the portion of the multi-chip module
30 that is closest to the memory board 70 when the multi-chip
module 30 is mounted to the memory board 70. The terms "top,"
"bottom," and "lower" are not intended to imply a specific spacial
orientation of the multi-chip module 30.
Each side board 42, 44 has a plurality of plated through-holes or
"vias" 48 for receiving the pins 50 of the chips 32-38, with each
via 48 comprising a conductive tubular cylinder portion 48a that
extends through the side board. The vias 48 are positioned to form
four horizontal rows 52, 54, 56, 58, with each row corresponding to
a respective memory chip 32, 34, 36, 38. With reference to FIG. 4,
the rows 52-58 of vias are formed such that the distance D between
centers of adjacent rows is approximately equal to the thickness T
of each chip 32-38, so that adjacent memory chips are touching (or
nearly touching) each other when the multi-chip module 30 is
assembled. This close spacing of adjacent memory chips contributes
to a low profile of the multi-chip module 30 relative to the memory
board 70 (FIG. 1), as further discussed below. Adjacent memory
chips could alternatively be spaced apart from one another, as may
be desirable in certain applications to facilitate the cooling of
the memory chips 32-38.
With reference to FIGS. 1 and 2, for each side board 42, 44, the
vias of the bottom-most row 58 are partially cut away, with the
conductive cylinder 48a of each such via extending to the lower
edge 80 of the side board so that the pins 50 of the bottom-most
chip 38 can be soldered directly to the surface mount pads 66 (FIG.
1) of the memory board 70. The vias 48 along the lower edges 80 of
the side boards 42, 44 thus serve as surface mount terminals. This
aspect of the multi-chip module 30, in combination with the close
spacings between adjacent memory chips, allows the multi-chip
module 30 to be mounted with a very low profile relative to the
memory board 70. The lower edge 80 is preferably formed using a
routing machine, as further described below. As illustrated in FIG.
3, the multi-chip module 30 has a total of 28 surface mount
terminals (terminal numbers shown in brackets), with the terminals
arranged in two rows of 14 terminals each.
With reference to FIG. 1, the surface mount pads 66 are arranged in
two rows of 14 pads each (corresponding to the 14 terminals per
side board 42, 44), with the distance between the two rows
corresponding to the width of each chip 32--38. As best seen in
FIGS. 1 and 3, the multi-chip module 30 occupies approximately the
same area on the memory board 70 as would a single one of the
memory chips 32-38.
Conductive traces (shown in FIGS. 5a and 5b) of the side boards 42,
44 interconnect the pins 50 of the memory chips 32-38 such that all
memory locations of all memory chips 32-38 can be utilized. In the
embodiment shown, the memory chips 32-38 are interconnected such
that all four 16M.times. 1-bit chips 32-38 are selected
simultaneously, with each chip supplying (or, during a write cycle,
storing) one bit of data. The multi-chip module 30 thus acts as a
16M.times.4-bit memory module.
With reference to FIGS. 1-3, four "extra" vias 72 are provided
along the lower edges 80 of the multi-chip module 30. The four vias
72 serve as terminals only, and do not receive pins 50 of any of
the memory chips 32-38. Each via 72 provides access to either a
data input pin or a data output pin of a respective memory chip
32-38, and is thus dedicated to a single chip. It will be
recognized that other types of terminal structures could be used in
place of the vias 72.
To assemble the multi-chip module 30, the memory chips 32-38 are
initially stacked on top of one another. The side boards 42, 44 are
then positioned so that the pins 50 extend within the corresponding
vias, as best shown by FIG. 4. Advantageously, no modification to
the pins 50 of the standard TSOP memory chips 32-38 is required.
Once the side boards 42, 44 are properly positioned, all of the
vias 48 of both side boards 42, 44 are filled with solder (solder
plugs omitted in FIGS. 1-4). A solder with a relatively high
melting point is used for this purpose so that the multi-chip
module 30 can subsequently be mounted to the memory board 70 using
a solder with a lower melting point without melting the solder
within the vias 48.
A preferred process for manufacturing the side boards 42, 44 of the
multi-chip module 30 will now be described with reference to FIGS.
5a and 5b, which illustrate a circuit board panel 90 mid-way
through the manufacturing process. FIG. 5a illustrates the
outward-facing surface (relative to the multi-chip module 30) of
the side board 42, and the inward-facing surface of the side board
44. FIG. 5b illustrates the inward-facing surface of the side board
42, and the outward-facing surface of the side board 44.
Traces 92 are initially formed on both sides of the circuit board
panel 90 using a conventional film etching process. Via holes are
then drilled through the circuit board panel 90, with the holes
positioned to correspond to the pin positions of the chips 32-38. A
conventional plating process is then used to form the conductive
cylinders 48a of the vias 48 (preferably formed from copper), and
to interconnect the via cylinders 48a to the appropriate traces
92.
Once the vias 48 and traces 92 are formed, the panel 90 is routed
to form the lower edge 80 and the top edge 81 of each side board
42, 44. The panel 90 shown in FIGS. 5a and 5b is mid-way through
the routing process, with top and bottom edges 80, 81 formed only
for the four side boards 42, 44 closest to the bottom of each
Figure. During the routing process, the routing bit is preferably
passed so that approximately 5% of the diameter of each via
cylinder 48a along the bottom row 58 is cut away. Due to
imperfections in the routing process, the lower portions of some
cylinders may be pushed inward (toward the centers of the
respective vias) by the routing bit, as schematically shown at 96
in FIGS. 5a and 5b (and further illustrated in FIG. 6b). Cylinders
that are formed in this manner have been found to work well as
surface mount terminals, and need not be modified.
The panel 90 is scored on both sides to form break-away grooves 94.
The break-away grooves 94 can be formed either before or after the
above-described routing process. Finally, side boards 42, 44 are
manually broken away from the panel 90, and soldered to stacks of
memory chips (as described above) to form multi-chip modules
30.
With reference to FIG. 6a, once the partially cut-away vias 48
along the bottom edge 80 of a side board 42, 44 are filled with
solder, a portion of each solder plug 98 is exposed along the
bottom edge 80, forming a terminal that can be soldered to a
corresponding surface mount pad 66. Each solder plug 98 preferably
extends slightly below the lower edge 80, facilitating connection
of the multi-chip module 30 to the pads 66. As illustrated in FIG.
6b, via cylinders 48a that are pushed inward during the routing
process are similarly exposed along the lower edge 80, and are
well-suited for connection to the pads 66.
FIG. 7 illustrates the interconnections the memory chips 32-38 of
the multi-chip module 30, and also illustrates the connections
between the memory chips 32-38 and the 28 terminals of the
multi-chip module 30. Signal names for each of the 28
multi-multi-chip module terminals are shown at the left of FIG. 7.
Terminal numbers for the multi-chip module 30 are shown in brackets
in FIG. 7, and correspond to the bracketed terminal numbers of FIG.
3. Pin numbers for the chips 32-38 are shown in parenthesis in FIG.
6. As shown, like address pins (A0-A11), control pins (RAS, CAS and
WE), and power pins (VCC and VSS) of the four memory chips 32-38
are connected together, and are connected to respective terminals
of the multi-chip module 30. For example, the A0 pins (pin 8) of
all four memory chips 32-38 are connected together, and are
accessed via terminal 10 of the multi-chip module. With like
address and control pins connected together, all four chips 32-38
are selected simultaneously, and are fed identical address values.
The data-input pin (D) of each memory chip 32-38 is connected to a
respective dedicated input terminal (D0-D3) of the multi-chip
module 30, allowing a 4-bit value to be written to the multi-chip
module 30 on each write cycle. Similarly, the data-output pin (Q)
of each memory chip 32-38 is connected to a respective dedicated
output terminal (Q0-Q3), allowing a 4-bit value to be read from to
the multi-chip module 30 on each read cycle. As will be recognized,
the chips 32-38 could alternatively be connected such that fewer
than all of the chips are selected with each multi-chip module
access. For example, a 64M.times.4-bit multi-chip can be
constructed from four 16M.times.4-bit memory chips that are
interconnected so that only one memory chip is selected at a time.
In such an arrangement, the write enable pins and like address,
data-in, and data-out pins of all four memory chips would be
connected, and the RAS and CAS pins of each chip would be connected
to dedicated RAS and CAS input lines (i.e., one pair of RAS/CAS
input lines per memory chip).
FIG. 8 illustrates one side of a 16M.times.36 bit single in-line
memory module (SIMM) 100 in accordance with the present invention.
The SIMM 100 comprises a SIMM board 170 having eight 16M.times.4
bit multi-chip modules 30a-30h mounted on the side shown. Four
16M.times.1-bit TSOP memory chips (not shown) are mounted on the
opposite side of the SIMM board 170, in addition to one or more
conventional buffer chips. Standard connector terminals 104 are
provided along the bottom edge of the SIMM 100, permitting
insertion of the SIMM into a connector slot. The eight
16M.times.4-bit multi-chip modules 30a-30h and four 16M.times.1-bit
memory chips combine to produce a data width of 36 bits (32 data
bits plus 4 error-correction code bits). The low profile of each
multi-chip module 30a-30h advantageously enables multiple SIMMs to
be mounted in close proximity to one another within a computer.
While the design of a single multi-chip module 30 has been
described in detail herein, various modifications to the design are
possible without departing from the scope of the present invention.
For example, a different type of memory chip can be used in the
place of the 16M.times.1-bit chips 32-38 of the multi-chip module
30. Alternatively, a mixture of memory chips of different types can
be used. Further, a different number of chips per multi-chip module
can be used. Further, the side boards 42, 44 may be constructed
according to alternative techniques that are apparent to those
skilled in the art.
It will further be noted that the stacking techniques described
herein may be useful in alternative applications that do not
involve the stacking of memory chips. For example, the stacking
techniques could be used to stack multiple buffer chips, or to
stack multiple logic driver chips.
Accordingly, the scope of the present invention is intended to be
defined only by reference to the appended claims.
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