Electronics enclosure
Moore , et al. October 11, 2
U.S. patent number D768,585 [Application Number D/511,819] was granted by the patent office on 2016-10-11 for electronics enclosure. This patent grant is currently assigned to GENERAL ELECTRIC COMPANY. The grantee listed for this patent is General Electric Company. Invention is credited to Robert Earl Grubbs, Dennis Brian King, Alan Carroll Lovell, Christopher Todd Moore.
| United States Patent | D768,585 |
| Moore , et al. | October 11, 2016 |
Electronics enclosure
Claims
CLAIM The ornamental design for an electronics enclosure, as shown and described.
| Inventors: | Moore; Christopher Todd (Troutville, VA), King; Dennis Brian (Salem, VA), Grubbs; Robert Earl (Salem, VA), Lovell; Alan Carroll (Salem, VA) | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Applicant: |
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| Assignee: | GENERAL ELECTRIC COMPANY
(Schenectady, NY) |
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| Appl. No.: | D/511,819 | ||||||||||
| Filed: | December 15, 2014 |
| Current U.S. Class: | D13/184 |
| Current International Class: | 1399 |
| Field of Search: | ;200/51.05 ;D13/101,110,118,122,123,162,197,184,199 ;307/150-152,9.1 ;361/600,601,622,702,703,730,796,809 ;363/141,142 ;385/135 ;D14/188 |
References Cited [Referenced By]
U.S. Patent Documents
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| 3573708 | April 1971 | Yarrick |
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| D747683 | January 2016 | Krivonak |
| 2005/0175307 | August 2005 | Battey |
Assistant Examiner: Blackwell, II; Harold
Attorney, Agent or Firm: GE Global Patent Operation
Description
FIG. 1 is a top, front, left perspective view of our design for an electronics enclosure;
FIG. 2 is a top plan view of our design in FIG. 1;
FIG. 3 is a bottom plan view of our design in FIG. 1;
FIG. 4 is a front elevation view of our design in FIG. 1;
FIG. 5 is a rear elevation view of our design in FIG. 1;
FIG. 6 is a left side elevation view of our design in FIG. 1; and,
FIG. 7 is a right side elevation view of our design in FIG. 1.
In Figures 1-7, the broken lines are directed to environment, and are for illustrative purposes.
The broken lines in the drawings illustrate portions of an electronics enclosure which form no part of the claimed design.
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