Electronic device

Description

FIG. 1 is a perspective view illustrating an electronic device design according to one embodiment;

FIG. 2 is a front view illustrating an electronic device design according to one embodiment;

FIG. 3 is a back view illustrating an electronic device design according to one embodiment;

FIG. 4 is a side view illustrating an electronic device design according to one embodiment;

FIG. 5 is another side view illustrating an electronic device design according to one embodiment;

FIG. 6 is a top view illustrating an electronic device design according to one embodiment;

FIG. 7 is a bottom view illustrating an electronic device design according to one embodiment;

FIG. 8 is a perspective view illustrating an electronic device design according to one embodiment;

FIG. 9 is a front view illustrating an electronic device design according to one embodiment;

FIG. 10 is a back view illustrating an electronic device design according to one embodiment;

FIG. 11 is a side view illustrating an electronic device design according to one embodiment;

FIG. 12 is another side view illustrating an electronic device design according to one embodiment;

FIG. 13 is a top view illustrating an electronic device design according to one embodiment; and,

FIG. 14 is a bottom view illustrating an electronic device design according to one embodiment.

The broken lines shown immediately adjacent to the shaded areas in FIGS. 1 and 8 and also those shown immediately adjacent to the solid contour lines surrounding the unshaded region of the display window in FIGS. 8, 9, 13, represent the bounds of the claimed design, while all other broken lines are directed to environment and form no part of the claimed design.

Claims

CLAIM The ornamental design for an electronic device, as shown and described.

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Inventors:	Okuley; James M. (Portland, OR), Jensen; Kimi (Beaverton, OR)
Applicant:	Name City State Country Type Okuley; James M. Jensen; Kimi Portland Beaverton OR OR US US
Assignee:	Intel Corporation (Santa Clara, CA)
Appl. No.:	D/428,400
Filed:	July 30, 2012

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Current U.S. Class:	D14/315
Current International Class:	1402
Field of Search:	;D14/315-327 ;D18/1,2,7,11 ;235/145A,145R ;341/22,23 ;345/104,156,168,169,173 ;361/679.08,679.09,679.11,679.26,679.27

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References Cited [Referenced By]

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U.S. Patent Documents

5548478	August 1996	Kumar et al.
D425874	May 2000	Tanimura
6091600	July 2000	Jeong
6785128	August 2004	Yun
6816365	November 2004	Hill et al.
D615539	May 2010	Jen
D616883	June 2010	Denhez et al.
D631472	January 2011	Kawase et al.
8081438	December 2011	Karashima et al.
2005/0041378	February 2005	Hamada et al.

Other References

"Thunderbolt (interface)" retrieved Aug. 7, 2012 from Wikipedia at http://en.wikipedia.org/wiki/Thunderbolt.sub.--%28interface%29 ; 7 pages. cited by applicant . Nelson, Tom, "What is Thunderbolt High Speed I/O?", retrieved Aug. 7, 2012 from http://macs.about.com/od/faq1/f/What-Is-Thunderbolt-High-Speed-I-O.h- tm ; 2 pages. cited by applicant . Intel Corporation Technology Brief, "Thunderbolt Technology", copyright 2012. Retrieved Aug. 7, 2012 from http://www.intel.com/content/dam/doc/technology-brief/thunderbolt-technol- ogy-brief.pdf ; 4 pages. cited by applicant . VAIO 13.1'' Z Series Laptop; retrieved Jul. 31, 2012 from http://store.sony.com/webapp/wcs/stores/servlet/ProductDisplay?catalogId=- 10551&storeId=10151&langId=-1&productId=8198552921666449851#additionalImag- e1'' , 3 pages. cited by applicant.

Primary Examiner: Nunn; Freda S
Attorney, Agent or Firm: Patent Capital Group