Solid-state memory module

Frost , et al. April 2, 2

Patent Grant D679272

U.S. patent number D679,272 [Application Number D/390,914] was granted by the patent office on 2013-04-02 for solid-state memory module. This patent grant is currently assigned to Texas Memory Systems, Inc.. The grantee listed for this patent is Holloway H. Frost, John R. Harris, Daniel E. Scheel. Invention is credited to Holloway H. Frost, John R. Harris, Daniel E. Scheel.


United States Patent D679,272
Frost ,   et al. April 2, 2013

Solid-state memory module

Claims

CLAIM The ornamental design for a solid-state memory module, as shown and described.
Inventors: Frost; Holloway H. (Houston, TX), Scheel; Daniel E. (Houston, TX), Harris; John R. (Houston, TX)
Applicant:
Name City State Country Type

Frost; Holloway H.
Scheel; Daniel E.
Harris; John R.

Houston
Houston
Houston

TX
TX
TX

US
US
US
Assignee: Texas Memory Systems, Inc. (Houston, TX)
Appl. No.: D/390,914
Filed: April 29, 2011

Current U.S. Class: D14/313
Current International Class: 1402
Field of Search: ;D14/300-313,348-356 ;312/223.2 ;361/679.39,690,695,724-730,796

References Cited [Referenced By]

U.S. Patent Documents
4744005 May 1988 Milani
4931907 June 1990 Robinson et al.
D329641 September 1992 Goff
D330198 October 1992 Lajara et al.
D335651 May 1993 Jones et al.
D338671 August 1993 Ito et al.
5460571 October 1995 Kato et al.
5751549 May 1998 Eberhardt et al.
6075698 June 2000 Hogan et al.
D485835 January 2004 Ritson et al.
6714411 March 2004 Thompson et al.
D504425 April 2005 Ritson et al.
7110256 September 2006 Hasegawa et al.
7290842 November 2007 Lai
7450383 November 2008 Li et al.
7583507 September 2009 Starr et al.
2003/0030977 February 2003 Garnett et al.
2008/0124234 May 2008 Echazarreta
2008/0180920 July 2008 Chang
2010/0284149 November 2010 Su
2011/0090633 April 2011 Rabinovitz
2011/0219259 September 2011 Frost et al.
Primary Examiner: Kearney; Karen E
Attorney, Agent or Firm: Locke Lord LLP

Description



FIG. 1 is a perspective view of a solid-state memory module according to my new design;

FIG. 2 is a top view of the solid-state memory module according to my new design;

FIG. 3 is a bottom view of the solid-state memory module according to my new design;

FIG. 4 is a front view of the solid-state memory module according to my new design;

FIG. 5 is a rear view of the solid-state memory module according to my new design; and,

FIG. 6 is a left side view of the solid-state memory module according to my new design, the right side being a mirror image thereof.

The broken line showings of the fastener holes and other portions are for the purpose of illustrating unclaimed portions of the solid-state memory module and form no part of the claimed design.

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