Semiconductor substrate

Nishiguchi , et al. January 10, 2

Patent Grant D651992

U.S. patent number D651,992 [Application Number D/379,485] was granted by the patent office on 2012-01-10 for semiconductor substrate. This patent grant is currently assigned to Sumitomo Electric Industries, Ltd.. Invention is credited to Shinsuke Fujiwara, Shin Harada, Yasuo Namikawa, Taro Nishiguchi, Makoto Sasaki.


United States Patent D651,992
Nishiguchi ,   et al. January 10, 2012

Semiconductor substrate

Claims

CLAIM The ornamental design for a semiconductor substrate, as shown and described.
Inventors: Nishiguchi; Taro (Itami, JP), Sasaki; Makoto (Itami, JP), Harada; Shin (Osaka, JP), Fujiwara; Shinsuke (Itami, JP), Namikawa; Yasuo (Osaka, JP)
Assignee: Sumitomo Electric Industries, Ltd. (Osaka-shi, Osaka, JP)
Appl. No.: D/379,485
Filed: November 19, 2010

Foreign Application Priority Data

Aug 17, 2010 [JP] D2010-019920
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;D6/300,309 ;D7/541 ;D9/428,433,456 ;D25/103,109,138-140,155-157 ;117/95 ;257/77,255,627,628 ;438/149,150,689-692,697

References Cited [Referenced By]

U.S. Patent Documents
D217594 May 1970 Bardell
D262962 February 1982 Strumpell
4630093 December 1986 Yamaguchi et al.
5182233 January 1993 Inoue
6927416 August 2005 Arai et al.
7112952 September 2006 Arai et al.
7205639 April 2007 Hierlemann et al.
7476575 January 2009 Tsurume et al.
D589473 March 2009 Takamoto et al.
D614593 April 2010 Lee et al.
7705430 April 2010 Sekiya
D638382 May 2011 Kuzuoka
2005/0106839 May 2005 Shimoda et al.
2005/0287846 December 2005 Dozen et al.
2006/0038182 February 2006 Rogers et al.
2006/0091402 May 2006 Shiomi et al.
2007/0082508 April 2007 Chiang et al.
2009/0011598 January 2009 Nagaya et al.
2010/0176403 July 2010 Sasaki et al.
2011/0111593 May 2011 Kanno
Foreign Patent Documents
8-32038 Feb 1996 JP
2003-68592 Mar 2003 JP
2005-260154 Sep 2005 JP

Other References

US. Appl. No. 29/379,460, filed Nov. 19, 2010, Taro Nishiguchi et al. cited by other .
U.S. Appl. No. 29/379,488, filed Nov. 19, 2010, Taro Nishiguchi et al. cited by other .
U.S. Appl. No. 29/379,471, filed Nov. 19, 2010, Taro Nishiguchi et al. cited by other .
U.S. Notice of Allowance dated Jul. 18, 2011, issued in U.S. Appl. No. 29/379,471. cited by other .
U.S. Office Action dated Jul. 22, 2011, issued in U.S. Appl. No. 29/379,488. cited by other .
U.S. Notice of Allowance dated Jul. 25, 2011, issued in U.S. Appl. No. 29/379,460. cited by other .
U.S. Notice of Allowance dated Aug. 30, 2011, issued in U.S. Appl. No. 29/379,471. cited by other.

Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Drinker Biddle & Reath LLP

Description



FIG. 1 is a front, right, and top perspective view of a semiconductor substrate showing our new design;

FIG. 2 is a front view thereof, a rear view being a mirror image thereof;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a right-side view thereof, a left side view being a mirror image thereof;

FIG. 6 is a partially enlarged view at 6 shown in FIG. 2 thereof;

FIG. 7 is a partially enlarged view at 7 shown in FIG. 2 thereof;

FIG. 8 is an enlarged ended view at 8-8 shown in FIG. 3 thereof; and,

FIG. 9 is a partially enlarged sectional view at 9 shown in FIG. 8 thereof.

The broken line showing of the semiconductor substrate is for the purpose of illustrating environmental structure and forms no part of the claimed design.

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