Pattern formed on the ground layer of a multilayer printed circuit board

Description

FIG. 1 shows a front view of the design according to a first embodiment of the present invention.

FIG. 2 shows a back view of the design according to a first embodiment of the present invention.

FIG. 3 shows a top plan view of the design according to a first embodiment of the present invention.

FIG. 4 shows a bottom plan view of the design according to a first embodiment of the present invention.

FIG. 5 shows a left side view of the design according to a first embodiment of the present invention.

FIG. 6 shows a right side view of the design according to a first embodiment of the present invention.

FIG. 7 shows a partial view of FIG. 1 corresponding to the area indicated by the dashed box in FIG. 1.

FIG. 8 shows a detailed view of an enlarged portion of FIG. 7 indicated by the dashed box in FIG. 7.

FIG. 9 shows a sectional view along the line 9--9 indicated in FIG. 7.

FIG. 10 shows a front plan view of the design according to a second embodiment of the present invention. In this embodiment, the ground layer is transparent.

FIG. 11 shows a back view of the design according to a second embodiment of the present invention.

FIG. 12 shows a top plan view of the design according to a second embodiment of the present invention.

FIG. 13 shows a bottom plan view of the design according to a second embodiment of the present invention.

FIG. 14 shows a right side view of the design according to a second embodiment of the present invention.

FIG. 15 shows a left side view of the design according to a second embodiment of the present invention.

FIG. 16 shows a partial view of FIG. 11 corresponding to the area indicated by the dashed box in FIG. 11.

FIG. 17 shows a detailed view of an enlarged portion of FIG. 17 indicated by the dashed box in FIG. 17; and,

FIG. 18 shows a sectional view along the line 19--19 indicated in FIG. 17.

The broken lines represent unclaimed subject matter.

Claims

CLAIM The ornamental design for a pattern formed on the ground layer of a multilayer printed circuit board, as shown and described.

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Inventors:	Honjo; Mitsuru (Osaka, JP), Yamazaki; Hiroshi (Osaka, JP), Naito; Toshiki (Osaka, JP)
Assignee:	Nitto Denko Corporation (Osaka, JP)
Appl. No.:	D/245,352
Filed:	December 22, 2005

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Foreign Application Priority Data

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Jun 24, 2005 [JP]			2005-018348
Jun 24, 2005 [JP]			2005-018349

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/182 ;174/254,261 ;428/209,901 ;439/55

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References Cited [Referenced By]

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U.S. Patent Documents

3819989	June 1974	Braune
4524239	June 1985	Rouge
4791238	December 1988	Kanno et al.
5855988	January 1999	Matsuo
5999097	December 1999	Liddle et al.
6380493	April 2002	Morita et al.
D457146	May 2002	Yamamoto et al.
6385035	May 2002	Matoba et al.
2002/0075660	June 2002	Samant et al.
2005/0018409	January 2005	Hirakata
2006/0175082	August 2006	Tanaka
2006/0246268	November 2006	Honjo et al.

Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Osha Liang LLP