U.S. patent number D570,283 [Application Number D/278,665] was granted by the patent office on 2008-06-03 for chip-type solid state electrolytic capacitor.
This patent grant is currently assigned to NEC TOKIN Corporation. Invention is credited to Kazuyuki Katoh, Kunihiko Shimizu, Katsuhiro Yoshida.
United States Patent |
D570,283 |
Yoshida , et al. |
June 3, 2008 |
Chip-type solid state electrolytic capacitor
Claims
CLAIM The ornamental design for a chip-type solid state
electrolytic capacitor, as shown and described.
Inventors: |
Yoshida; Katsuhiro (Sendai,
JP), Katoh; Kazuyuki (Sendai, JP), Shimizu;
Kunihiko (Sendai, JP) |
Assignee: |
NEC TOKIN Corporation
(Sendai-shi, JP)
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Appl.
No.: |
D/278,665 |
Filed: |
April 5, 2007 |
Foreign Application Priority Data
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Oct 6, 2006 [JP] |
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2006-027114 |
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Current U.S.
Class: |
D13/125 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/118,123-125,133,184,199 ;320/2
;361/523,535,536,538,539,540,271,277,301.1,328-330,763
;429/178 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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2003-115418 |
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Apr 2003 |
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JP |
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2006-100372 |
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Apr 2006 |
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JP |
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2006-173441 |
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Jun 2006 |
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JP |
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Primary Examiner: Bui; Daniel D
Assistant Examiner: Johannes; Thomas J
Attorney, Agent or Firm: Westerman, Hattori, Daniels &
Adrian, LLP.
Description
FIG. 1 is a front, bottom and right side perspective view of a
chip-type solid state electrolytic capacitor showing our new
design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a left side elevational view thereof;
FIG. 5 is a right side elevational view thereof;
FIG. 6 is a top plan view thereof; and,
FIG. 7 is a bottom plan view thereof.
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