Groove formed around a semiconductor device on a circuit board

Ohsawa , et al. May 13, 2

Patent Grant D568836

U.S. patent number D568,836 [Application Number D/240,252] was granted by the patent office on 2008-05-13 for groove formed around a semiconductor device on a circuit board. This patent grant is currently assigned to Nitto Denko Corporation. Invention is credited to Tetsuya Ohsawa, Emiko Tani.


United States Patent D568,836
Ohsawa ,   et al. May 13, 2008

Groove formed around a semiconductor device on a circuit board

Claims

CLAIM The ornamental design for a groove formed around a semiconductor device on a circuit board, as shown and described.
Inventors: Ohsawa; Tetsuya (Osaka, JP), Tani; Emiko (Osaka, JP)
Assignee: Nitto Denko Corporation (Osaka, JP)
Appl. No.: D/240,252
Filed: October 11, 2005

Foreign Application Priority Data

Apr 13, 2005 [JP] 2005-010971
Apr 13, 2005 [JP] 2005-010989
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;174/250,251,253,254,255,256,265,260,261 ;361/760,748,720 ;336/200

References Cited [Referenced By]

U.S. Patent Documents
D319629 September 1991 Hasegawa et al.
5420558 May 1995 Ito et al.
5467252 November 1995 Nomi et al.
5777277 July 1998 Inagawa
5969590 October 1999 Gutierrez
6114937 September 2000 Burghartz et al.
6121552 September 2000 Brosnihan et al.
6486412 November 2002 Kato
7126452 October 2006 Teshima et al.
2006/0266545 November 2006 Takeuchi et al.
2007/0188287 August 2007 Lien et al.
2007/0205856 September 2007 Matsunaga et al.
Foreign Patent Documents
11-8275 Jan 1999 JP

Other References

Offica Action dated Nov. 4, 2005 for Japanese Application No. 2005-010995 (2 pages). cited by other .
English translation of Office Action dated Nov. 4, 2005 for Japanese Patent Application No. 2005-010995 (1 page). cited by other .
English Translation of Japanese Publication No. 11-8275 dated Jan. 12, 1999 (16 pages). cited by other.

Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Osha Liang LLP

Description



FIG. 1 is a plan view of the groove formed around a semiconductor device on a circuit board showing our new design;

FIG. 2 is an enlarged view of the area boxed by the dash-dot-dash line in FIG. 1; and,

FIG. 3 is a sectional view taken along line 3--3 in FIG. 2.

The broken lines represent unclaimed subject matter.

* * * * *


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