Memory storage device having a poker chip design

Dal Porto , et al. October 16, 2

Patent Grant D553131

U.S. patent number D553,131 [Application Number D/264,091] was granted by the patent office on 2007-10-16 for memory storage device having a poker chip design. This patent grant is currently assigned to X-Digital Media. Invention is credited to Sandro F. Dal Porto, Randall S. Jordan.


United States Patent D553,131
Dal Porto ,   et al. October 16, 2007

Memory storage device having a poker chip design

Claims

CLAIM The ornamental design for a memory storage device having a poker chip design, as shown and described.
Inventors: Dal Porto; Sandro F. (Ladera Ranch, CA), Jordan; Randall S. (San Juan Capistrano, CA)
Assignee: X-Digital Media (Ladera Ranch, CA)
Appl. No.: D/264,091
Filed: August 3, 2006

Current U.S. Class: D14/480.2; D14/480.7
Current International Class: 1402
Field of Search: ;D14/137,156,167,240,242,299,348,356,384-5,402,432-435,496 ;439/518,139,141,144,140,638 ;710/74,62 ;365/131

References Cited [Referenced By]

U.S. Patent Documents
3635608 January 1972 Crouch et al.
D257675 December 1980 Green et al.
D376593 December 1996 Riggs
D391943 March 1998 Han
D433994 November 2000 Jobs et al.
D438202 February 2001 Hui
6522291 February 2003 Noguchi et al.
D482694 November 2003 Chen
D512417 December 2005 Hirakawa et al.
D516031 February 2006 Han et al.
D519454 April 2006 Christianson
7097018 August 2006 Wu
D534160 December 2006 Lin et al.
Primary Examiner: Webster; Robin
Assistant Examiner: Kearney; Karen E
Attorney, Agent or Firm: Stentina Brunda Garred & Brucker

Description



FIG. 1 is a bottom perspective view of the memory storage device having a poker chip design showing our new design, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;

FIG. 2 is a bottom plan view thereof, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;

FIG. 3 is a right side elevational view thereof, the left side elevational view being a mirror image of the right side elevational view;

FIG. 4 is a front elevational view thereof;

FIG. 5 is a rear elevational view thereof;

FIG. 6 is a top plan view thereof, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;

FIG. 7 is a bottom perspective view thereof depicting the connector head of the memory device in an extended state, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;

FIG. 8 is a bottom plan view thereof depicting the connector head of the memory device in an extended state, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;

FIG. 9 is a right side elevational view thereof depicting the connector head of the memory device in an extended state, the left side elevational view with the connector head of the memory device in an extended state being a mirror image of the right side elevational view;

FIG. 10 is a front elevational view thereof depicting the connector head of the memory device in an extended state;

FIG. 11 is a rear elevational view thereof with the connector head of the memory device being in an extended state; and,

FIG. 12 is a top plan view thereof depicting the connector head of the memory device in an extended state, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design.

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