Semiconductor device

Description

FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a right side elevational view thereof; and,

FIG. 7 is a left side elevational view thereof.

Claims

The ornamental design for a semiconductor device, as shown and described.

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Inventors:	Yamada; Junji (Tokyo, JP), Saiki; Seiji (Fukuoka, JP)
Assignee:	Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Appl. No.:	D/164,710
Filed:	July 31, 2002

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Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/110,123,125,179,182 ;174/16.3,52.1,52.2,52.4,261 ;211/4.17,162 ;361/718,728,747,748,760,774,784,785,813,820

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References Cited [Referenced By]

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U.S. Patent Documents

5369551	November 1994	Gore et al.
D357672	April 1995	Terasawa et al.
D389808	January 1998	Yamada et al.
D396450	July 1998	Nishiura et al.
D396847	August 1998	Nakayama et al.
5991162	November 1999	Saso
D453746	February 2002	Kato et al.
6355877	March 2002	Watanabe

Other References

J Yamada, et al., "Next Generation High Power Dual IGBT Module with CSTBT Chip and New Packgage Concept", Official Proceedings International Conferences ZM Communications GmbH, PCIM 2002, Power Electronics, May 14-16, 2002, 11 pages..

Primary Examiner: Shooman; Ted
Assistant Examiner: Sikder; Selina
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.