Integrated circuits substrate

Description

FIG. 1 is a front, top and right side perspective view of an integrated circuits substrate, showing my new design;

FIG. 2 is a front elevational view thereof, the rear elevational view is omitted as that is symmetrical to the front elevational view thereof;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a right side elevational view thereof;

FIG. 6 is a left side elevational view thereof; and,

FIG. 7 is an enlarged cross-sectional view thereof, taken along line 7--7 of FIG. 2, with the internal system omitted.

The broken lines in all views are shown for illustrative purposes only and form no part of the claimed design.

Claims

The ornamental design for an integrated circuits substrate, as shown and described.

---

Inventors:	Michii; Kazunari (Tokyo, JP)
Assignee:	Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Appl. No.:	D/165,700
Filed:	August 16, 2002

---

Foreign Application Priority Data

---

Mar 29, 2002 [JP]			2002-008443

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/182 ;174/52.2,52.4 ;257/666,667,676,686,690,692,696,705,712,735 ;361/742,777,813

---

References Cited [Referenced By]

---

U.S. Patent Documents

5138438	August 1992	Masayuki et al.
5352852	October 1994	Chun
5677570	October 1997	Kondoh et al.
5777265	July 1998	Bhattacharyya et al.
5824950	October 1998	Mosley et al.
5912808	June 1999	Ikemoto
D432097	October 2000	Song et al.
6211564	April 2001	Hatano
6316825	November 2001	Park et al.
6462408	October 2002	Wehrly, Jr.

Foreign Patent Documents

	11-40745		Feb 1999		JP

Primary Examiner: Shooman; Ted
Assistant Examiner: Sikder; Selina
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.