U.S. patent number 9,059,109 [Application Number 13/427,787] was granted by the patent office on 2015-06-16 for package assembly and method of forming the same.
This patent grant is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.. The grantee listed for this patent is Ming-Da Cheng, Chien-Hsiun Lee, Hung-Jen Lin, Chung-Shi Liu, Wen-Hsiung Lu, Tsung-Ding Wang. Invention is credited to Ming-Da Cheng, Chien-Hsiun Lee, Hung-Jen Lin, Chung-Shi Liu, Wen-Hsiung Lu, Tsung-Ding Wang.
United States Patent |
9,059,109 |
Lin , et al. |
June 16, 2015 |
Package assembly and method of forming the same
Abstract
A package assembly including a semiconductor die electrically
coupled to a substrate by an interconnected joint structure. The
semiconductor die includes a bump overlying a semiconductor
substrate, and a molding compound layer overlying the semiconductor
substrate and being in physical contact with a first portion of the
bump. The substrate includes a no-flow underfill layer on a
conductive region. A second portion of the bump is in physical
contact with the no-flow underfill layer to form the interconnected
joint structure.
Inventors: |
Lin; Hung-Jen (Tainan,
TW), Wang; Tsung-Ding (Tainan, TW), Lee;
Chien-Hsiun (Chu-tung Town, TW), Lu; Wen-Hsiung
(Jhonghe, TW), Cheng; Ming-Da (Jhubei, TW),
Liu; Chung-Shi (Hsinchu, TW) |
Applicant: |
Name |
City |
State |
Country |
Type |
Lin; Hung-Jen
Wang; Tsung-Ding
Lee; Chien-Hsiun
Lu; Wen-Hsiung
Cheng; Ming-Da
Liu; Chung-Shi |
Tainan
Tainan
Chu-tung Town
Jhonghe
Jhubei
Hsinchu |
N/A
N/A
N/A
N/A
N/A
N/A |
TW
TW
TW
TW
TW
TW |
|
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
COMPANY, LTD. (TW)
|
Family
ID: |
48796560 |
Appl.
No.: |
13/427,787 |
Filed: |
March 22, 2012 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20130187269 A1 |
Jul 25, 2013 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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61590255 |
Jan 24, 2012 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
21/565 (20130101); H01L 23/3171 (20130101); H01L
24/81 (20130101); H01L 24/11 (20130101); H01L
21/566 (20130101); H01L 21/768 (20130101); H01L
23/3114 (20130101); H01L 21/563 (20130101); H01L
2224/0401 (20130101); H01L 2224/73204 (20130101); H01L
2924/00014 (20130101); H01L 24/83 (20130101); H01L
2224/0239 (20130101); H01L 2224/024 (20130101); H01L
2224/13111 (20130101); H01L 24/27 (20130101); H01L
2924/181 (20130101); H01L 2224/81815 (20130101); H01L
24/16 (20130101); H01L 2224/05582 (20130101); H01L
2224/02311 (20130101); H01L 2224/16227 (20130101); H01L
2224/81191 (20130101); H01L 2224/83855 (20130101); H01L
2224/92125 (20130101); H01L 2224/05666 (20130101); H01L
2224/16145 (20130101); H01L 24/13 (20130101); H01L
2224/0362 (20130101); H01L 2224/05124 (20130101); H01L
2224/81024 (20130101); H01L 2924/2076 (20130101); H01L
2224/13113 (20130101); H01L 2224/05073 (20130101); H01L
2224/05644 (20130101); H01L 2224/13144 (20130101); H01L
2224/03614 (20130101); H01L 2224/05008 (20130101); H01L
2224/94 (20130101); H01L 2224/11849 (20130101); H01L
2224/13116 (20130101); H01L 2224/0347 (20130101); H01L
2224/81801 (20130101); H01L 2224/03612 (20130101); H01L
2224/05647 (20130101); H01L 2224/13139 (20130101); H01L
24/02 (20130101); H01L 24/94 (20130101); H01L
2224/27334 (20130101); H01L 2224/2919 (20130101); H01L
2224/05147 (20130101); H01L 23/525 (20130101); H01L
2224/05187 (20130101); H01L 2224/1146 (20130101); H01L
2224/16225 (20130101); H01L 24/92 (20130101); H01L
2224/27416 (20130101); H01L 24/03 (20130101); H01L
24/05 (20130101); H01L 2224/13147 (20130101); H01L
2924/01047 (20130101); H01L 2224/27318 (20130101); H01L
24/29 (20130101); H01L 2224/11334 (20130101); H01L
2224/05611 (20130101); H01L 2224/05655 (20130101); H01L
2224/13022 (20130101); H01L 2224/131 (20130101); H01L
2224/21 (20130101); H01L 2924/01013 (20130101); H01L
2924/12042 (20130101); H01L 2224/05166 (20130101); H01L
2224/05681 (20130101); H01L 2224/13155 (20130101); H01L
2224/81203 (20130101); H01L 2224/83192 (20130101); H01L
2224/94 (20130101); H01L 2224/81 (20130101); H01L
2224/0239 (20130101); H01L 2924/01029 (20130101); H01L
2224/0239 (20130101); H01L 2924/01013 (20130101); H01L
2224/05124 (20130101); H01L 2924/00014 (20130101); H01L
2224/05147 (20130101); H01L 2924/00014 (20130101); H01L
2224/0347 (20130101); H01L 2924/00014 (20130101); H01L
2224/0362 (20130101); H01L 2924/00014 (20130101); H01L
2224/03612 (20130101); H01L 2924/00014 (20130101); H01L
2224/03614 (20130101); H01L 2924/00014 (20130101); H01L
2224/05166 (20130101); H01L 2924/00014 (20130101); H01L
2224/05666 (20130101); H01L 2924/00014 (20130101); H01L
2224/05681 (20130101); H01L 2924/00014 (20130101); H01L
2224/05187 (20130101); H01L 2924/04941 (20130101); H01L
2224/05187 (20130101); H01L 2924/04953 (20130101); H01L
2224/05647 (20130101); H01L 2924/00014 (20130101); H01L
2224/05655 (20130101); H01L 2924/00014 (20130101); H01L
2224/05611 (20130101); H01L 2924/00014 (20130101); H01L
2224/05644 (20130101); H01L 2924/00014 (20130101); H01L
2224/131 (20130101); H01L 2924/014 (20130101); H01L
2224/21 (20130101); H01L 2924/014 (20130101); H01L
2224/13147 (20130101); H01L 2924/00014 (20130101); H01L
2224/13155 (20130101); H01L 2924/00014 (20130101); H01L
2224/13144 (20130101); H01L 2924/00014 (20130101); H01L
2224/13111 (20130101); H01L 2924/01047 (20130101); H01L
2224/13116 (20130101); H01L 2924/00014 (20130101); H01L
2224/13139 (20130101); H01L 2924/00014 (20130101); H01L
2224/13113 (20130101); H01L 2924/00014 (20130101); H01L
2224/11334 (20130101); H01L 2924/00014 (20130101); H01L
2224/1146 (20130101); H01L 2924/00014 (20130101); H01L
2224/11849 (20130101); H01L 2924/00014 (20130101); H01L
2224/94 (20130101); H01L 2224/11 (20130101); H01L
2224/81203 (20130101); H01L 2924/00014 (20130101); H01L
2224/83855 (20130101); H01L 2924/00014 (20130101); H01L
2224/27334 (20130101); H01L 2924/00014 (20130101); H01L
2224/27416 (20130101); H01L 2924/00014 (20130101); H01L
2224/27318 (20130101); H01L 2924/00014 (20130101); H01L
2924/181 (20130101); H01L 2924/00 (20130101); H01L
2924/12042 (20130101); H01L 2924/00 (20130101) |
Current International
Class: |
H01L
23/31 (20060101); H01L 21/56 (20060101); H01L
23/00 (20060101); H01L 23/525 (20060101) |
Field of
Search: |
;257/737,738,778,780,781,739,779 ;438/108,613,614,615,545 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
Kolbeck, Anton et al., "No-Flow Underfill Process for Flip-Chip
Assembly", 14th European Microelectronics and Packaging Conference
& Exhibition, Friedrichshafen, Germany, Jun. 23-25, 2002, pp.
1-5. cited by applicant.
|
Primary Examiner: Vu; David
Assistant Examiner: Inoussa; Mouloucoulaye
Attorney, Agent or Firm: Lowe Hauptman & Ham LLP
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATION
The present application claims priority of U.S. Provisional Patent
Application No. 61/590,255, filed on Jan. 24, 2012, which is
incorporated herein by reference in its entirety.
Claims
What is claimed is:
1. A package assembly, comprising a semiconductor die electrically
coupled to a substrate by an interconnected joint structure:
wherein the semiconductor die comprises a bump overlying a
semiconductor substrate, and a molding compound layer overlying the
semiconductor substrate and being in physical contact with a first
portion of the bump; wherein the substrate comprises a no-flow
underfill layer on a conductive region, the no-flow underfill layer
comprising flux, and the no-flow underfill layer is separated from
the molding compound layer; and wherein a second portion of the
bump is in physical contact with the no-flow underfill layer to
form the interconnected joint structure.
2. The package assembly of claim 1, wherein the bump is a solder
bump.
3. The package assembly of claim 1, wherein the bump is
electrically connected to the conductive region.
4. The package assembly of claim 1, wherein the second portion of
the bump protrudes from a top surface of the molding compound
layer.
5. The package assembly of claim 1, wherein the semiconductor die
further comprises a post-passivation interconnect (PPI) layer
between the semiconductor substrate and the molding compound
layer.
6. The package assembly of claim 5, wherein semiconductor die
further comprises a polymer layer between the PPI layer and the
molding compound layer.
7. The package assembly of claim 5, wherein semiconductor die
further comprises a polymer layer between the PPI layer and the
semiconductor substrate.
8. The package assembly of claim 1, wherein the bump is a solder
bump with a diameter greater than 200 .mu.m.
9. A package assembly comprising: a first substrate having a
conductive pad; a bump structure electrically connected to the
conductive pad; a molding compound over the first substrate and in
physical contact with the bump structure; a second substrate having
a conductive region; a no-flow underfill (NUF) material over the
conductive region; and a gap between the NUF material and the
molding compound, wherein the bump structure is in physical contact
with the NUF material and in electrical contact with the conductive
region; and the NUF comprises flux.
10. The package assembly of claim 9, wherein a height of the
molding compound is less than a height of the bump structure.
11. The package assembly of claim 10, wherein the height of the
molding compound is between about 0.25 times the height of the bump
structure and about 0.75 times the height of the bump
structure.
12. The package assembly of claim 9, further comprising an
interconnect layer electrically connected between the bump
structure and the conductive pad, the interconnect layer comprising
a landing pad region, and the bump structure is in contact with the
landing pad region.
13. The package assembly of claim 12, wherein the landing pad
region is directly above the conductive pad.
14. The package assembly of claim 9, wherein the bump structure
comprises: an under bump metallurgy (UBM) layer over the conductive
pad; and a bump feature over the UBM layer.
15. A package assembly comprising: a first substrate having a
conductive pad; a bump structure electrically connected to the
conductive pad; a molding compound in physical contact with the
bump structure, wherein the bump structure protrudes from the
molding compound; a second substrate having a conductive region;
and a no-flow underfill (NUF) material comprising flux over the
conductive region, wherein the NUF material is separated from the
molding compound, wherein the bump structure is in physical contact
with the NUF material and in electrical contact with the conductive
region.
16. The package assembly of claim 15, further comprising a
protection layer between the molding compound and the first
substrate, wherein the molding compound is in physical contact with
the protection layer.
17. The package assembly of claim 15, further comprising a
redistribution layer (RDL) between the molding compound and the
first substrate, wherein the RDL is in electrical contact with the
conductive pad, and the bump structure is in electrical contact
with the RDL.
18. The package assembly of claim 15, wherein the second substrate
is an interposer.
19. The package assembly of claim 15, further comprising a mask
layer over the second substrate, wherein the mask layer defines an
opening exposing the conductive region.
20. The package assembly of claim 19, wherein the NUF material
covers the conductive region and exposes a portion of the mask
layer.
Description
TECHNICAL FIELD
This disclosure relates to the fabrication of package assemblies
and, more particularly, to the fabrication of package assemblies
for semiconductor devices.
BACKGROUND
Modern integrated circuits are made up of literally millions of
active devices such as transistors and capacitors. These devices
are initially isolated from each other, but are later
interconnected together to form functional circuits. Typical
interconnect structures include lateral interconnections, such as
metal lines (wirings), and vertical interconnections, such as vias
and contacts. Interconnections are increasingly determining the
limits of performance and the density of modern integrated
circuits. On top of the interconnect structures, bond pads are
formed and exposed on the surface of the respective chip.
Electrical connections are made through bond pads to connect the
chip to a package substrate or another die. Bond pads can be used
for wire bonding or flip-chip bonding. Flip-chip packaging utilizes
bumps to establish electrical contact between a chip's input/output
(I/O) pads and a substrate or lead frame of a package.
Structurally, a bump actually contains the bump itself and an
"under bump metallurgy" (UBM) located between the bump and the I/O
pad.
Wafer level chip scale packaging (WLCSP) is currently widely used
because WLCSP is low cost and has relatively simple processes. In a
typical WLCSP, post-passivation interconnect (PPI) lines such as
redistribution lines (RDLs) are formed on passivation layers,
followed by the formation of polymer films and bumps. A ball
placement or a ball drop process is utilized in the WLCSP
technology, but the ball drop performance is still a concern.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-5 are cross-sectional views of a semiconductor die at
various intermediate stages of a method of forming a semiconductor
device in accordance with exemplary embodiments;
FIG. 6 is a cross-sectional view of a package substrate in
accordance with an exemplary embodiment; and
FIG. 7 is a cross-sectional view of a package assembly in
accordance with an exemplary embodiment.
DETAILED DESCRIPTION
The making and using of the embodiments of the disclosure are
discussed in detail below. It should be appreciated, however, that
the embodiments provide many applicable inventive concepts that can
be embodied in a wide variety of specific contexts. The specific
embodiments discussed are merely illustrative of specific ways to
make and use the embodiments, and do not limit the scope of the
disclosure. Embodiments described herein relate to the use of bump
structures for use with semiconductor devices. As will be discussed
below, embodiments are disclosed that utilize a bump structure for
the purpose of attaching one substrate to another substrate,
wherein each substrate may be a die, wafer, interposer substrate,
printed circuit board, packaging substrate, or the like, thereby
allowing for die-to-die, wafer-to-die, wafer-to-wafer, die or wafer
to interposer substrate or printed circuit board or packaging
substrate, or the like. Throughout the various views and
illustrative embodiments, like reference numerals are used to
designate like elements.
Reference will now be made in detail to exemplary embodiments
illustrated in the accompanying drawings. Wherever possible, the
same reference numbers are used in the drawings and the description
to refer to the same or like parts. In the drawings, the shape and
thickness may be exaggerated for clarity and convenience. This
description will be directed in particular to elements forming part
of, or cooperating more directly with, an apparatus in accordance
with the present disclosure. It is to be understood that elements
not specifically shown or described may take various forms well
known to those skilled in the art. Further, when a layer is
referred to as being on another layer or "on" a substrate, it may
be directly on the other layer or on the substrate, or intervening
layers may also be present. Reference throughout this specification
to "one embodiment" or "an embodiment" means that a particular
feature, structure, or characteristic described in connection with
the embodiment is included in at least one embodiment. Thus, the
appearances of the phrases "in one embodiment" or "in an
embodiment" in various places throughout this specification are not
necessarily all referring to the same embodiment. Furthermore, the
particular features, structures, or characteristics may be combined
in any suitable manner in one or more embodiments. It should be
appreciated that the following figures are not drawn to scale;
rather, these figures are merely intended for illustration.
FIGS. 1-5 are cross sectional views of a semiconductor die at
various intermediate stages of a method of forming a semiconductor
device in accordance with some embodiments.
Referring first to FIG. 1, a semiconductor substrate 102 includes a
substrate 10, an electrical circuitry 12, an inter-layer dielectric
(ILD) layer 14, inter-metal dielectric (IMD) layers 16 and the
associated metallization layers.
A portion of the substrate 10 having electrical circuitry 12 formed
thereon is shown, in accordance with some embodiments. The
substrate 10 may comprise, for example, bulk silicon, doped or
undoped, or an active layer of a semiconductor-on-insulator (SOI)
substrate. The substrate 10 may be provided as a wafer level scale
or a chip level scale. Other substrates, such as a multi-layered or
gradient substrate may also be used.
Electrical circuitry 12 formed on the substrate 10 may be any type
of circuitry suitable for a particular application. In some
embodiments, the electrical circuitry 12 includes electrical
devices formed on the substrate 10 having one or more dielectric
layers overlying the electrical devices. Metal layers may be formed
between dielectric layers to route electrical signals between the
electrical devices. Electrical devices may also be formed in one or
more dielectric layers. For example, the electrical circuitry 12
may include various N-type metal-oxide semiconductor (NMOS) and/or
P-type metal-oxide semiconductor (PMOS) devices, such as
transistors, capacitors, resistors, diodes, photo-diodes, fuses,
and the like, interconnected to perform one or more functions. The
functions may include memory structures, processing structures,
sensors, amplifiers, power distribution, input/output circuitry, or
the like. One of ordinary skill in the art will appreciate that the
above examples are provided for illustrative purposes only to
further explain applications of some illustrative embodiments and
are not meant to limit the disclosure in any manner. Other
circuitry may be used as appropriate for a given application.
The ILD layer 14 may be formed, for example, of a low-K dielectric
material, such as phosphosilicate glass (PSG), borophosphosilicate
glass (BPSG), fluorinated silicate glass (FSG), SiO.sub.xC.sub.y,
Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds
thereof, composites thereof, combinations thereof, or the like, by
any suitable method, such as spinning, chemical vapor deposition
(CVD), and/or plasma-enhanced CVD (PECVD). In some embodiments, the
ILD layer 14 may comprise a plurality of dielectric layers.
Contacts (not shown) may be formed through the ILD layer 14 to
provide an electrical connection to the electrical circuitry
12.
One or more inter-metal dielectric (IMD) layers 16 and the
associated metallization layers are formed over the ILD layer 14.
Generally, the one or more IMD layers 16 and the associated
metallization layers (such as metal lines 18 and vias 19) are used
to interconnect the electrical circuitry 12 to each other and to
provide an external electrical connection. The IMD layers 16 may be
formed of a low-K dielectric material, such as FSG formed by PECVD
techniques or high-density plasma CVD (HDPCVD), or the like, and
may include intermediate etch stop layers. In some embodiments, one
or more etch stop layers (not shown) may be positioned between
adjacent ones of the dielectric layers, e.g., the ILD layer 14 and
the IMD layers 16. Generally, the etch stop layers provide a
mechanism to stop an etching process when forming vias and/or
contacts. The etch stop layers are formed of a dielectric material
having a different etch selectivity from adjacent layers, e.g., the
underlying semiconductor substrate 10, the overlying ILD layer 14,
and the overlying IMD layers 16. In some embodiments, etch stop
layers may be formed of SiN, SiCN, SiCO, CN, combinations thereof,
or the like, deposited by CVD or PECVD techniques.
In some embodiments, the metallization layers, including metal
lines 18 and vias 19, may be formed of copper or copper alloys, or
of other metals. Further, the metallization layers include a top
metal layer 20 formed and patterned in or on an uppermost IMD layer
to provide external electrical connections and to protect the
underlying layers from various environmental contaminants. In some
embodiments, the uppermost IMD layer is formed of a dielectric
material, such as silicon nitride, silicon oxide, undoped silicon
glass, and the like. In subsequent drawings, semiconductor
substrate 10, electrical circuitry 12, ILD layer 14, and
metallization layers 18 and 19 are not illustrated. In some
embodiments, the top metal layer 20 is formed as a part of the top
metallization layer on the uppermost IMD layer.
Thereafter, a contact pad 104 is formed and patterned to contact
the top metal layer 20, or alternatively, electrically coupled to
top metal layer 20 through a via. In some embodiments, the contact
pad 104 may be formed of aluminum, aluminum copper, aluminum
alloys, copper, copper alloys, or the like. One or more passivation
layers, such as a passivation layer 106 are formed and patterned
over the contact pad 104. In some embodiments, the passivation
layer 106 may be formed of a dielectric material, such as undoped
silicate glass (USG), silicon nitride, silicon oxide, silicon
oxynitride or a non-porous material by any suitable method, such as
CVD, PVD, or the like. The passivation layer 106 is formed to cover
a peripheral portion of the contact pad 104, and to expose a
central portion of the contact pad 104 through an opening in
passivation layer 106. The passivation layer 106 may be a single
layer or a laminated layer. In FIG. 1, a single layer of the
contact pad 104 and the passivation layer 106 are shown for
illustrative purposes only. As such, other embodiments may include
any number of conductive layers and/or passivation layers.
Next, a first protective layer 108 is formed and patterned over the
passivation layer 106. In some embodiments, the first protective
layer 108 may be, for example, a polymer layer, which is patterned
to form an opening 109, through which the contact pad 104 is
exposed. In some embodiments, the polymer layer is formed of a
polymer material such as an epoxy, polyimide, benzocyclobutene
(BCB), polybenzoxazole (PBO), and the like, although other
relatively soft, often organic, dielectric materials can also be
used. The formation methods include spin coating or other methods.
The first protective layer 108 has a thickness in a range between
about 1 .mu.m and about 10 .mu.m. For example, a thickness between
about 5 .mu.m and about 8 .mu.m.
Referring to FIG. 2 at least one metallization layer 110 is formed
on the first protective layer 108 and fills the opening 109. The
metallization layer patterned as an interconnect layer, which is
electrically connected to the contact pad 104 and may expose a
portion of the underlying first protective layer 108. In at least
an embodiment, the interconnect layer 110 is a post-passivation
interconnect (PPI) layer 110, which may also functions as power
lines, re-distribution lines (RDL), inductors, capacitors or any
passive components. The PPI layer 110 includes an interconnect line
region 110A and a landing pad region 110B. In some embodiments, the
interconnect line region 110A and the landing pad region 110B may
be formed simultaneously, and may be formed of a same conductive
material. A bump feature will be formed over and electrically
connected to the landing pad region 110B in subsequent processes.
In some embodiments, the PPI layer 110 includes copper, aluminum,
copper alloy, or other mobile conductive materials using plating,
electroless plating, sputtering, chemical vapor deposition methods,
and the like. In some embodiments, the PPI layer 110 includes a
copper layer or a copper alloy layer. In the embodiment of FIG. 2,
the landing region 110B is not directly over the contact pad 104.
In other embodiments, through the routing of PPI layer 110, the
landing pad region 110B is directly over the contact pad 104.
With reference to FIG. 2, a second protective layer 112 is then
formed on the PPI layer 110. Using photolithography and/or etching
processes, the second protective layer 112 is patterned to form an
opening 113 exposing at least a portion of the landing pad region
110B of the PPI layer 110. The formation methods of the opening 113
may include lithography, wet or dry etching, laser drilling, and/or
the like. In some embodiments, the second protective layer 112 is
formed of a polymer layer, such as an epoxy, polyimide,
benzocyclobutene (BCB), polybenzoxazole (PBO), and the like,
although other relatively soft, often organic, dielectric materials
may also be used. In some embodiments, the second protective layer
112 is formed of a non-organic material selected from un-doped
silicate glass (USG), silicon nitride, silicon oxynitride, silicon
oxide, and combinations thereof.
As shown in FIG. 3, an under-bump metallization (UBM) layer 114 is
formed on the exposed portion of the landing pad region 110B. UBM
layer 114 is formed so as to electrically connect to the PPI layer
110. In some embodiments, the UBM layer 114 may extend to a surface
of the second protective layer 112. The formation methods of the
UBM layer 114 include photoresist coating, lithography, wet or dry
etching, and/or the like. In some embodiments, the UBM layer 114
includes at least one metallization layer comprising titanium (Ti),
tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN),
copper (Cu), copper alloys, nickel (Ni), tin (Sn), gold (Au), or
combinations thereof. In some embodiments, the UBM layer 114
includes at least one Ti-containing layer and at least one
Cu-containing layer.
As shown in FIG. 4, a bump 118 is formed on the UBM layer 114. The
bump 118 can be a solder bump, a Cu bump or a metal bump including
Ni or Au. In some embodiments, the bump 118 is a solder bump formed
by attaching a solder ball to the UBM layer 114 and then thermally
reflowing the solder material. In an embodiment, the solder bump
has a diameter greater than about 200 .mu.m. In some embodiments,
the solder bump includes a lead-free pre-solder layer, SnAg, or a
solder material including alloys of tin, lead, silver, copper,
nickel, bismuth, or combinations thereof. In some embodiments, the
solder bump is formed by plating a solder layer using
photolithography technologies followed by reflow processes.
Next, as shown in FIG. 5, a molding compound layer 116 is applied
on the second protective layer 112, where the bump 118 is partially
buried in the molding compound layer 116. In some embodiments, the
molding compound layer 116 is in physical contact with a lower
portion of the bump 118, while an upper portion of the bump 118 is
exposed and protrudes from a top surface 116A of the molding
compound layer 116. In some embodiments, a top portion 118T of the
bump 118 is higher than the top surface 116A of the molding
compound layer 116. In some embodiments, the bump 118 is not
polished after the reflow, and the top portion 118T of the bump 118
above the top surface 116A of the molding compound layer 116 may
remain to have a rounded-like profile. The molding compound layer
116 may be in physical contact with the second protective layer 112
and/or the UBM layer 114. In some embodiments, a height (H1) of the
bump 118 that is buried in the molding compound layer 116 may be
between about 1/4 to 3/4 of a total height H2 of the bump 118. In
at least one embodiment, the molding compound layer 116 is formed
by applying a liquid molding compound and performing a curing
process to cure and solidify the liquid molding compound. In some
embodiments, a release film or a soft material may be applied on
the liquid molding compound. Pressure is applied on the release
film on the liquid molding compound, so that a portion of the bump
118 is pressed into release film. Furthermore, the pressure applied
on the release film may push some of liquid molding compound
downward. While the pressure is applied to the release film pushing
against the bump and the liquid molding compound, a curing may be
performed to cure and solidify liquid molding compound. After the
solidification, the top portion 118T of the bump 118 is lower than
the top surface 116A of molding compound layer 116. Thereafter, the
release film is peeled off the molding compound layer 116, which is
now in a solid form. The molding compound layer 116 residue
remaining on the top portion 118T of the bump 118 is then etched.
In the resulting structure, the molding compound layer 116 is
formed with a portion of the bump 118 buried therein.
After the bump formation, for example, an encapsulant may be
formed, a singulation process may be performed to singulate
individual dies 100 and wafer-level or die-level stacking or the
like may be performed. Embodiments may be used in many different
situations. For example, embodiments may be used in a die-to-die
bonding configuration, a die-to-wafer bonding configuration, a
wafer-to-wafer bonding configuration, die-level packaging,
wafer-level packaging, or the like. In some embodiments, the
semiconductor die 100 shown in FIG. 5 is flipped upside down and
attached to another substrate 200 as depicted in FIG. 6.
FIG. 6 is a cross-sectional view of a package substrate in
accordance with an exemplary embodiment. In some embodiments, the
substrate 200 may be a package substrate, board (e.g., a printed
circuit board (PCB)), a wafer, a die, an interposer substrate, or
other suitable substrate. The bump 118 of the semiconductor die 100
can be electrically coupled to the substrate 200 through various
conductive attachment points. For example, a conductive region 202
is formed and patterned on the substrate 200. The conductive region
202 is a contact pad or a portion of a conductive trace, which is
exposed by an opening in a mask layer 204. In some embodiments, the
mask layer 204 is a solder resist layer formed and patterned on the
substrate 200 to expose the conductive region 202. The mask layer
204 has a mask opening, which provides a window for jointing.
In at least on embodiment, a no-flow underfill (NUF) layer 206 is
formed on the conductive region 202 within the window of the mask
layer 204 prior to mounting the semiconductor die 100 to the
substrate 200. The NUF material combines underfill and flux into a
single material as a hybrid underfill-flux. The NUF layer 206 may
act as fluxing agent for the solder reflow and form a solid during
reflow cycle that reinforces the interconnects. Using the NUF
material provides significant cost savings as it reduces the number
of process steps used to bond the semiconductor die 100 to the
substrate 200 and increases the throughput of the process. In some
embodiments, the no-flow underfill material is deposited on the
conductive region 202 using spin coating, dispensing, or
lamination. The NUF material may be an epoxy resin having a high
coefficient of thermal expansion (CTE) and high glass transition
temperature. The volume deposition of the NUF material can be
controlled to a thickness that covers a major portion of the
conductive region 202 and exposes the remainder of the mask layer
204.
FIG. 7 is a cross-sectional diagram depicting an exemplary
embodiment of a package assembly. In some embodiments, the
semiconductor die 100 can be electrically coupled to the substrate
200, in which the bump 118 is in physical contact with the NUF
layer 206 and electrically connected to the conductive region 202
so as to form an interconnected joint structure 208 between the die
100 and the substrate 200. In some embodiments, the upper portion
of the bump 118 is in physical contact with the NUF layer 206, and
the top portion 118T of the bump 118 is electrically connected to
the conductive region 202. For example, the semiconductor die 100
can be attached to the substrate 200 by heating the substrate 200,
dispensing the NUF layer 206 on the substrate, positioning the bump
118 of the semiconductor die 100 on/in the NUF layer 206 and then
using a thermal-compression bonding process to reflow and attach
the die 100 to the substrate 200. During reflow, the flux embedded
in the NUF layer 206 activates and allows the solder bump to reflow
and form the interconnected joint structure 208. After reflow,
further curing of underfill may be performed. Therefore, the
semiconductor die 100, the interconnected joint structure 208, and
the substrate 200 are completed as a package assembly 300, or in
the present embodiment, a flip-chip package assembly. By forming
the molding compound layer 116 around the lower portion of the bump
118, the thermal cycling life of the package assembly can be
enhanced. By applying the NUF layer 206 on the substrate 200, the
solder ball drop performance can be further improved.
In accordance with an embodiment, a package assembly includes a
semiconductor die electrically coupled to a substrate by an
interconnected joint structure. The semiconductor die includes a
bump overlying a semiconductor substrate, and a molding compound
layer overlying the semiconductor substrate and being in physical
contact with the bump, where the bump is partially embedded in the
molding compound layer. The substrate comprises a no-flow underfill
layer on a conductive region. A portion of the bump is in physical
contact with the no-flow underfill layer to form the interconnected
joint structure.
In accordance with another embodiment, a method of forming a
package assembly including: forming a no-flow underfill layer on a
substrate; and attaching a semiconductor die to the substrate. The
semiconductor die comprises a bump and a molding compound layer in
physical contact with a lower portion of the bump. An upper portion
of the bump is in physical contact with the no-flow underfill
layer.
In according with one aspect of the exemplary embodiment, a method
of forming a package assembly includes: forming a bump on a first
substrate; forming a molding compound layer on the first substrate,
being in physical contact with a lower portion of the bump; forming
a no-flow underfill layer on a second substrate; and attaching the
first substrate to a second substrate. The second substrate
includes the no-flow underfill layer on a conductive region. An
upper portion of the bump is in physical contact with the no-flow
underfill layer and electrically connected to the conductive region
so as to form an interconnected joint structure between the first
substrate and the second substrate.
In the preceding detailed description, the disclosure is described
with reference to specific exemplary embodiments thereof. It will,
however, be evident that various modifications, structures,
processes, and changes may be made thereto without departing from
the broader spirit and scope of the disclosure. The specification
and drawings are, accordingly, to be regarded as illustrative and
not restrictive. It is understood that the disclosure is capable of
using various other combinations and environments and is capable of
changes or modifications within the scope of inventive concepts as
expressed herein.
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