U.S. patent number 8,912,840 [Application Number 13/638,063] was granted by the patent office on 2014-12-16 for switching device with a jfet series arrangement.
This patent grant is currently assigned to Eth Zurich, Eth Transfer. The grantee listed for this patent is Daniel Aggeler, Jurgen Biela, Johann Walter Kolar. Invention is credited to Daniel Aggeler, Jurgen Biela, Johann Walter Kolar.
United States Patent |
8,912,840 |
Aggeler , et al. |
December 16, 2014 |
Switching device with a JFET series arrangement
Abstract
A switching device for switching a current between a first
connection and a second connection including a series circuit of at
least two JFETs (J1-Jn), with further JFETs (J2-Jn), which are
connected in series to a lowest JFET (J1), and wherein a wiring
network for stabilizing the gate voltages of the JFETs (J1-Jn) is
connected between the second connection and the first termination.
One additional circuit is connected between each gate connection
(GJ2, GJ3 . . . GjN) of the further JFETs (J2-Jn) and associated
cathode connections of diodes (DAV) of the wiring network. During
switch-on and in the switched-on state, said additional circuit
keeps the potential of the respective gate connection higher than
the potential of the associated source connection.
Inventors: |
Aggeler; Daniel (Zurich,
CH), Biela; Jurgen (Zurich, CH), Kolar;
Johann Walter (Zurich, CH) |
Applicant: |
Name |
City |
State |
Country |
Type |
Aggeler; Daniel
Biela; Jurgen
Kolar; Johann Walter |
Zurich
Zurich
Zurich |
N/A
N/A
N/A |
CH
CH
CH |
|
|
Assignee: |
Eth Zurich, Eth Transfer
(Zurich, CH)
|
Family
ID: |
44227928 |
Appl.
No.: |
13/638,063 |
Filed: |
April 6, 2011 |
PCT
Filed: |
April 06, 2011 |
PCT No.: |
PCT/CH2011/000072 |
371(c)(1),(2),(4) Date: |
October 30, 2012 |
PCT
Pub. No.: |
WO2011/123962 |
PCT
Pub. Date: |
October 13, 2011 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20130057332 A1 |
Mar 7, 2013 |
|
Foreign Application Priority Data
Current U.S.
Class: |
327/430 |
Current CPC
Class: |
H03K
17/102 (20130101); H03K 17/567 (20130101); H03K
2017/6875 (20130101); H03K 17/107 (20130101) |
Current International
Class: |
H03K
17/687 (20060101) |
Field of
Search: |
;327/392-394,398,399,427,430 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
Other References
Biela J et al; Balancing circuit for a 5kV/50ns Pulsed Power Switch
Based on SiC-JFET Super Cascode, 2009. cited by applicant.
|
Primary Examiner: Nguyen; Hai L
Attorney, Agent or Firm: Rankin, Hill & Clark LLP
Claims
The invention claimed is:
1. A switching device for switching a current between a first
terminal and a second terminal, comprising: a series arrangement of
at least two JFETs of which a lowermost JFET is connected to a
first terminal or the lowermost JFET is connected in a cascade
arrangement via a control switch to the first terminal, and of one
or more further, upper JFETs which is or are connected in series to
the lowermost JFET, wherein the JFET which is distanced furthest
from the lowermost JFET is indicated as the uppermost JFET and with
its drain terminal is connected to a second terminal, wherein a
passive circuit network for the dynamic activation of the gate
voltages of the JFETs is connected between the gate terminals of
the JFETs and the first terminal, wherein the passive circuit
network in each case between the gates of two consecutive JFETs
comprises diodes which are operated in the blocking direction,
wherein an additional circuit is connected in each case between the
gate terminals of the upper JFETs and the cathode terminals of the
diodes of the circuit network, or between anode terminals of the
diodes of the circuit network and the gate terminals of assigned
JFETs, and this additional circuit keeps the potential of the
respective gate terminal high with respect to the associated source
terminal, during the dynamic switching-on as well as in the
stationary switched-on state; wherein the additional circuit
comprises one or more diodes which are operated in series and in
the blocking direction between the gate terminals and the cathode
terminals; and, wherein the additional circuit comprises one or
more capacitors which are in each case parallel to the diodes
operated in the blocking direction.
2. The switching device according to claim 1, wherein the
additional circuit comprises one or more diodes which are operated
in series and in the blocking direction between the gate terminals
and the cathode terminals.
3. The switching device according to claim 1, wherein the
additional circuit comprises one or more capacitors which are in
each case parallel to the diodes operated in the blocking
direction.
4. The switching device according to claim 1, wherein the
additional circuit and the activation circuit are designed such
that with a switching-on procedure and with the switched-on state,
the voltage drops occurring at the upper JFETs as well as the
forward voltage of the diodes of the circuit network which are
operated in the blocking direction, are reduced, and wherein in
comparison to the switching device without an additional circuit or
activation circuit, a gate-source voltage results which is at least
two times smaller, or no voltage drop results or the gate-source
voltage is slightly positive.
5. The switching device according to claim 1, wherein at least one
activation circuit comprising an additional circuit and of a
further diode is present.
6. The switching device according to claim 5, in which in at least
one of the additional circuits, a further diode is connected in
series to the capacitor of the additional circuit and antiparallel
to the diode of the additional circuit.
7. A switching device for switching a current between a first
terminal and a second terminal, comprising: a series arrangement of
at least two p-channel JFETs, of which a lowermost JFET is
connected to a first terminal, or the lowermost JFET is connected
in a cascade arrangement via a control switch to the first
terminal, and of one or more further, upper JFETs which is or are
connected in series to the lowermost JFET, wherein the JFET which
is distanced furthest from the lowermost JFET is indicated as the
uppermost JFET and with its source terminal is connected to a
second terminal, wherein a passive circuit network for the dynamic
activation of the gate voltages of the JFETs is connected between
the gate terminals of the JFETs and the first terminal, wherein the
passive circuit network in each case between the gates of two
consecutive JFETs comprises diodes which are operated in the
blocking direction, wherein an additional circuit is connected in
each case between the gate terminals of the upper JFETs and the
cathode terminals of the diodes of the circuit network, or between
anode terminals of the diodes of the circuit network and the gate
terminals of assigned JFETs, and this additional circuit keeps the
potential of the respective gate terminal high with respect to the
associated drain terminal, during the dynamic switching-on as well
as in the stationary switched-on state; wherein the additional
circuit comprises one or more diodes which are operated in series
and in the blocking direction between the gate terminals and the
cathode terminals; and, wherein the additional circuit comprises
one or more capacitors which are in each case parallel to the
diodes operated in the blocking direction.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of electronic switch technology
and in particular to a switching device with a series arrangement
of JFETs (junction field effect transistors).
2. Description of Related Art
Power switches or switching devices for switching at high operating
voltages can be realised in power-electronic circuits by way of
cascading or serially arranged transistors. Thereby, according to
U.S. Pat. No. 6,822,842 or DE 199 26 109 A1, such switching devices
are, for example, indicated as a cascode circuit, and are based on
the special arrangement of a MOSFET M and at least one JFET
J.sub.1, illustrated by FIG. 1. The switches are arranged between a
first terminal 1 and a second terminal 2 and are controlled by a
control connection 3 of the MOSFET M. This known switching device
for high operating voltages based on the cascode topology envisages
the connection of several JFETs J.sub.2 . . . J.sub.n in series,
and thus the attainment of a high blocking voltage. A circuit
network 4 is connected between the first terminal 1 and the second
terminal 2, for the passive control of the dynamic blocking voltage
distribution of the power switch constructed with the transistors
arranged in series, wherein avalanche diodes D.sub.Av,1-D.sub.AV,n
of the circuit network 4 are connected between the gate terminals
of the JFETs. The manner of functioning of the circuit network 4
for the symmetrical blocking voltage distribution of the JFETs is
described in the publication "Balancing Circuit for a 5 kV/50 ns
Pulsed Power Switch Based on SiC-JFET Super Cascode" (J. Biela, D.
Aggeler, J. W. Kolar, Proceedings of the 17.sup.th IEEE Pulsed
Power Conference (PPCV'09)).
In the switched-on condition, a voltage drop across each element
arises due to the forward resistances of the individual
semiconductor switches M, J.sub.1 . . . J.sub.n in the series
arrangement. Thereby, the sum of all voltage drops particularly
with the uppermost JFET J.sub.n of FIG. 1 causes a different
gate-source voltage than at the lower JFETs. This different
gate-source voltage can lead to the uppermost transistor switching
off and thereby becoming high-impedance and experiencing a high
forward voltage in the switched-on state, which leads to its
destruction in the worst case.
BRIEF SUMMARY OF THE INVENTION
It is therefore the object of the invention, to provide a switching
device with a series arrangement of JFETs of the initially
mentioned type, which overcomes the mentioned disadvantages.
The switching device for switching a current between a first
terminal and a second terminal thus comprises a series arrangement
of at least two JFETs, of which a lowermost JFET is connected to
the first terminal or is connected to the first terminal via a
control switch arranged in series. At least one further JFET is
present, which is connected in series to the lowermost JFET,
wherein the JFET which is distanced furthest to the lowermost JFET
is indicated as the uppermost JFET and with its drain terminal is
connected to the second terminal. The JFETS which are different
from the lowermost or first JFET are commonly also indicated as
upper JEFTs. A circuit network for the dynamic blocking voltage
distribution and for the stabilisation of the gate voltages of the
JFETs is connected between the first terminal and the second
terminal. The circuit network, for example, in each case comprises
diodes operated in the blocking direction, between the gates of two
consecutive JFETs. Thereby, an additional circuit is connected in
each case between the gate terminals of the upper JFETs and the
cathode of the respective diode, and this additional circuit in the
switched-on state of the circuit maintains a high potential at the
gate terminal of the upper JFETs, and prevents an undesired
switching-off of the upper JFET.
By way of this, with switched-on upper JFETs, the voltages at the
upper gates are kept slightly above, preferably however equal to or
slightly below the voltage at the respective source terminal,
depending on the load current. Preferably, a gate-source voltage
results, which is at least two times, preferably five times or ten
times smaller than without the additional circuit. When
switching-on, the upper JFETS tend to remain switched on more so
than without the additional circuit, on account of this. By way of
this, one again prevents, in particular, the uppermost JFET between
the first and the second terminal becoming high-impedance and
taking up the complete voltage.
The additional circuit has the effect that when switching on, the
parasitic capacitances of the circuit network can be discharged in
each case via the diode of the additional circuit and
simultaneously the voltages of the respective gates of the JFETs
being kept high via a capacitance parallel to the diode of the
additional circuit.
By way of this, the dynamic switching-on of the power switch which
is constructed with transistors arranged in series, is balanced as
well as synchronised due to the complete additional circuit
network.
The additional circuit seen per se, generally speaking and for each
of the JFETs is capable of applying a settable voltage between its
gate terminal and source terminal. This additional circuit effects
a symmetrical voltage loading of the gate-source terminals of the
JFETs connected in series.
In further preferred embodiments of the invention, the additional
circuit is not connected at each of the upper JFETs, but only at
one or more, preferably at JFETs lying further to the top.
In a further embodiment of the invention, a further diode is
connected antiparallel to the existing diode and in series with the
capacitor of the additional circuit, in at least one of the
additional circuits. This resulting activation circuit has the
effect that the capacitors of the additional circuit do not
discharge during the dynamic switching-on and the static
switched-on condition and thus the gate potentials of the upper
JFETs remain at defined potential.
In a further embodiment of the invention, the sequence of the diode
and the additional circuit in the series arrangement is the other
way round: the additional circuit is not connected between the gate
terminal and the cathode terminal, but between the gate terminal of
the respective lower JFET and the anode terminal of the respective
diode.
Basically, it is the case that the circuit in this context can be
applied in a modified manner also for p-channel JFETs instead of
the n-channel JFETs which are indicated here. Thereby,
complementarily, the drain terminal corresponds to the source
terminal and the source terminal to the drain terminal.
Further preferred embodiments are to be deduced from the dependent
patent claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject-matter of the invention is hereinafter explained in
more detail by way of preferred embodiment examples which are
represented in the accompanying drawings. In each case are
schematically shown in:
FIG. 1 a series arrangement of JFETs according to the state of the
art; and
FIG. 2 a first embodiment of the invention; and
FIG. 3 a second embodiment of the invention.
Basically, the same parts are provided with the same reference
numerals in the figures.
DETAILED DESCRIPTION OF THE INVENTION
The invention for a switching device of a high operating voltage is
represented in FIG. 1. The switch comprises a cascode arrangement
of a MOSFET M with a first or lowermost JFET J.sub.1 and at least
one further or upper JFET J.sub.2-J.sub.n which is connected in
series to this first JFET J.sub.1. The lowermost or first JFET is
therefore activated in the cascode circuit by a MOSFET acting as a
control switch. The last JFET of the JFETs connected in series and
which is distanced furthest from the first JFET is also indicated
as the uppermost JFET J.sub.n. A circuit network 4 is arranged for
stabilising the gate voltages of the JFETs and for smoothing out
the voltage load of the JFETs. This circuit network, in each case,
between the gates of two consecutive JFETs comprises a parallel
arrangement of diodes D.sub.AV,1, D.sub.AV,2, . . . D.sub.AV,n
which are operated in the blocking direction, and an RC-circuit
R.sub.D,1, C.sub.T,1, R.sub.D,1, C.sub.T,2, . . . R.sub.D,n,
C.sub.T,n.
In each case, resistors (in FIG. 1: R.sub.GS,2-R.sub.GS,n) are
connected between the gate and the source of the upper JFETs
J.sub.2-J.sub.n, (thus not of the first JFET). One can also use
Zener diodes instead of resistors.
An additional circuit 5 is connected in each case between the gate
(G.sub.J2, G.sub.J3 . . . G.sub.Jn) and the cathode terminal
(K.sub.1, K.sub.2, . . . K.sub.n-1) of the diode of the circuit
network, for the dynamic and also static control of the gate
voltages. Each additional circuit 5 according to FIG. 2 comprises a
parallel arrangement of a Zener diode D.sub.Z, 1, D.sub.Z,2 . . .
D.sub.Z,n-1 and of a capacitor C.sub.CL, 1, C.sub.CL,2 . . .
C.sub.CL, n-1. The effect of these is that the potential at the
gate terminal of the upper JFETS is kept high and thus on the one
hand the forwards voltage of the diodes, and on the other hand the
voltage drop resulting due to the forward resistance are
compensated, and the voltage prevailing between the gate terminal
and the source terminal is preferably equal to zero or kept
slightly positive.
The capacitance or capacitor of the additional circuit, compared to
the junction capacitance of the diodes operated in the blocking
direction and to the drain-source capacitance of the respective
JFETs, is a multiple greater and due to this, when switching on,
has the effect that the stored energy cannot be completely
withdrawn and a resulting voltage across the capacitor of the
additional circuit remains and this keeps the voltage of the
respective gate high.
The circuit network leads a charging current from the gate
terminals of the JFETs (J.sub.1-J.sub.n) into the respectively
assigned storage element (junction capacitance of the diode
operated in the blocking direction and capacitance of the
RC-element of the circuit network with the additional circuit) and
thus effects a dynamic stabilisation of the JFETs connected in
series.
Other switch elements which have the same effect, e.g. only one or
two or more Zener diodes connected in series, or only one or two or
more capacitors connected in parallel, can be present in the
additional circuit instead of the Zener diode and the
capacitor.
In a preferred embodiment of the invention, the additional circuit
is not connected at each of the upper JFETs, but only at one or
more, preferably at JFETs lying further up.
FIG. 3 shows an alternative preferred embodiment of the invention,
in which further diodes D.sub.ZR,1, D.sub.ZR,2 . . . D.sub.ZR, n-1
are each connected in series to the capacitor and antiparallel to
the diode of the additional circuit.
It is basically the case for the invention as a whole, that the
circuit can also be applied in a modified manner for p-channel
JFETs instead of the n-channel JFETs indicated here.
* * * * *