U.S. patent number 8,884,584 [Application Number 13/726,720] was granted by the patent office on 2014-11-11 for multi-series battery control system.
This patent grant is currently assigned to Shin-Kobe Electric Machinery Co., Ltd.. The grantee listed for this patent is Akihiko Emori, Tatsuo Horiba, Akihiko Kudo, Kazuyoshi Sasazawa, Shigeyuki Yoshihara. Invention is credited to Akihiko Emori, Tatsuo Horiba, Akihiko Kudo, Kazuyoshi Sasazawa, Shigeyuki Yoshihara.
United States Patent |
8,884,584 |
Emori , et al. |
November 11, 2014 |
Multi-series battery control system
Abstract
A multi-series battery control system comprises a plurality of
unit battery cell of which unit consists of multiple battery cells
connected in series; a plurality of control IC comprising a control
circuit for controlling the unit battery cell; a main controller
that sends and receives signal to/from the control ICs via an
insulation; means for sending an abnormality signal, which
represents the existence or the absence of abnormality of the
control ICs or the battery cells, to the main controller from the
control ICs, responding to the first signal outputted from the main
controller via the insulation; and means for searching contents of
the abnormality in the control ICs or the battery cells and sending
the abnormality contents signal based on the search, to the main
controller from the control ICs, responding to the second signal
outputted from the main controller via the insulation.
Inventors: |
Emori; Akihiko (Hitachi,
JP), Yoshihara; Shigeyuki (Hitachinaka,
JP), Sasazawa; Kazuyoshi (Hitachinaka, JP),
Horiba; Tatsuo (Fukaya, JP), Kudo; Akihiko
(Hitachinaka, JP) |
Applicant: |
Name |
City |
State |
Country |
Type |
Emori; Akihiko
Yoshihara; Shigeyuki
Sasazawa; Kazuyoshi
Horiba; Tatsuo
Kudo; Akihiko |
Hitachi
Hitachinaka
Hitachinaka
Fukaya
Hitachinaka |
N/A
N/A
N/A
N/A
N/A |
JP
JP
JP
JP
JP |
|
|
Assignee: |
Shin-Kobe Electric Machinery Co.,
Ltd. (Tokyo, JP)
|
Family
ID: |
35186348 |
Appl.
No.: |
13/726,720 |
Filed: |
December 26, 2012 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20130207609 A1 |
Aug 15, 2013 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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12415775 |
Mar 31, 2009 |
8339099 |
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11117480 |
Apr 29, 2005 |
7511457 |
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Foreign Application Priority Data
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Apr 30, 2004 [JP] |
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2004-135022 |
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Current U.S.
Class: |
320/116;
320/118 |
Current CPC
Class: |
B60L
3/0069 (20130101); B60L 58/15 (20190201); H02J
7/0048 (20200101); G01R 31/3835 (20190101); H02J
7/007 (20130101); B60L 58/24 (20190201); B60L
58/18 (20190201); B60L 53/51 (20190201); H02J
7/0016 (20130101); B60L 50/64 (20190201); B60L
53/14 (20190201); B60L 58/22 (20190201); B60L
50/16 (20190201); B60L 58/14 (20190201); H02J
7/0047 (20130101); B60L 58/19 (20190201); H02J
7/0021 (20130101); B60L 3/0046 (20130101); Y02T
90/16 (20130101); H02J 3/32 (20130101); Y02E
60/00 (20130101); Y02T 10/70 (20130101); Y02T
90/12 (20130101); B60L 2240/547 (20130101); B60L
2240/545 (20130101); Y02T 10/7072 (20130101); Y04S
10/126 (20130101); Y02T 90/14 (20130101); B60L
2210/40 (20130101); Y02T 10/72 (20130101); B60L
2240/549 (20130101); B60L 2240/80 (20130101) |
Current International
Class: |
H02J
7/00 (20060101) |
Field of
Search: |
;320/116,118,134-136 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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63-314939 |
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Dec 1988 |
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JP |
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2002-25628 |
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Jan 2002 |
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JP |
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2003-32907 |
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Jan 2003 |
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JP |
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2003-070179 |
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Mar 2003 |
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JP |
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2003-217681 |
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Jul 2003 |
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JP |
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2000-014027 |
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Jan 2007 |
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JP |
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Other References
Office Action in Japanese patent application JP2010-215188, mailed
Jun. 19, 2012 (2 pgs, in Japanese), partial English language
translation (2 pgs). cited by applicant .
Office Action in U.S. Appl. No. 13/724,828, dispatched Oct. 10,
2013. cited by applicant.
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Primary Examiner: Berhanu; Samuel
Attorney, Agent or Firm: Antonelli, Terry, Stout &
Kraus, LLP.
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation application of U.S. application
Ser. No. 12/415,775, filed Mar. 31, 2009, which, in turn, is a
continuation application of U.S. application Ser. No. 11/117,480,
filed Apr. 29, 2005 (now U.S. Pat. No. 7,511,457); and which
application claims priority from Japanese application serial No.
2004-135022, filed on Apr. 30, 2004, the contents of which are
hereby incorporated by reference into this application.
Claims
What is claimed is:
1. A battery system, comprising: a battery cell control unit that
detect a terminal voltage of each of the plurality of battery cells
and adjust a state of charge of each of the plurality of battery
cells; a power supply unit that supplies an electric power; a
controller that outputs a signal to the battery cell control unit
and the power supply unit; and an insulation unit that electrically
insulates the battery cell control unit from the controller, and
transmits a signal outputted from the controller to the battery
cell control unit by being driven with the electric power supplied
from the power supply unit, wherein: the controller outputs a first
starting signal to the power supply unit to turn on the power
supply unit and outputs a second starting signal to turn on the
battery cell control unit via the insulation unit; the power supply
unit starts supplying the electric power to the insulation unit by
being turned on in response to the first starting signal; the
battery cell control unit is turned on by receiving the second
starting signal via the insulation unit after the controller
outputs the first signal to the power supply unit and the
insulation unit is turned on by the electric power from the power
supply unit.
2. A battery system, comprising: a plurality of unit battery cells
that are electrically connected in series and each include a
plurality of battery cells that are electrically connected in
series; a plurality of battery-cell-control integrated circuits
that are provided to respectively correspond to the plurality of
unit battery cells, each are used to detect a state of each of a
plurality of battery cells of a corresponding unit battery cell and
adjust a state of charge of each of the plurality of battery cells,
and each include a signal input terminal to input a signal and a
signal output terminal to output a signal; a plurality of
battery-cell-monitor integrated circuits that are respectively
paired with the plurality of battery-cell-control integrated
circuits, each are connected with a plurality of battery cells that
are connected with a corresponding paired battery-cell-control
integrated circuit, each are used to monitor the plurality of
battery cells connected with the corresponding paired
battery-cell-control integrated circuit, and each include a signal
input terminal to input a signal and a signal output terminal to
output a signal; a controller that outputs a signal to the
plurality of battery-cell-control integrated circuits and to the
plurality of battery-cell-monitor integrated circuits; a first
signal transmission line via which a signal is transmitted in
series through the plurality of battery-cell-control integrated
circuits is provided among the plurality of battery-cell-control
integrated circuits so that a signal is outputted from a signal
output terminal of a 1st battery-cell-control integrated circuit
based upon a signal inputted at a signal input terminal of the 1st
battery-cell-control integrated circuit to be inputted at a signal
input terminal of a 2nd battery-cell-control integrated circuit; a
second signal transmission line via which a signal is transmitted
in series through the plurality of battery-cell-monitor integrated
circuits is provided among the plurality of battery-cell-monitor
integrated circuits so that a signal is outputted from a signal
output terminal of a 1st battery-cell-monitor integrated circuit
based upon a signal inputted at a signal input terminal of the 1st
battery-cell-monitor integrated circuit to be inputted at a signal
input terminal of a 2nd battery-cell-monitor integrated circuit;
and a third signal transmission line that is provided between a
first battery-cell-control integrated circuit among the plurality
of integrated circuits, which receives a signal outputted from the
controller, and the controller; and a fourth signal transmission
line that is provided between a first battery-cell-monitor
integrated circuit among the plurality of integrated circuits,
which receives a signal outputted from the controller, and the
controller, wherein: the third signal transmission line is
electrically insulated between the controller and the first
battery-cell-control integrated circuit by a first insulation unit;
the fourth signal transmission line is electrically insulated
between the controller and the first battery-cell-monitor
integrated circuit by a second insulation unit; the first
insulation unit is operated with an electric power supplied from
the first battery-cell-monitor integrated circuit a first starting
signal outputted from the controller is transmitted to the first
battery-cell-monitor integrated circuit via the second insulation
unit, then the first battery-cell-monitor integrated circuit is
turned on, then the first insulation unit is turned on with an
electric power which is supplied to the first insulation unit from
the first battery-cell-monitor integrated circuit, then a second
starting signal outputted from the controller is transmitted to the
first battery-cell-control integrated circuit via the first
insulation unit, and then the first battery-cell-control integrated
circuit is turned on.
3. A battery system according to claim 2, wherein: the first
starting signal transmitted to the first battery-cell-monitor
integrated circuit is sequentially transmitted through a plurality
of other battery-cell-monitor integrated circuits via the second
transmission line, and the plurality of other battery-cell-monitor
integrated circuits are sequentially turned on.
4. A battery system according to claim 2, wherein: the second
starting signal transmitted to the first battery-cell-control
integrated circuit is sequentially transmitted through a plurality
of other battery-cell-control integrated circuits via the first
transmission line, and the plurality of other battery-cell-control
integrated circuits are sequentially turned on.
5. A battery system according to claim 2, further comprising: a
fifth signal transmission line that is provided between a second
battery-cell-control integrated circuit among the plurality of
battery-cell-control integrated circuits, which outputs a signal to
the controller, and the controller; and a sixth signal transmission
line that is provided between a second battery-cell-monitor
integrated circuit among the plurality of battery-cell-monitor
integrated circuits, which outputs a signal to the controller, and
the controller, wherein: the fifth signal transmission line is
electrically insulated between the controller and the second
battery-cell-control integrated circuit by a third insulation unit;
the sixth signal transmission line is electrically insulated
between the controller and the second battery-cell-monitor
integrated circuit by a fourth insulation unit; the third
insulation unit is operated with an electric power supplied from
the second battery-cell-monitor integrated circuit; the first
starting signal transmitted to the first battery-cell-monitor
integrated circuit is sequentially transmitted through a plurality
of other battery-cell-monitor integrated circuits via the second
transmission line, and the plurality of other battery-cell-monitor
integrated circuits are sequentially turned on; the second starting
signal transmitted to the first battery-cell-control integrated
circuit is sequentially transmitted through a plurality of other
battery-cell-control integrated circuits via the first transmission
line, and the plurality of other battery-cell-control integrated
circuits are sequentially turned on; and the third insulation unit
is turned on with an electric power which is supplied to the third
insulation unit from the second battery-cell-monitor integrated
circuit, and then the second starting signal is transmitted from
the second battery-cell-monitor integrated circuit to the
controller via the third insulation unit.
6. A battery system according to claim 5, wherein: the controller
confirms by receiving the first starting signal and the second
starting signal whether or not the plurality of
battery-cell-control integrated circuits and the plurality of
battery-cell-monitor integrated circuits are correctly turned
on.
7. A battery-cell-monitor integrated circuit that is provided to
correspond to a plurality of battery cells that are electrically
connected in series, is paired with a first integrated circuit that
is connected with terminals of the plurality of battery cells, is
electrically connected with the plurality of battery cells
connected with the paired first integrated circuit, and is used to
monitor the plurality of battery cells connected with the paired
first integrated circuit, comprising: a signal input terminal to
input a starting signal; and a power supply unit that supplies an
electric power to an insulation unit connected with the paired
first integrated circuit, wherein: the battery-cell-monitor
integrated circuit is turned on in response to receiving the
starting signal at the signal input terminal, and then the power
supply unit supplies the electric power to the insulation unit.
8. A battery-cell-monitor integrated circuit that is provided to
correspond to each of a plurality of unit battery cells that are
electrically connected in series and each include a plurality of
battery cells that are electrically connected in series, is paired
with a first integrated circuit that is connected with terminals of
the plurality of battery cells of a corresponding unit battery
cell, is electrically connected with the plurality of battery cells
connected with the paired first integrated circuit, and is used to
monitor the plurality of battery cells connected with the paired
first integrated circuit, comprising: a signal input terminal to
input a starting signal; and a power supply unit that supplies an
electric power to an insulation unit connected with the paired
first integrated circuit, wherein: the battery-cell-monitor
integrated circuit is turned on in response to receiving the
starting signal at the signal input terminal, and then the power
supply unit supplies the electric power to the insulation unit.
Description
BACKGROUND OF THE INVENTION
The present invention relates to secondary battery (lithium
battery) for vehicle or for power supply, particularly to a
multi-series battery control system for managing the condition of
the secondary battery (lithium battery).
In order to solve a problem that higher precision voltage sensing
involves cost increase of insulation means installed for each of
multiple lower control units, there has been proposed a storage
battery unit aiming at cost reduction by reducing the number of
insulation means, for example, refer to Japanese Patent Laid-open
2003-70179, especially pages 3-4, FIG. 1. This Patent Document aims
to lower the effect of disturbance such as noise and thereby
improve reliability and enable higher precision voltage
sensing.
SUMMARY OF THE INVENTION
A conventional storage battery unit is so constructed as to
comprise multiple series-connected battery modules, each consisting
of multiple series-connected storage batteries, multiple lower
control units that are provided corresponding respectively to the
multiple battery modules and control the multiple storage batteries
constituting the battery module, and upper control unit that
controls the multiple lower control units, wherein there are
provided an input terminal of the lower control unit positioned at
the maximum potential among the multiple lower control units and
output terminal of the lower control unit positioned at the minimum
potential, insulation means or potential conversion means that
connects the upper control unit, and cutout device that is
installed between the output terminal of the lower control unit and
storage battery in the battery module on the lower potential side
and cuts out the discharge current from the storage battery in the
battery module, and signal input/output terminals of the multiple
lower control units are connected with each other, electrically not
insulated.
This conventional storage battery unit is not satisfactory in view
of high reliability.
An object of the present invention is to offer a multi-series
battery control system that can realize high reliability.
In an aspect of the invention, a multi-series battery control
system comprising: a plurality of unit battery cells of which unit
consists of multiple battery cells connected in series; a plurality
of control ICs each comprising a control circuit for controlling
the unit battery cell; a main controller that sends and receives
signal to/from the control ICs via an insulation; means for sending
an abnormality signal, which represents the existence or the
absence of abnormality of the control ICs or the battery cells, to
the main controller from the control ICs, responding to the first
signal outputted from the main controller via the insulation; and
means for sending an abnormality contents signal of the control ICs
or the battery cells, to the main controller from the control ICs,
responding to the second signal outputted from the main controller
via the insulation.
In another aspect of the invention, A multi-series battery control
system comprising: a plurality of unit battery cells of which unit
consists of multiple battery cells connected in series; a plurality
of control IC chips comprising a control circuit for controlling
the unit battery cell; a plurality of cell monitor IC chips each
monitoring the voltage of the unit battery cell; a plurality of
control ICs each consisting of the control IC chip and the cell
monitor IC chip; a main controller that sends and receives signal
to/from the control IC chips via an insulation; means for sending
an abnormality signal, which represents the existence or the
absence of abnormality of the control IC chips or the battery
cells, to the main controller from the control IC chips, responding
to the first signal outputted from the main controller via the
insulation; and means for sending the abnormality contents signal
of the control IC chip or the battery cells, to the main controller
from the control IC chips, responding to the second signal
outputted from the main controller via the insulation.
According to a preferred embodiment of the present invention, a
high reliability multi-series battery control system can be
realized.
Other objects and features of the present invention are described
hereunder along with preferred embodiments.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a diagram showing an embodiment of the multi-series
battery control system of the present invention.
FIG. 2 is a detailed circuit diagram of the control IC chip shown
in FIG. 1.
FIG. 3 is a block diagram showing a concrete embodiment of the
voltage sensing means shown in FIG. 2.
FIG. 4 is a diagram showing an embodiment of communication
command.
FIG. 5 is a chart showing the wake-up sequence in starting up the
system.
FIG. 6A-6J is a chart showing the sent/received wake-up signals on
each control IC shown in FIG. 5.
FIG. 7 is a chart showing an FF-TEST subroutine.
FIG. 8 is a chart showing a balancing subroutine for switching the
balancing switch.
FIG. 9 is a flow chart showing an operation flow for testing
abnormality of battery cell or IC chip.
FIG. 10 is a chart for explaining how communication signal is
sensed in each control IC.
FIG. 11 is a diagram showing a case where the invention is employed
in combination with a commercial power source.
FIG. 12 is a diagram showing a case where the invention is applied
to a motor generator.
DETAILED DESCRIPTION OF THE INVENTION
The present invention can be realized by monitoring multiple
series-connected battery cells as a unit and managing the condition
of a battery so as to sense abnormality of IC chip circuit or
battery cell and take appropriate measures.
Embodiment 1
An embodiment of the multi-series battery control system according
to the present invention is described hereunder in detail.
FIG. 1 shows the construction of the multi-series battery control
system of the present invention.
In FIG. 1, a battery system 1 is so constructed that a unit battery
cell 2 comprising four series-connected battery cells 2A, 2B, 2C,
2D is provided with a corresponding paired control IC 3 (control IC
chip 3A and cell monitor IC chip 3B). The paired control IC 3
consists of two ICs: one is the control IC chip 3A that contains a
control circuit and the other is the cell monitor IC chip that
monitors the unit battery cell. One end of the control IC chip 3A
is connected with each terminal of the battery cells 2A, 2B, 2C, 2D
of the unit battery cell 2. The other end of the control IC chip 3A
is connected with a main controller 5 via a high-speed insulation
means 4. The main controller 5 is connected with one end of the
cell monitor IC chip 3B via insulation means 6 and 7. The other end
of the cell monitor IC chip 3B is connected with each terminal of
the battery cells 2A, 2B, 2C, 2D.
The paired control IC 3 is provided for each unit battery cell
comprising four battery cells. Although FIG. 1 shows only three
paired ICs, the number of paired ICs 3 is the same number of units
of all battery cells of a lithium battery where one unit comprises
four battery cells.
FIG. 2 shows a detailed circuit of the control IC chip 3A. Although
the figure shows the control IC chip 3A only, the other control IC
chip 4A, 5A . . . have the same construction. Moreover, the cell
monitor IC chips 3B-5B in FIG. 1 can also completely be constituted
using the same IC chip. Then, in the following explanation, FIG. 2
is referred to also to explanation of the cell monitor IC chips
3B-5B.
In FIG. 2, the (+) terminal of the battery cell 2A of the unit
battery cell 2 is connected with a selection means 20 via the V1
input terminal. This selection means 20 is a multiplexer, for
example. The selection means is provided with switches 20A, 20B,
20C, 20D, 20E. One end of the switch 20A is connected with the V1
input terminal and the other end of the switch 20A is connected
with a power supply 21 and voltage sensing means 22. In addition,
the (-) terminal of the battery cell 2A of the unit battery cell 2,
which is the (+) terminal of the battery cell 2B, is connected with
one end of the switch 20B of the selection means 20 via the V2
input terminal and the other end of the switch 20B is connected
with the voltage sensing means 22.
In addition, the (-) terminal of the battery cell 2B of the unit
battery cell 2, which is the (+) terminal of the battery cell 2C,
is connected with one end of the switch 20C of the selection means
20 via the V3 input terminal and the other end of the switch 20C is
connected with the voltage sensing means 22. Furthermore, the (-)
terminal of the battery cell 2C of the unit battery cell 2, which
is the (+) terminal of the battery cell 2D, is connected with one
end of the switch 20D of the selection means 20 via the V4 input
terminal and the other end of the switch 20D is connected with the
voltage sensing means 22.
The (-) terminal of the battery cell 2D of the unit battery cell 2
is connected with one end of the switch 20E of the selection means
20 via the GND (ground) terminal and the other end of the switch
20E is connected with the voltage sensing means.
The power supply 21 is constructed for example as a DC/DC
converter, which is made using the unit battery cells so as to
convert the power of the unit battery cell 2 to a specified voltage
and supply to the outside through the VDD terminal and also to
supply drive power to each circuit in the control IC chip 3A.
The voltage sensing means 22 senses each terminal-to-terminal
voltage between the battery cells 2A, 2B, 2C, 2D of the unit
battery cell 2, and the sensed terminal-to-terminal voltage between
the battery cells 2A, 2B, 2C, 2D is outputted to a calculation
means 23. The calculation means comprises a power supply management
means 24, storage means 25 and correction means 26. The power
supply management means 24 controls ON/OFF of the power supply
21.
The storage means 25 stores each terminal-to-terminal voltage
between the battery cells 2A, 2B, 2C, 2D of the unit battery cell 2
sensed by the voltage sensing means 22 separately for each battery
cell 2A, 2B, 2C, 2D. To be concrete, the storage means 25 is
constructed as a shift register. The correction means 26 corrects
each terminal-to-terminal voltage between the battery cells 2A, 2B,
2C, 2D of the unit battery cell 2 sensed by the voltage sensing
means 22.
The calculation means 23 is connected with a communication means
27. The communication means 27 receives through the RX terminal via
the high-speed insulation means 4 a communication command (such as
8-bit, 10-bit or 12-bit ON/OFF signal) sent from the main
controller 5. That is to say, the main controller 5 sends out a
command for operating a specified control IC chip 3A to the
high-speed insulation means 4, including a communication command
for reading the voltage between each battery cell 2A, 2B, 2C, 2D or
communication command for adjusting the voltage between each
battery cell 2A, 2B, 2C, 2D of a specified unit battery cell 2. The
high-speed insulation means 4 does not send out the communication
command received from the main controller 5 directly to the
communication means 27 but via the insulation means.
The high-speed insulation means 4 is a transformer type and as
small as an IC. Being a transformer type, the high-speed insulation
means 4 needs power and is driven by power supplied from the cell
monitor chip 3B.
The communication means 27 generates a communication command (such
as 10-bit or 12-bit ON/OFF signal), corresponding to the
communication command sent from the main controller 5 via the
high-speed insulation means 4, by the voltage of eight battery
cells, that is, two series-connected unit battery cells and outputs
it to the calculation means 23.
How communication signal is sensed in each control IC chip 3A, 4A,
. . . 5A is described hereunder, using FIG. 10.
In FIG. 10, among the control IC chip 3A, control IC chip 4A, . . .
control IC chip 5A, communication signal is judged by the control
IC chip 3A and control IC chip 4A, and the control IC chip 4A and
control IC chip 5A. In the control IC chip 3A in FIG. 10, a VCC3
voltage level signal (Hi/Low signal of the VCC3 voltage level), of
which Hi is the total voltage of the sum of each voltage of battery
cells 2A, 2B, 2C, 2D of the unit battery cell 2 and Low is the GND
(ground) level, is inputted into the RX terminal of the control IC
chip 3A. The VCC3 voltage level signal inputted into the RX
terminal of the control IC chip 3A is outputted from the TX
terminal of the control IC chip 3A but the voltage is divided by a
resistor, and so a divided VCC3 voltage level signal (Hi/Low signal
of the VCC3 voltage level divided to 1/2 for example) is inputted
into the RX terminal of the control IC chip 4A. That is, the
communication signal is inputted into the RX terminal of the
control IC chip 4A as a signal for example repeating Hi/Low of the
VCC3 voltage level divided to 1/2. If the control IC chip 4A
attempts to judge the signal outputted from the TX terminal of the
control IC chip 3A using the same threshold as for the control IC
chip 3A based on each voltage of the unit battery cell 2 under its
control, judgment is impossible because the Low level of the signal
outputted from the TX terminal of the control IC chip 3A is half
the total voltage applied to the control IC chip 4A.
That is to say, in FIG. 10, the RX terminal voltage of the control
IC chip 3A ranges VCC3 to GND3. The RX terminal voltage of the
control IC chip 4A ranges (VCC3 to GND4).times.R/2R because the
voltage outputted from the TX terminal of the control IC chip 3A is
divided to 1/2 by a resistor. The TX terminal voltage of the
control IC chip 4A ranges VCC4 to GND4. The RX terminal voltage of
the control IC chip 5A ranges (VCC4 to GND5).times.R/2R because the
voltage outputted from the TX terminal of the control IC chip 4A is
divided to 1/2 by a resistor.
Accordingly, both input and output (RX and TX) of the highest
control IC chip 3A ranges VCC to GND. The threshold of the highest
control IC chip 3A for judging Hi/Low of the input (RX) is
therefore 1/2 VCC. The output (TX) of other control IC chips (4A, .
. . 5A) than the highest control IC chip 3A ranges VCC to 1/2 VCC.
Accordingly, for smooth operation, the threshold of each control IC
chip 4A, . . . 5A for judging Hi/Low of the input (RX) shall be
nothing but 3/4 VCC.
In addition, the (+) terminal of the battery cell 2A of the unit
battery cell 2 is connected with the B1 terminal via a resistor R1.
This B1 terminal is connected with one end of the SW condition
sensing means 28A and the other end of the SW condition sensing
means 28A is connected with the (-) terminal of the battery cell 2A
of the unit battery cell 2 via the V2 terminal. And, a balancing
switch 29A series-connected with the resistor R1 is inserted
between the two terminals of the battery cell 2A of the unit
battery cell 2.
In addition, the (+) terminal of the battery cell 2B of the unit
battery cell 2 is connected with the B2 terminal via a resistor R2.
This B2 terminal is connected with one end of the SW condition
sensing means 28B and the other end of the SW condition sensing
means 28B is connected with the (-) terminal of the battery cell 2B
of the unit battery cell 2 via the V3 terminal. And, a balancing
switch 29B series-connected with the resistor R2 is inserted
between the two terminals of the battery cell 2B of the unit
battery cell 2.
In addition, the (+) terminal of the battery cell 2C of the unit
battery cell 2 is connected with the B3 terminal via a resistor R3.
This B3 terminal is connected with one end of the SW condition
sensing means 28C and the other end of the SW condition sensing
means 28C is connected with the (-) terminal of the battery cell 2C
of the unit battery cell 2 via the V4 terminal. And, a balancing
switch 29C series-connected with the resistor R3 is inserted
between the two terminals of the battery cell 2C of the unit
battery cell 2.
Furthermore, the (+) terminal of the battery cell 2D of the unit
battery cell 2 is connected with the B4 terminal via a resistor R4.
This B4 terminal is connected with one end of the SW condition
sensing means 28D and the other end of the SW condition sensing
means 28D is connected with the (-) terminal of the battery cell 2D
of the unit battery cell 2. And, a balancing switch 29D
series-connected with the resistor R4 is inserted between the two
terminals of the battery cell 2D of the unit battery cell 2.
These SW condition sensing means 28A, 28B, 28C, 28D sense the
voltage between both ends of the balancing switches 29A to 29D,
respectively. They also sense abnormality of the balancing switches
29A, 29B, 29C, 29D. That is to say, if the terminal voltage of the
battery cells 2A, 2B, 2C, 2D is outputted while the balancing
switches 29A, 29B, 29C, 29D are ON, the balancing switches 29A,
29B, 29C, 29D can be judged abnormal. These SW condition sensing
means 28A, 28B, 28C, 28D are a voltage sensing circuit comprising a
differential amplifier.
These balancing switches 29A, 29B, 29C, 29D are switches that
short-circuits each battery cell via the resistor R1, resistor R2,
resistor R3, and resistor R4 respectively so as to discharge the
series-connected battery cells 2A, 2B, 2C, 2D constituting the unit
battery cell 2 and match the battery cell voltage of the four
battery cells 2A, 2B, 2C, 2D constituting the unit battery cell
with each other. To be concrete, they are constructed as a MOS type
FET. In addition, the SW condition sensing means 28A senses whether
the balancing switch 29A is operating correctly, SW condition
sensing means 28B senses whether the balancing switch 29B is
operating correctly, SW condition sensing means 28C senses whether
the balancing switch 29C is operating correctly, and SW condition
sensing means 28D senses whether the balancing switch 29D is
operating correctly. That is, the SW condition sensing means 28A to
28D continuously monitor the voltage of the balancing switches 29A
to 29D, and when the balancing switches 29A, 29B, 29C, 29D are
turned ON, the SW condition sensing means 28A, 28B, 28C, 28D sense
a voltage near 0 (zero), respectively.
A potential conversion means 30 is connected with these SW
condition sensing means 28A, 28B, 28C, 28D. The potential
conversion means 30 convert the voltage between each battery cell
2A, 2B, 2C, 2D sensed by the SW condition sensing means 28A, 28B,
28C, 28D to a specific potential (potential suitable for
processing) and output it to a comparison means 31. That is, since
the potential levels between each battery cell 2A, 2B, 2C, 2D are
different, the potential conversion means 30 converts them to such
potential levels that can be compared with each other.
The comparison means 31, into which a drive signal of a SW drive
means 33 is inputted, compares the drive signal with the voltage,
which is the voltage between each balancing switches 29A, 29B, 29C,
29D sensed by the SW condition sensing means 28A, 28B, 28C, 28D,
and converted into a specific voltage (potential suitable for
processing) and outputted from the potential conversion means 30,
and judges whether the balancing switches 29A, 29B, 29C, 29D are
normal or abnormal.
On the other hand, a signal for driving the balancing switch 29A is
inputted via the BS1 terminal, signal for driving the balancing
switch 29B is inputted via the BS2 terminal, signal for driving the
balancing switch 29C is inputted via the BS3 terminal, and signal
for driving the balancing switch 29D is inputted via the BS4
terminal from the main controller 5 into the SW drive means 33,
respectively. The SW drive means 33 converts the switch signal sent
from the main controller 5 into each switch drive signal and
outputs it to the comparison means 31 connected with the SW drive
means and potential conversion means 32.
The potential conversion means 32 receives the switch drive signal
sent from the SW drive means 33, converts it to a drive voltage
signal (to be concrete, a gate signal) for turning ON/OFF the
balancing switches 29A, 29B, 29C, 29D, and supplies it (to be
concrete, supplies a gate voltage) to the balancing switches 29A,
29B, 29C, 29D
When abnormality of the balancing switches 29A, 29B, 29C, 29D is
sensed by the comparison means 31, it identifies which balancing
switch 29A, 29B, 29C, 29D is abnormal based on the switch drive
signal outputted from the SW drive means 33 and outputs the result
to the calculation means 23. When abnormality is sensed by the
comparison means 31, the calculation means 23 identifies an
abnormal balancing switch and sends a signal informing the
abnormality is sent to the main controller 5 from the FFO terminal
of the communication means 27 or TX terminal of the communication
means 27.
In FIG. 2, the BS1 to BS4 terminals in the SW drive means 33 are
used to input a signal for turning ON the balancing switches 19A to
19D from the outside, and the signal inputted from these terminals
BS1 to BS4 drives the SW drive means 33 and the SW drive means 33
sends out an ON signal of the balancing switches 19A to 19D to the
potential conversion means 32. The potential conversion means 32
receives the switch drive signal sent from the SW drive means 33,
converts it to a drive voltage signal (to be concrete, a gate
signal) for turning ON the balancing switches 29A, 29B, 29C, 29D,
and supplies it (to be concrete, supplies a gate voltage) to the
balancing switches 29A, 29B, 29C, 29D.
34 in FIG. 2 is a temperature abnormality sensing means, and the
temperature abnormality sensing means 34 senses the temperature of
the control IC chip 3A, checking whether it reaches a preset
temperature. If the temperature abnormality sensing means 34 senses
a temperature in excess of the preset temperature, it sends out a
signal to the SW drive means 33 so as to stop supplying current to
the balancing switches 29A to 29D and terminate the charging
control by the balancing switches 29A, 29B, 29C, 29D so that no
more heat is generated.
FIG. 3 shows a concrete embodiment of the voltage sensing means 22
shown in FIG. 2.
The voltage sensing means 22 in FIG. 3 is connected with the
selection means 20. The voltage sensing means 22 is provided with a
resistor 22R1 connected with the (+) terminal of the battery cells
2A, 2B, 2C, 2D of which connection is switched by the switches 20A,
20B, 20C, 20D, 20E of the selection means 20. The other end of the
resistor 22R1 is connected with one end of a resistor 22R2 and the
(-) input terminal of the operation amplifier 22OP1. The other end
of the resistor 22R2 is connected with an AC/DC converter 22A.
On the other hand, there is provided a resistor 22R3 connected with
the (-) terminal of the battery cells 2A, 2B, 2C, 2D of which
connection is switched by the switches 20A, 20B, 20C, 20D, 20E of
the selection means 20, and the other end of the resistor 22R3 is
connected with one end of a resistor 22R4 and the (+) input
terminal of the operation amplifier 22OP1. The output terminal of
the operation amplifier 22OP1 is connected with the AC/DC converter
22A. The other end of the resistor 22R4 is connected with the
ground.
The output terminal of the AC/DC converter 22A is connected with an
adder 12C via a 10-bit resistor 22B, and the adder 12C is connected
with a 16-bit resistor rolling average 22D.
Because a duplex integration type is employed as explained above,
noise content in the input voltage can be filtered. In addition,
because a 16-bit resistor rolling average is employed, resolution
can be improved and sensed value can be filtered.
FIG. 4 shows an embodiment of communication command. This
communication command is sent from the main controller 5 and
inputted to the RX terminal of the communication means 27 shown in
FIG. 2. A unit data of this communication command comprises 8 bits
and a communication command contains 5 bytes. The first 8 bits of
the communication command are a break field informing an incoming
signal, second 8 bits are a synchronous field as a signal for
synchronization, third 8 bits are an identifier equivalent to an
address showing which control IC chip 3A applies, fourth 8 bits are
a data byte showing the communication detail (control detail), and
fifth 8 bits are a checksum. These communication commands
consisting of 5 bytes are sent in series.
FIG. 5 shows the wake-up sequence in starting up the system. That
is, this wake-up sequence is the operation flow for actuating the
control IC chip 3A and cell monitor IC chip 3B in turning on the
main controller 5.
In FIG. 5, when the main controller 5 shown in FIG. 2 is turned on
(key-switch is turned on) in step 100, the main controller 5 is
initialized in step 110. After the initialization of the main
controller 5 in step 110, a wake-up signal shown in FIG. 6 (A) is
outputted from the wake-up terminal of the main controller 5 to the
RX terminal of the cell monitor IC chip 3B via the insulation means
6 in step 120. The RX terminal of the cell monitor IC chip 3B is
for waking up the cell monitor IC chip 3B and so, when a wake-up
signal is inputted to the RX terminal of the cell monitor IC chip
3B, the cell monitor IC chip 3B is actuated (wakes up). When this
cell monitor IC chip 3B wakes up, the power VCC supplied from the
battery cells 2A, 2B, 2C, 2D as shown in FIG. 6 (B) is outputted
from the VDD terminal of the cell monitor IC chip 3B.
When a wake-up signal shown in FIG. 6 (A) is outputted from the
wake-up terminal of the main controller 5 to the RX terminal of the
cell monitor IC chip 3B via the insulation means 6 in step 120, the
cell monitor IC chip 3B supplies the power VCC shown in FIG. 6 (B)
from the VDD terminal to the high-speed insulation means 4 (VDD
output) in step 140. When the power VCC shown in FIG. 6 (B) is
supplied from the VDD terminal of the cell monitor IC chip 3B to
the high-speed insulation means 4, the high-speed insulation means
4 wakes up. When the high-speed insulation means 4 wakes up, the
wake-up signal shown in FIG. 6 (D) outputted from the TX terminal
of the main controller 5 can be outputted to the RX terminal of the
control IC chip 3A.
As explained above, the cell monitor IC chip 3B wakes up when a
wake-up signal shown in FIG. 6 (A) outputted from the wake-up
terminal of the main controller 5 via the insulation means 6 is
received at the RX terminal in step 120, and a wake-up signal shown
in FIG. 6 (D) for waking up the control IC chip 3A is outputted
from the TX terminal of the main controller 5 to the RX terminal of
the control IC chip 3A via the high-speed insulation means 4 in
step 130. In step 130, a wake-up signal shown in FIG. 6 (D) for
waking up the control IC chip 3A is outputted from the TX terminal
of the main controller 5 to the RX terminal of the control IC chip
3A via the high-speed insulation means 4 in step 130, and when it
is received at the RX terminal of the control IC chip 3A, the
control IC chip 3A wakes up in step 150.
When the cell IC chip 3B is woken up by a wake-up signal shown in
FIG. 6 (A) outputted from the wake-up terminal of the main
controller 5 to the RX terminal of the cell monitor IC chip 3B via
the insulation means 6, the cell IC chip 3B copies the wake-up
signal shown in FIG. 6 (A) as a wake-up signal shown in FIG. 6 (C)
and outputs it from the RX terminal of the cell monitor IC chip 3B
to the RX terminal of the cell monitor IC chip 4B in the next
stage. The cell IC chip 4B is woken up by a wake-up signal shown in
FIG. 6 (C) outputted from the TX terminal of the cell monitor IC
chip 3B, and the cell IC chip 4B copies the wake-up signal shown in
FIG. 6 (C) outputted from the TX terminal of the cell monitor IC
chip 3B and outputs it as a wake-up signal shown in FIG. 6 (E) from
the TX terminal of the cell monitor IC chip 4B to the RX terminal
of the cell monitor IC chip 5B in the last stage. There are
multiple cell IC chips provided between the cell monitor IC chip 4B
and the cell monitor IC chip 5B in the last stage, but they are
omitted in FIG. 1.
On the other hand, the power supplied from the battery cells 2A,
2B, 2C, 2D is outputted from the VDD terminal of the cell monitor
IC chip 3B to the high-speed insulation means 4, the high-speed
insulation means 4 is turned on, and a wake-up signal shown in FIG.
6 (D) is outputted from the TX terminal of the main controller 5 to
the RX terminal of the control IC chip 3A via the high-speed
insulation means 4. When this wake-up signal shown in FIG. 6 (D) is
inputted to the RX terminal of the control IC chip 3A, the control
IC chip 3A wakes up. When the control IC chip 3A wakes up, the
control IC chip 3A copies the wake-up signal shown in FIG. 6 (D)
sent from the TX terminal of the main controller 5 and outputs it
as a wake-up signal shown in FIG. 6 (F) from the TX terminal of the
control IC chip 3A to the RX terminal of the control IC chip 4A in
the next stage.
The cell IC chip 4A is woken up by a wake-up signal shown in FIG. 6
(F) outputted from the TX terminal of the cell monitor IC chip 3A,
and the cell IC chip 4A copies the wake-up signal shown in FIG. 6
(F) outputted from the TX terminal of the cell monitor IC chip 3A
and outputs it as a wake-up signal shown in FIG. 6 (I) from the TX
terminal of the cell monitor IC chip 4A to the RX terminal of the
cell monitor IC chip 5A in the last stage. There are multiple cell
IC chips provided between the cell monitor IC chip 4A and the cell
monitor IC chip 5A in the last stage, but they are omitted in FIG.
1.
The control IC chip 3A, control IC chip 4A, . . . control IC chip
5A and the cell monitor IC chip 3B, cell monitor IC chip 4B, . . .
cell monitor IC chip 5B wake up as explained above, and the battery
management IC for managing the battery cells 2A to 2N wakes up. In
addition, there is provided a VDD terminal on each control IC chip
3A, control IC chips 4A to 5A, cell monitor IC chip 3B, and cell
monitor IC chips 4B to 5B, and so power can be supplied to the
outside by appropriate utilization of these VDD terminals.
After the cell monitor IC chip 3B wakes up as above, the cell
monitor IC chip 4B and remaining cell monitor IC chips wake up by
repeating a similar operation. The cell IC chip 5B wakes up as it
receives a wake-up signal shown in FIG. 6 (E) outputted from the TX
terminal of the cell monitor IC chip 4B at the RX terminal. When
the cell monitor IC chip 5B wakes up as it receives a wake-up
signal shown in FIG. 6 (E) outputted from the TX terminal of the
cell monitor IC chip 4B to the RX terminal of the cell monitor IC
chip 5B, the cell monitor IC chip 5B copies the wake-up signal
shown in FIG. 6 (E) and outputs it as a wake-up signal shown in
FIG. 6 (G) from the TX terminal of the cell monitor IC chip 5B to
the ANS terminal of the main controller 5.
When the cell monitor IC chip 5B wakes up, it supplies the power
VCC shown in FIG. 6 (H) from the VDD terminal to the high-speed
insulation means 8 (VDD output). When the power VCC shown in FIG. 6
(H) is supplied from the VDD terminal of the cell monitor IC chip
5B to the high-speed insulation means 8, the high-speed insulation
means 8 wakes up. When the high-speed insulation means 8 wakes up,
the high-speed insulation means 8 is turned ON and so the TX
terminal of the control IC chip 5A can communicate with the RX
terminal of the main controller 6. That is, when the high-speed
insulation means 8 wakes up, a wake-up signal shown in FIG. 6 (J)
is sent from the TX terminal of the control. IC chip 5A to the RX
terminal of the main controller 5. When the wake-up signal shown in
FIG. 6 (J) from the TX terminal of the control IC chip 5A is
received at the RX terminal of the main controller 5, the main
controller 5 confirms that the control IC chip 3A, control IC chip
4A, . . . control IC chip 5A and the cell monitor IC chip 3B, cell
monitor IC chip 4B, . . . cell monitor IC chip 5B have woken up and
the battery management IC for managing the battery cells 2A to 2N
has woken up correctly. Whether the cell monitor IC chip 3B, cell
monitor IC chip 4B, . . . cell monitor IC chip 5B have woken up is
judged by confirming that the high-speed insulation means 8 is
turned ON and a wake-up signal shown in FIG. 6 (J) is sent from the
TX terminal of the control IC chip 5A to the RX terminal of the
main controller 5 is the cell monitor IC chip 5B has woken up.
The battery management IC is provided with a high-speed insulation
means 4 on its top stage and high-speed insulation means 8 on its
bottom stage for the purpose of insulation and so it is not
grounded to chassis (power supply is lifted from the chassis).
FIG. 7 shows an FF-TEST subroutine. That is, the FF-TEST subroutine
is a processing flow for inputting a test signal from the FFI of
the cell monitor IC chip 3B and sensing abnormality in the circuits
of the cell monitor IC chips 3B to 5B.
In FIG. 7, a High signal is sent from the FF-TEST terminal of the
main controller 5 as shown in FIG. 1 to the FFI terminal of the
communication means of the cell monitor IC chip 3B shown in FIG. 1
via an insulation means 7 in step 200. When a High signal is sent
to the FFI terminal of the communication means of the cell monitor
IC chip 3B in step 200, the cell monitor IC chip 3B outputs the
High signal, without adding any processing, from the FFO terminal
to the FFI terminal of the cell monitor IC chip 4B in the next
stage. Similarly, when a High signal is sent to the FFI terminal of
the communication means of the cell monitor IC chip 4B, the cell
monitor IC chip 4B outputs the High signal, without adding any
processing, from the FFO terminal to the FFI terminal of the cell
monitor IC chip 5B in the next stage. Then, when a High signal is
sent to the FFI terminal of the communication means of the cell
monitor IC chip 5B, the cell monitor IC chip 5B outputs the High
signal, without adding any processing, from the FFO terminal to the
main controller 5. When a signal is outputted from the FFO terminal
of the communication means 27, the FF port level is judged based on
the signal sent from the FFO terminal to the main controller 5 in
step 220. When the FF port level is judged based on the signal
outputted from the FFO terminal and sent to the main controller 5
in step 220, the main controller 5 judges whether the FF port level
is High or not in step 230.
If the main controller 5 judges that the FF port level is not High
(is Low) in step 230, it takes an action needed in a case the
circuit is disconnected somewhere or the cell monitor IC chip
itself is abnormal.
If the main controller 5 judges the FF port level is High in step
230, it is necessary in step 250 to check if the returned High
signal is a signal representing normality (High signal) that has
been inputted by chance in spite of overcharging or
over-discharging. That is, in step 250, it sends a condition
(abnormality) sensing command, which is a command for sensing other
abnormality (abnormality of battery cell), to the RX terminal of
the communication means 27 provided on the control IC chip 3A. When
this condition (abnormality) sensing command is sent to the
controller 5 and RX terminal of the communication means 27 of the
control IC chip 3A, a condition (abnormality) data, which is a data
showing the current condition, is sent from the TX terminal of the
communication means 27 of the control IC chip 3A to the main
controller 5 in step 260. When this condition (abnormality) data is
sent from the TX terminal of the communication means 27 to the main
controller 5, the main controller 5 checks the condition
(abnormality) in step 270 and judges whether the condition
(abnormality) data sent from the TX terminal of the communication
means 27 is a signal indicating abnormality in step 280. In a
similar manner, it checks the condition (abnormality) of the
control IC chip 4A and control IC chip 5A and judges whether the
condition (abnormality) data sent from the TX terminal of the
communication means 27 is a signal indicating abnormality. If the
condition (abnormality) data sent from the TX terminal of the
communication means 27 is judged to be a signal indicating no
abnormality in step 280, it takes a normal action and finishes the
flow. If the condition (abnormality) data sent from the TX terminal
of the communication means 27 is judged to be a signal indicating
abnormality in step 280, it takes an action against battery
abnormality and finishes the flow.
FIG. 8 shows a balancing subroutine for switching the balancing
switches 29A, 29B, 29C, 29D. That is, this balancing subroutine is
a processing flow for discharging the series-connected battery
cells 2A, 2B, 2C, 2D constituting the unit battery cell 2 and
matching the battery cell voltage of the four battery cells 2A, 2B,
2C, 2D constituting the unit battery cell with each other.
In step 400 in FIG. 8, the main controller 5 sends each battery
cell voltage reading command, which is a command for reading the
voltage data of each battery cell 2A to 2D, to the RX terminal of
the communication means 27 in FIG. 2. When the each battery cell
voltage reading command is sent in step 400, the each battery cell
voltage reading command judges control particulars and reads the
battery cell voltage of each battery cell 2A, 2B, 2C, 2D,
periodically updated and stored in the storage means, in the
calculation means 23 of the control IC chip 3A and sends in series
each battery cell voltage data from the TX terminal to the main
controller 5. When each battery cell voltage data from the control
IC chip 3A is received, the main controller 5 finds the minimum
battery cell voltage out of each battery cell voltage data received
and calculates the minimum cell voltage so as to calculate the
discharging time of each battery cell in step 420. After
calculating the minimum cell voltage in step 420, it calculates the
ON time of each balancing switch 29A, 29B, 29C, 29D in step 430.
The ON time of each balancing switch 29A, 29B, 29C, 29D is
calculated by subtracting the minimum cell voltage from each
battery cell voltage.
In step 440, a bypass SW control (ON) command for ON control of
each balancing switch 29A, 29B, 29C, 29D is sent from the main
controller 5 to the RX terminal of the communication means 27 shown
in FIG. 2. When the bypass SW control (ON) command is sent in step
440, the bypass control (ON) command judges control particulars in
the calculation means 23 of the control IC chip 3A and drives the
SW drive means 33 so that a switch drive signal (a signal
specifying which switch to drive) is outputted from the SW drive
means 33 to the potential conversion means 32, and a selected
balancing switch out of 29A, 29B, 29C, 29D is turned ON in step
450. When the selected balancing switch out of 29A, 29B, 29C, 29D
is turned ON, one of the battery cells 2A, 2B, 2C, 2D
discharges.
When the selected balancing switch out of 29A, 29B, 29C, 29D is
turned ON in step 450, the main controller 5 counts the ON elapsed
time of each bypass SW (balancing switch) 29A, 29B, 29C, 29D in
step 460. When the ON elapsed time of each bypass SW is counted in
step 460, whether the ON elapsed time of each bypass SW (balancing
switch) 29A, 29B, 29C, 29D becomes greater than the ON time in step
470. That is, in step 470, the main controller waits until the ON
elapsed time of each bypass SW (balancing switch) 29A, 29B, 29C,
29D becomes greater than the ON time.
When the ON elapsed time of each bypass SW (balancing switch) 29A,
29B, 29C, 29D is judged greater than the ON time in step 470, a
bypass SW control (OFF) command for OFF control of each balancing
switch 29A, 29B, 29C, 29D is sent from the main controller 5 to the
RX terminal of the communication means 27 shown in FIG. 2 in step
480. When the bypass SW control (OFF) command is sent in step 480,
the bypass control (OFF) command judges control particulars in the
calculation means 23 of the control IC chip 3A and controls the SW
drive means 33 so that a switch drive signal (a signal specifying
which switch to drive) is outputted from the SW drive means 33 to
the potential conversion means 32, and a selected balancing switch
out of 29A, 29B, 29C, 29D is turned OFF in step 490. When the
selected balancing switch out of 29A, 29B, 29C, 29D is turned OFF,
one of the battery cells 2A, 2B, 2C, 2D stops discharging. A
similar operation applies to the control IC chip 4A and control IC
chip 5A.
FIG. 9 shows an operation flow for checking whether the control IC
chips 3A to 5A or each battery cell is normal or not.
To start with, in step 500, a condition (abnormality) sensing
command (the first signal) is sent from the TX terminal of the main
controller 5 to the RX terminal of the control IC chip 3A. When a
condition (abnormality) sensing command is sent from the TX
terminal of the main controller 5, the control IC chip 3A receives
the condition (abnormality) sensing command.
When the condition (abnormality) sensing command is sent from the
TX terminal of the main controller 5 in step 500, the control IC
chip 3A, control IC chip 4A, . . . control IC chip 5A receives it
in turn and the cell monitor IC chip 5B on the last stage sends it
to the main controller 5.
That is, the control IC chip 3A that has received the condition
(abnormality) sensing command adds an abnormality signal
representing the existence or the absence of abnormality in own
range, and sends the condition (abnormality) sensing command to the
RX terminal of the next control IC chip 4A. When the condition
(abnormality) sensing command is outputted from the TX terminal of
the control IC chip 3A, the control IC chip 4A receives the
condition (abnormality) sensing command and sends the condition
(abnormality) sensing command to the TX terminal of the next
control IC chip 5A. Consequently, when the control IC chip 5A on
the last stage receives the condition (abnormality) sensing command
sent from the TX terminal of the control IC chip 4A, it sends the
condition (abnormality) sensing command received through the TX
terminal of the control IC chip 5A to the RX terminal of the main
controller 5 via the insulation means 10.
When the control IC chip 3A, control IC chip 4A, . . . control IC
chip 5A receives the command in turn and the cell monitor IC chip
5B on the last stage sends it to the main controller 5 in step 510,
the main controller 5 that has received the condition (abnormality)
sensing command from the control IC chip 5A checks the condition
(abnormality) in step 520. Which of the control IC chip 3A, control
IC chip 4A, . . . control IC chip 5A or corresponding battery cells
is abnormal can be judged from the condition (abnormality) sensing
command returned to the main controller 5.
After checking the condition (abnormality) of the control IC chip
3A, control IC chip 4A, . . . control IC chip 5A in step 520, the
main controller 5 judges whether abnormality is found on any of the
control IC chips or corresponding battery cells in step 530. If it
judges no abnormality is found on any of the control IC chips or
corresponding battery cells in step 530, it finishes the flow. If
the main controller 5 judges abnormality is found on any of the
control IC chip 4A, . . . control IC chip 5A in step 530, a
condition (abnormality detail) sensing command (the second signal)
for specifying the address of the control IC chip on which
abnormality is sensed and identifying the abnormality detail is
sent from the TX terminal of the main controller 5 to the RX
terminal of the control IC chip 3A via the insulation means 7 in
step 540.
When the condition (abnormality detail) sensing command is sent
from the TX terminal of the main controller 5 in step 540, the
control IC chip 3A receives it in step 550 and then a control IC
chip having different address than the specified sends the
condition (abnormality detail) sensing command as it is to the
control IC chip on the next stage. This sending and receiving is
performed sequentially as follows: the control IC chip 3A receives
the condition (abnormality detail) sensing command through the RX
terminal and sends it from the TX terminal to the RX terminal of
the control IC chip 4A, and the control IC chip 4A sends it from
the TX terminal to the RX terminal of the control IC chip 5A, and
the control IC chip 5A sends the condition (abnormality detail)
sensing command received from the control IC chip 4A from the TX
terminal of the control IC chip 5A to the RX terminal of the main
controller 5 via the insulation means 10.
When abnormality is sensed based on the condition (abnormality
detail) sensing command that is received from the control IC chip
4A and sent from the TX terminal of the control IC chip 5A to the
RX terminal of the main controller 5 via the insulation means 9, a
signal is outputted from the Relay terminal of the main controller
5 so as to drive a relay drive circuit and turn OFF the relay.
When the control IC chip 3A, control IC chip 4A, . . . control IC
chip 5A receives the command in turn and the cell monitor IC chip
5A on the last stage sends it to the main controller 5 in step 550,
the main controller 5 having received the condition (abnormality
detail) sensing command from the control IC chip 5A checks the
abnormal portion and abnormality detail in the control IC chip 3A,
control IC chip 4A, . . . control IC chip 5A in step 560 and
finishes the flow.
The main controller 5 first sends an alert signal for sending a
signal (break field) from the TX terminal of the main controller 5
to the RX terminal of the control IC chip 3A and then sends a
synchronous signal for receiving an incoming signal synchronously,
and after that, sends out the first signal for sensing abnormality
continuously. Responding to the first signal for sensing
abnormality, an abnormality sensed signal showing abnormality is
sensed on one of the control IC chip 3A, control IC chip 4A, . . .
control IC chip 5A or corresponding battery cells is sent back with
an identified address of abnormal control IC chip. When this
abnormality sensed signal which represents the existence or the
absence of abnormality of the control IC chip or the battery cells
is received, the main controller 5 sends out the second signal for
identifying the abnormality detail based on the abnormal sensed
signal. This signal for identifying the abnormality detail
specifies which control IC chip shall send what type of
information, and the abnormality detail specifies the address and
type of data (overcharging, battery cell voltage, etc.).
As explained above, the main controller 5 collects individual
voltage of the battery cells and performs cell balancing control
upon start-up, and then sends a signal for sensing abnormality of
each control IC chip and, if abnormality is sensed, sends a signal
for identifying the abnormality detail.
In this embodiment, a multi-series battery control system comprises
a plurality of unit battery cells (2) of which unit consists of
multiple battery cells (2A-2D) connected in series; a plurality of
control IC chips (3A-5A) comprising a control circuit for
controlling the unit battery cell (2); a plurality of cell monitor
IC chips (3B-5B) each monitoring the voltage of the unit battery
cell (2); a plurality of control ICs (3) each consisting of the
control IC chip (3A-5A) and the cell monitor IC chip (3B-5B); a
main controller (5) that sends and receives signal to/from the
control IC chips (3A-5A) via an insulation (4,8); means (process in
510) for sending an abnormality signal, which represents the
existence or the absence of abnormality of the control IC chips or
the battery cells, to the main controller (5) from the control IC
chips (3A-5A), responding to the first signal (abnormality sensing
command) outputted from the main controller (5) via the insulation
(4,8); means (process in 540) for sending the abnormality contents
signal of the control IC chip or the battery cells, to the main
controller (5) from the control IC chips (3A-5A), responding to the
second signal (condition sensing command) outputted from the main
controller (5) via the insulation (4,8); and means (process in 410)
for sending voltage signals of the battery cells, to the main
controller (5) from the control IC chips (3A-5A), responding to a
voltage sensing command outputted from the main controller (5) via
the insulation (4,8).
The main controller 5 periodically senses the total voltage of the
battery cells by the voltage sensing means and collects it through
the VALL terminal of the main controller 5 via the insulation
means. It also senses the total current through the battery cells
by the current sensing means and collects it through the CUR
terminal of the main controller 5. In addition, the main controller
5 periodically sums up each cell voltage and compares the total
voltage so as to accomplish conformity diagnosis by checking if the
differential voltage is within a specified range. Since whether
this differential voltage is within a specified range or not is
always checked, nothing more is needed to adjust the balancing but
turning ON/OFF the balancing switches according to the voltage of
each battery cell.
FIG. 11 shows a case where this embodiment is employed in
combination with a commercial power source.
In the figure, 1201 is a commercial power source, 1202 is a
solar-power generation system, 1203 is a load device, 1204 is a
control converter, and 1205 is a switch.
Multiple battery cells 101 are connected in series, a battery
management IC is connected with each battery cell 101, and the
output of the battery management IC is connected with the main
controller 5 via an insulation coupler. In addition, the control
converter 1204 is connected to both ends of the row of the battery
cells 101, and the main controller 5 is connected with the MCU in
the control converter 1204.
Furthermore, the solar-power generation system 1202, load device
1203 and control converter 1204 are connected with the common
commercial power source 1201 each via a switch 1205. At the same
time, the solar-power generation system 1202, load device 1203,
control converter 1204, switch 1205 and main controller 5 are
connected with each other in both directions.
The solar-power generation system 1202 is a system that converts
the sunlight to DC current using solar cells and outputs AC current
using an inverter.
The load device 1203 includes home electric appliances such as
air-conditioner, refrigerator, microwave range, and lighting, and
electric appliances such as motor, computer, and medical devices.
The control converter 1204 is a charging/discharging device that
converts AC current to DC current or DC current to AC current. This
converter also functions as a controller for controlling the
charging and discharging as well as for controlling the above
solar-power generation system 1202 and load device 1203.
In the construction as above, if power needed for the load device
1203 cannot be fully supplied by the commercial power source 1201
and solar-power generation system 1202, power is supplied from the
battery cell 101 via the control converter 1204. When the power
supplied from the commercial power source 1201 and solar-power
generation system 1202 becomes excessive, it is stored in the
battery cell 101 via the control converter 1204.
If the terminal-to-terminal voltage of the battery cell 101 reaches
a level requiring charging or discharging to be ceased in the
course of the above operation, the main controller 5 sends a
relevant signal to the control converter 1204 and the control
converter 1204 controls charging and discharging accordingly.
With the above construction, it becomes possible to lower the
contract demand and power demand of the commercial power source
1201 and generation rating of the solar-power generation system
1202, and hence equipment cost and running cost decrease.
In addition, if power is supplied from the battery cell 101 to the
commercial power source 1201 when the power demand concentrates to
a specific time zone and stored into a storage battery when the
power demand is low, the concentration of power demand can be
moderated and the power demand can be leveled
Furthermore, since the control converter 1204 monitors the power
demand of the load device 1203 and controls the load device 1203
accordingly, energy saving and effective utilization of power can
be realized.
FIG. 12 shows a case where the embodiment is applied to a motor
generator.
If the figure, 1101 is a motor generator, 1004 is a control
converter, 1005 is a voltage regulator, and 1102 is a DC load
device (for example, power steering, electric brake, and
suction/exhaust valve timing device).
Multiple battery cells 101 are connected in series, a battery
management IC is connected with each battery cell 101, and the
output of the battery management IC is connected with the main
controller 5 via an insulation coupler. In addition, the main
controller 5 is connected with the MCU in the control converter
1004.
The motor generator 1101 is a motor that converts the generated AC
power to DC power and outputs.
With the above construction, while an automobile is driven by
engine and is moving, power is generated by the motor generator
1101 that is driven by the automobile movement via a drive belt or
directly driven by actuating an electromagnetic clutch. The power
generated by the motor generator 1101 is supplied and charged into
the battery cell 101 via the control converter 1004. Charging and
discharging of the battery cell 101 is controlled by the motor
generator 1101 through the battery management IC and via the main
controller 5. In case of discharging, power is supplied through the
battery management IC to the motor to drive the tires to rotate.
The MCU in the control converter 1004 and the system are also
connected with each other.
The main controller 5 is grounded with the ground (chassis ground)
but both ends of the battery cells 2A, 2B, 2C, 2D of the unit
battery cell 2 are lifted from the ground. The control converter
1004 is not grounded, either but lifted from the ground. In short,
the power related circuit is lifted from the ground.
If the system is actually abnormal while the main controller 5
becomes out of control and mistakenly judges normal, the relay
cannot be turned off because the main controller 5 is out of
control. If this happens, a signal is outputted from an analog
system so as to drive the relay drive circuit and turn OFF the
relay.
With this embodiment, the number of components constituting the
multi-series battery control system can be decreased.
In addition, with this embodiment, lower cost can be realized in
constructing the multi-series battery control system.
Furthermore, with this embodiment, higher reliability of the
multi-series battery control system can be realized.
Furthermore, with this embodiment, operability of the multi-series
battery control system can be improved.
Furthermore, with this embodiment, the multi-series battery control
system can be further generalized.
With this embodiment, higher-speed communication in the
multi-series battery control system can also be realized.
In addition, with this embodiment, the multi-serial battery control
system can be easily constructed and can be simplified.
According to the proper embodiments of the present invention, high
reliability can be achieved.
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