U.S. patent number 8,518,747 [Application Number 13/619,409] was granted by the patent office on 2013-08-27 for stackable semiconductor assemblies and methods of manufacturing such assemblies.
This patent grant is currently assigned to Micron Technology, Inc.. The grantee listed for this patent is Swee Kwang Chua. Invention is credited to Swee Kwang Chua.
United States Patent |
8,518,747 |
Chua |
August 27, 2013 |
**Please see images for:
( Certificate of Correction ) ** |
Stackable semiconductor assemblies and methods of manufacturing
such assemblies
Abstract
Stacked semiconductor devices and assemblies including attached
lead frames are disclosed herein. One embodiment of a method of
manufacturing a semiconductor assembly includes forming a plurality
of first side trenches to a first intermediate depth in a molded
portion of a molded wafer having a plurality of dies arranged in
rows and columns. The method also includes forming a plurality of
lateral contacts at sidewall portions of the trenches and
electrically connecting first side bond-sites of the dies with
corresponding lateral contacts of the trenches. The method further
includes forming a plurality of second side channels to a second
intermediate depth in the molded portion such that the channels
intersect the trenches. The method also includes singulating and
stacking the first and second dies with the channels associated
with the first die aligned with channels associated with the second
die.
Inventors: |
Chua; Swee Kwang (Singapore,
SG) |
Applicant: |
Name |
City |
State |
Country |
Type |
Chua; Swee Kwang |
Singapore |
N/A |
SG |
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|
Assignee: |
Micron Technology, Inc. (Boise,
ID)
|
Family
ID: |
42107988 |
Appl.
No.: |
13/619,409 |
Filed: |
September 14, 2012 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20130011966 A1 |
Jan 10, 2013 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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12982296 |
Dec 30, 2010 |
8288874 |
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12254111 |
Oct 20, 2008 |
7863722 |
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Current U.S.
Class: |
438/112; 257/787;
438/107; 438/110; 257/E23.128; 257/723 |
Current CPC
Class: |
H01L
24/96 (20130101); H01L 23/49822 (20130101); H01L
24/97 (20130101); H01L 21/561 (20130101); H01L
24/25 (20130101); H01L 24/82 (20130101); H01L
25/105 (20130101); H01L 24/24 (20130101); H01L
2924/01082 (20130101); H01L 2924/01033 (20130101); H01L
2224/24145 (20130101); H01L 2924/14 (20130101); H01L
2225/1064 (20130101); H01L 2924/01005 (20130101); H01L
2924/014 (20130101); H01L 2924/01078 (20130101); H01L
2224/97 (20130101); H01L 2225/1035 (20130101); H01L
2924/01006 (20130101); H01L 2924/12042 (20130101); H01L
2224/97 (20130101); H01L 2224/82 (20130101); H01L
2924/12042 (20130101); H01L 2924/00 (20130101) |
Current International
Class: |
H01L
21/00 (20060101) |
Field of
Search: |
;257/E21.001,E21.002,E21.499,E21.502,E21.504,E23.001,E23.128,E23.141,686,690,678,723,787
;438/106,107,110,112,113,127,464 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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102004041889 |
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Mar 2006 |
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DE |
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102005003125 |
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Jul 2006 |
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DE |
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11274354 |
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Oct 1999 |
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JP |
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20030032313 |
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Apr 2003 |
|
KR |
|
Other References
Furgut, E. et al., "Taking Wafer Level Packaging to the Next Stage:
A 200mm Silicon Technology Compatible Embedded Device Technology,"
Advanced Packaging Conference, SEMICON Europa 2006, Munich,
Germany, Apr. 4, 2006. cited by applicant.
|
Primary Examiner: Chu; Chris
Attorney, Agent or Firm: Perkins Coie LLP
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. application Ser. No.
12/982,296 filed on Dec. 30, 2010, now U.S. Pat. No. 8,288,874,
which is a continuation of U.S. application Ser. No. 12/254,111
filed on Oct. 20, 2008, now U.S. Pat. No. 7,863,722, each of which
is incorporated herein by reference in its entirety.
Claims
I claim:
1. A method of forming a semiconductor device, the method
comprising: embedding a first die in a mold material spaced apart
from a second die in the mold material; forming at least one trench
between the first and second dies in a first side of the mold
material; forming a first lateral contact on a first sidewall of
the trench and forming a second lateral contact on a second
sidewall of the trench; forming a plurality of channels in a second
side of the mold material opposite the first side; and singulating
the first and second dies, wherein singulating the first and second
dies includes-- exposing the first and second lateral contacts at
the corresponding first and second sidewalls of the trench; forming
a plurality of first extension portions projecting from the first
sidewall; and forming a plurality of second extension portions
projection from the second sidewall.
2. The method of claim 1, further comprising: stacking the first
die on the second die; and electrically coupling the first lateral
contact to the second lateral contact.
3. The method of claim 2 wherein electrically coupling the first
lateral contact to the second lateral contact comprises attaching a
lead finger to the first and second lateral contacts.
4. The method of claim 3 wherein attaching the lead finger
comprises: attaching a first contact portion of the lead finger to
the first lateral contact and positioning first alignment portions
of the lead finger adjacent to the corresponding first extension
portions; and attaching a second attachment portion of the lead
finger to the second lateral contact, wherein the second attachment
portion is spaced apart from the first attachment portion, and
positioning second alignment portions of the lead finger adjacent
to the corresponding second extension portions.
5. The method of claim 1 wherein: forming the at least one trench
comprises forming at least one trench having a first depth less
than a thickness of the mold material; and forming the plurality of
channels comprises forming the plurality of channels having
individual second depths that are less than the thickness of the
mold material, wherein the combination of the first depth and the
individual second depths is greater than the thickness of the mold
material.
6. The method of claim 1 wherein singulating the first and second
dies comprises cutting completely through the mold material in the
trench at a location spaced apart from the first and second
sidewalls.
7. The method of claim 1 wherein: forming the at least one trench
comprising forming a first trench spaced apart from a second; and
exposing the first and second lateral contacts comprises exposing
the first lateral contact at the first sidewall of the first trench
and exposing the second lateral contact at the second sidewall of
the second trench.
8. The method of claim 1 wherein: forming the plurality of first
extension portions comprises forming corresponding first extension
portions on opposite sides of the first lateral contact; and
forming the plurality of second extension portions comprises
forming corresponding second extension portions on opposite sides
of the second lateral contact.
9. The method of claim 1 wherein: embedding the first and second
dies in the mold material comprises embedding the first die having
a first bond site at the first side of the mold material and
embedding the second die having a second bond-site at the first
side of the mold material; and the method further comprises
electrically connecting the first bond-site to the first lateral
contact and electrically connecting the second bond-site to the
second lateral contact.
Description
TECHNICAL FIELD
The present disclosure relates to semiconductor devices and
assemblies, and methods for manufacturing such devices and
assemblies.
BACKGROUND
Semiconductor processing and packaging techniques are continually
evolving to meet industry demands for improved performance with
reduced size and cost. Electronic products require packaged
semiconductor assemblies with a high density of devices in a
relatively small space. For example, the space available for memory
devices, processors, displays, and other microfeature devices is
continually decreasing in personal electronic devices such as cell
phones, laptop computers, and many other products. Accordingly, a
need exists to decrease the overall size of the microfeature
devices while still maintaining or improving performance and
reducing cost.
One technique used to improve the performance and reduce the size
and cost of these microfeature devices involves wafer level
packaging ("WLP"). WLP generally refers to the packaging of
microfeature devices at the wafer level, rather than processing and
packaging individual devices after dicing them from a wafer. One
benefit of WLP is that it creates chip-sized packages having the
smallest form factor. WLP achieves these small sizes by limiting
components of the package, such as interconnect elements, to be
within the footprint or fan-in area of the device. These components
are limited within the device footprint because the components are
formed at the wafer level before the devices are singulated. WLP
also provides the benefit of producing packages having excellent
electrical and thermal performance due to the overall reduced size
of the package and relatively short length of the interconnects.
Additional advantages provided by WLP include the ease of
fabrication and reduced assembly cost due to simultaneous or
parallel processing and testing at the wafer level. Even though WLP
may provide the benefits listed above, it may not be suitable for
devices having high pin counts or high input/output requirements.
For example, the space limitation of the device footprint restricts
the number and pitch of the interconnect elements in the
package.
To overcome this problem, the dies can be diced and plated in
built-up packages that include interconnects that surround the die
and extend through a molded polymer. Although positioning these
interconnects outside of the footprint of the die can increase the
number and/or pitch of the interconnects, it can significantly
increase the cost and complexity of the processing. For example, in
certain circumstances the filling process can trap air in vias that
can cause the interconnect or package to crack as the fill material
and the package harden. Such non-uniformities in the vias provide
inconsistent electrical connections and compromise the integrity of
the interconnects and performance of the package. Additionally,
forming the vias by ablation or drilling processes typically
requires forming individual vias in a sequential manner, thus
increasing the processing time. Simultaneously forming the vias by
an etching process can be much faster, but etching can result in
inconsistent via sizes. It can also be difficult to achieve a dense
distribution of the vias with an etching process. Moreover, the
plating and filling processing steps following the formation of the
vias require additional processing time.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is an isometric view of a conventional semiconductor wafer
before singulation.
FIG. 1B is an isometric view of a molded wafer configured in
accordance with an embodiment of the disclosure.
FIG. 2A is a top isometric view and FIG. 2B is a bottom isometric
view of a semiconductor assembly configured in accordance with an
embodiment of the disclosure.
FIG. 2C is a side cross-sectional view, FIG. 2D is a top partial
view, and FIGS. 2E-2G are side cross-sectional views illustrating
various stages in a method of manufacturing a semiconductor
assembly configured in accordance with an embodiment of the
disclosure.
FIG. 3A is a top isometric view illustrating a stage in a method of
manufacturing a semiconductor device assembly configured in
accordance with an embodiment of the disclosure.
FIG. 3B is a top isometric view and FIG. 3C is a bottom isometric
view of a semiconductor assembly configured in accordance with an
embodiment of the disclosure.
FIG. 4 is a flow diagram of a process of manufacturing a
semiconductor assembly configured in accordance with another
embodiment of the disclosure.
FIG. 5 is a schematic view of a system that incorporates
semiconductor assemblies configured in accordance with further
embodiments of the disclosure.
DETAILED DESCRIPTION
Several embodiments of the present disclosure are directed toward
packaged semiconductor devices, packaged semiconductor assemblies,
and methods of forming such devices and assemblies. Many details of
the disclosure are described below with reference to specific
structures and methods of forming the devices and assemblies. The
terms "semiconductor device" and "semiconductor assembly" are used
throughout to include a variety of articles of manufacture
including, for example, semiconductor wafers having active
components, individual integrated circuit dies, packaged dies, and
semiconductor devices or assemblies in a stacked configuration.
Many specific details of certain embodiments are set forth in FIGS.
1A-5 and the following text to provide a thorough understanding of
these embodiments. Like reference characters refer to like
components in FIGS. 1A-5, and thus the description of many of these
components will not be repeated with reference to the Figures.
Several other embodiments can have different configurations,
components or processes than those described in this section. A
person skilled in the art will appreciate, therefore, that
additional embodiments may exist or that the described embodiments
may be practiced without several of the details described
below.
FIG. 1A is an isometric view of a conventional semiconductor wafer
100 having a first side 102 opposite a second side 104, and a
plurality of semiconductor devices or dies 106. The dies 106 can
include, for example, a dynamic or static random access memory, a
flash memory, a microprocessor, an imager, or another type of
application-specific integrated circuit. Individual dies 106 can
include a plurality of bond-sites 108 at the first side 102 to
electrically connect the dies 106 with other components. The
bond-sites 108 can include a staggered or aligned configuration at
the first side 102 of the dies 106. In the illustrated embodiment,
the dies 106 are delineated by boundary lines 107, and the dies 106
are processed and built up on the wafer 100 before dicing along the
boundary lines 107 to singulate the dies 106.
After singulating the dies 106 from the wafer 100, the dies 106 can
be embedded in a mold material configured in a wafer form as
illustrated in FIG. 1B. More specifically, FIG. 1B is an isometric
view of a molded wafer 110 including a first side 112 opposite a
second side 114. The molded wafer 110 is composed of a mold
material 116 that can include, for example, polymers, thermosets,
thermoplastics, hybridized versions of thermosets and
thermoplastics, or other suitable mold materials. The molded wafer
110 also includes the singulated dies 106 (individually identified
as a first die 106a, a second die 106b, a third die 106c, etc.). In
the illustrated embodiment, the bond-sites 108 are at the first
side 112 of the molded wafer 110 and the dies 106 are positioned in
a grid-like pattern and spaced apart from one other by lanes in the
mold material 116. As illustrated in FIG. 1B, for example, the
lanes between the dies can include rows 118a that run in a first
direction between the dies 106, and columns 118b that run in a
second direction between the dies 106 generally transverse to the
rows 118a. One skilled in the art will appreciate that describing
the lanes or spacing between the dies as "rows" and "columns" is
for the purpose of illustration and does not necessarily require a
horizontal or vertical configuration of the rows and columns. The
rows 118a and columns 118b in the mold material 116 provide
additional space around the dies 106 to form interconnect
structures or other components. These interconnect structures are
not typically formed between the dies 106 at the wafer 100 level
(shown in FIG. 1A) due to cost restrictions of the wafer 100
material. The assemblies and methods described below utilize the
molded wafer 110 configuration illustrated in FIG. 1B to form
interconnect structures or other features associated with the dies
106.
FIG. 2A illustrates one embodiment of a semiconductor assembly 200
that is processed and singulated from the molded wafer 110. More
specifically, FIG. 2A is a top isometric view of the semiconductor
assembly 200 including one of the dies 106 embedded in the mold
material 116. In the illustrated embodiment, the assembly 200
includes multiple redistribution structures or electrical
connectors 250 that extend from each bond-site 108 at a first side
202 of the assembly 200 to a corresponding lateral contact 256 at a
sidewall portion 218 of the assembly 200. Each electrical connector
250 can include a redistribution or conductive trace 252 that
extends from each bond-site 108 to a corresponding second bond-site
254 positioned at a peripheral edge portion of the assembly 200. In
certain embodiments, each second bond-site 254 can be a separate
contact that is electrically connected to the corresponding lateral
contact 256. In other embodiments, each second bond-site 254 can be
integrally formed (e.g., simultaneously deposited) with the
corresponding lateral contact 256.
In the illustrated embodiment, the assembly 200 also includes a
plurality of channels 220 formed in a second side 204 of the
assembly 200 opposite the first side 202. For example, FIG. 2B is a
bottom isometric view illustrating the channels 220 in the assembly
200. Referring to FIGS. 2A and 2B together, the channels 220 extend
from the second side 204 through a portion of the mold material 116
and form a plurality of spaced apart-ridges 222. In certain
embodiments, the ridges 222 can include raised features or heat
dissipation fins that extend across the width of the second side
204 between the adjacent channels 220. According to another example
of the illustrated embodiment, each ridge 222 includes an extension
portion 226 projecting laterally from the sidewall portion 218 of
the assembly 200. For example, each extension portion 226 can be a
stepped extension of the corresponding ridge 222 from the sidewall
portion 218. As explained in detail below with reference to FIGS.
2C-2G, the extension portions 226 can be created by forming the
channels 220 in the second side 204 and trenches 210 (only one of
which is shown in FIGS. 2A and 2B) in the first side 202 at the
sidewall portion 218 of the assembly 200. Moreover, each lateral
contact 256 can be disposed at an intersection between the channels
220 and the trenches 210. In this manner, each lateral contact 256
is aligned with the corresponding channel 220.
As explained in detail below, the assembly 200 incorporates the
processing benefits from WLP and the reconfigured molded wafer 110
(FIG. 1B) while still providing high quality electrical connections
that can be formed with relatively simplified processing steps. For
example, rather than ablating, etching, or drilling individual
vias, the lateral contacts 256 can be formed at intersections of
the first side trenches 210 and corresponding second side channels
220. In addition, in the embodiment shown in FIGS. 2A and 2B, each
electrical connector 250 includes the continuous conductive trace
252 extending from the corresponding first bond-site 108 to the
corresponding lateral contact 256, which provides a uniform
electrical connection without requiring the complex process of
forming, plating, and filling the vias associated with conventional
interconnects. Moreover, the extension portions 226 protruding from
the sidewall portion 218 form a generally castellated side surface
that facilitates stacking and interconnection of the assembly 200
with generally similar assemblies.
The individual assembly 200 and electrical connectors 250 have been
completely formed in the embodiment illustrated in FIGS. 2A and 2B.
FIGS. 2C-2G described below illustrate various techniques and
stages in a method of forming the assembly 200 of FIGS. 2A and 2B.
For example, FIG. 2C is a cross-sectional view of the assembly 200
along the line A-A of FIG. 1B that illustrates a stage of
processing the mold material 116 around the first and second dies
106a-b. At this stage, a portion of the mold material 116 is
removed to form one or more trenches 210 (identified individually
as a first trench 210a and second trench 210b) in the row 118a
between the first and second dies 106a-b. The trenches 210 are
formed at the first side 202 and extend to an intermediate depth in
the mold material. More specifically, the mold material 116 has a
first thickness T.sub.1, and each of the dies 106 has a second
thickness T.sub.2 that is less than the first thickness T.sub.1.
Each of the first and second trenches 210a-b has a first depth
D.sub.1 in the mold material 116 that is less than the first
thickness T.sub.1 of the mold material 116 and equal to or greater
than the second thickness T.sub.2 of the dies 106. Accordingly, the
individual trenches 210 can extend deeper into the mold material
116 than the individual dies 106 without extending through to the
second side 204 of the assembly 200.
In certain embodiments, forming the trenches 210 can include
partially dicing the mold material 116 with a cutting device 251,
such as a wafer saw, blade, laser, fluid jet, etchant, or other
tool suitable for removing controlled portions of the mold material
116. For example, to form the first and second trenches 210a-b, two
spaced-apart cutting devices 251 (only one of which is shown in
FIG. 2C) can remove the corresponding mold material 116 in a single
pass in the row 118a. In other embodiments, a single cutting device
251 can remove the mold material 116 by making multiple passes and
repositioning the cutting device and/or the wafer between passes.
Moreover, in certain embodiments a single trench 210 (rather than
first and second trenches 210a-b) can be formed in the row 118a
having a width generally the same as the width between the outer
walls of the first and second trenches 210a-b. In addition,
although the trenches 210 illustrated in FIG. 2C have a generally
rectilinear cross-sectional shape, one skilled in the art will
appreciate that that the trenches 210 can include other shapes
including, but not limited to, curved sidewalls, smooth transitions
between the sidewalls and bottoms of the trenches 210, etc.
FIG. 2D illustrates a stage after forming the trenches 210 in the
first side 202 in which conductive material is selectively applied
to form the redistribution structures or electrical connectors 250.
FIG. 2E is a side cross-sectional view taken along the line 2E-2E
of FIG. 2D. Referring to FIGS. 2D and 2E together, at this stage of
the processing the sidewalls of the trenches 210 can be plated with
conductive material to form the lateral contacts 256 in the
trenches 210. In certain embodiments, the second bond-sites 254 can
be plated and integrally formed with the lateral contacts 256. In
other embodiments, however, each second bond-site 254 can be
separately deposited and then electrically connected to the
corresponding lateral contact 256. Moreover, the conductive trace
252 can also be deposited to electrically connect each first
bond-site 108 to the corresponding second bond-site 254 and lateral
contact 256. In certain embodiments, for example, the conductive
trace 252 can be deposited or otherwise formed at the processing
stage illustrated in FIGS. 2D and 2E. In other embodiments,
however, the conductive trace 252 can be formed at the
semiconductor wafer prior to singulation (e.g., FIG. 1A).
FIG. 2F illustrates a stage after forming the trenches 210 and
electrical connectors 250 at the first side 202, and in which the
mold material 116 is selectively removed from the second side 204
to form the channels 220. More specifically, FIG. 2F is a side
cross-sectional view of the assembly 200 along the line B-B of FIG.
1B. For purposes of illustration, the assembly 200 shown in FIG. 2C
is inverted so that the second side 204 is facing up. In addition,
the dies 106 and the bond-sites 108 are out of the plane of FIG. 2C
and shown in broken lines for reference. In this configuration,
multiple second side channels 220 are formed in a direction
generally transverse to the trenches 210 described above (only one
trench 210 is shown in FIG. 2F). The channels 220 can be formed in
a manner similar to that described above with reference to the
trenches 210. In certain embodiments the channels 220 can be
generally similar to the trenches 210 and are called channels
rather than trenches for purposes of clarity in distinguishing
between the two.
In the embodiment illustrated in FIG. 2F, the channels 220 are not
formed in the column 118b between the first and second dies 106a-b,
but rather at a preselected pitch within the footprint of the
individual dies 106. In other embodiments, the channels 220 can be
formed at any preselected location at the second side 204,
including, for example, within the column 118b. The channels 220
have a second depth D.sub.2 into the mold material 116 from the
second side 204 that does not intersect the dies 106. The
combination of the first depth D.sub.1 of the trenches 210 and the
second depth D.sub.2 of the channels 220, however, is equal to or
greater than the first thickness T.sub.1 of the mold material 116.
Accordingly, the intersections between the first side trenches 210
and the second side channels 220 form a plurality of openings 224
through the mold material 116.
The configuration and method of forming the openings 224 described
above provide a relatively fast and cost-effective method of
forming the openings 224 through the mold material 116. For
example, cutting a single second side channel 220 after forming the
first side trenches 210 creates multiple openings 224 at the
intersections with only a single pass through the mold material
116. In addition, removing the mold material 116 in the trenches
210 and channels 220 uses existing methods and avoids some of the
challenges associated with conventional via techniques. For
example, drilling with a laser can create non-uniform vias having
an entry diameter that is larger than an exit diameter. Another
challenge associated with drilling a via includes unwanted melted
and resolidified mold material that can remain at the entry side of
the via. Moreover, adequately plating and filling a via having a
small aspect ratio formed by drilling techniques can also provide a
significant challenge.
Referring to FIG. 2G, the next processing step includes singulating
the first and second dies 106a-b and associated components from the
molded wafer 110 (FIG. 1B). The assemblies 200 can be singulated,
for example, by cutting the mold material 116 FIG. 1B along the
rows 118a and columns 118b between the individual dies 106 (FIG.
1B). More specifically, FIG. 2G is a side cross-sectional view
along the line A-A of FIG. 1B. In the illustrated embodiment, the
assemblies 200 can be singulated to expose the lateral contacts 256
at a peripheral edge portion of the mold material 116. The cutting
device 251 can singulate the assemblies 200 and remove a section
117 between the first and second trenches 210a-b to separate the
first die 106a from the second die 106b. Moreover, removing the
section 117 in the row 118a between the first and second trenches
210a-b forms the extension portions 226 extending laterally from
each assembly 200 (see, e.g., FIG. 2A). Exposing the lateral
contacts 256 at the sides of the assembly 200 provides locations to
electrically connect to in a later stage of the processing.
After the individual assemblies 200 have been formed and singulated
as described above with reference to FIGS. 1A-2G, they can be
assembled together in a stacked configuration. FIG. 3A, for
example, is an isometric top view illustrating a step in the
process of forming a stacked semiconductor assembly 300 configured
in accordance with an embodiment of the disclosure. In the
illustrated embodiment, the stacked assembly 300 includes multiple
assemblies 200 (identified individually as first through fourth
assemblies 200a-d) stacked on one other. In the stacked
configuration, the channels 220 of each individual assembly 200
extend through the width of the stacked assembly 300. When stacking
the assemblies 200, the channels 220 in each assembly 200 can be
aligned with the corresponding channels 220 in the adjacent
assemblies 200. Moreover, the lateral contacts 256 of each assembly
200 are also aligned with the corresponding lateral contacts 256 of
the adjacent assemblies 200. In addition, the extension portions
226 of each assembly 200 also protrude from a sidewall 361 of the
stacked assembly 300, thereby forming a grid-like or castellated
surface of the sidewall 361. In this manner, the lateral contacts
256 are externally accessible as well as aligned and spaced apart
from one other at the sidewall 361. Moreover, as explained below,
the extension portions 226 form a castellated side surface and act
as alignment features at the castellated surface of the sidewall
361.
As shown in the embodiment illustrated in FIG. 3A, the stacked
assembly 300 further includes grated lead frames 360 (identified
individually as a first lead frame 360a and a second lead frame
360b), each of which is configured to be attached to one of the
castellated sidewalls 361 of the stacked assembly 300. Each of the
lead frames 360 can be a conductive grid including a plurality of
conductors or lead fingers 362 extending from a stabilizing portion
363. In certain embodiments, each lead finger 362 can be an
elongated conductive bar. Each lead finger 362 includes multiple
contacts or attachment portions 364 positioned between alignment
portions 366. The attachment portions 364 are spaced apart along a
longitudinal axis of each lead finger 362. The alignment portions
366 extend laterally from the attachment portions 364 of each lead
finger 362. The attachment portions 364 (as well as the alignment
portions 366) are spaced apart from one another along each lead
finger 362 at a pitch matching that of the spaced-apart lateral
contacts 256 at the castellated sidewall 361. In certain
embodiments, the lead frames 360 are made from metallic materials
and can be coated with conductive materials, such as tin, solder,
or other suitable conductive materials, that can be reflowed to
connect the lead frames 360 to the sidewalls 361 of the stacked
assembly 300. In other embodiments, however, reflowable conductive
material can be deposited on the attachment portions 364 or on the
lateral contacts 256.
To attach the lead frames 360 to the stacked assembly 300, the
attachment portions 364 of the lead frames 360 are aligned with the
lateral contacts 256 at the sidewall 361, and conductive material
carried by the lead frame 360 can be reflowed to establish a
connection between the lead finger attachment portions 364 and the
lateral contacts 256 at the sidewall 361. FIG. 3B, for example, is
a top isometric view of the stacked assembly 300 after the first
lead frame 360a has been attached to the sidewall 361. As shown in
the illustrated embodiment, the alignment portions 366 of each lead
finger 362 engage the corresponding extension portions 226 and
align the first lead frame 360a at the sidewall 361 with the
corresponding extension portions 226.
After each lead frame 360 is attached to the sidewall 361 of the
stacked assembly 300, the stabilizing portion 363 of the lead frame
360 can be removed to electrically isolate the individual lead
fingers 362. As shown in FIG. 3B, for example, the stabilizing
portion 363 has been removed after attaching the lead fingers 362
to the sidewall 361 of the stacked assembly 300. Moreover, removing
the stabilizing portion 363 can form external contacts for each
lead frame 360 at the end portions of each lead finger 362. For
purposes of illustration, FIG. 3B illustrates different external
contacts in the same assembly 300. As shown towards the right side
of FIG. 3B, for example, each lead finger 362 can include a
generally planar external contact 367 (e.g., a gull-wing lead). In
other embodiments and as shown towards the left side of FIG. 3B,
each lead finger 362 can include a curved external contact 368
(e.g., a J-lead). In still further embodiments, the end portions of
the lead fingers 362 can include other suitable types of external
contacts.
FIG. 3C illustrates another embodiment of the stacked assembly 300.
More specifically, FIG. 3C is a bottom isometric view of the
stacked assembly 300. In this embodiment, however, the assemblies
200 are inverted so that the channels 220 and ridges 222 are facing
up. Moreover, the lead frames 360 are attached to the inverted
assemblies 200 at the castellated sides of the assemblies 200 with
the external contacts 367 and 368 of the lead fingers 362 facing
towards the bottom of the stacked assembly 300. Accordingly, in the
illustrated embodiment the ridges 222 of the first assembly 200a
can act as heat transfer features for heat dissipation from the
stacked assembly 300.
FIG. 4 is a flow diagram of an embodiment of a method or process
400 for forming a semiconductor assembly. In this embodiment, the
process 400 includes forming a plurality of first side trenches to
a first intermediate depth in a molded portion of a molded wafer
having a plurality of dies arranged in rows and columns (block
405). In certain embodiments, this step can include forming a
single trench in each row or column between the dies. In other
embodiments, however, this step can include forming two or more
parallel and spaced-apart trenches in each row or column between
the dies.
The process further includes forming a plurality of lateral
contacts at sidewall portions of the trenches (block 410) and
electrically connecting the first side bond-sites of the dies with
corresponding lateral contacts of the trenches (block 415). In
certain embodiments, these steps can include forming redistribution
structures forming an electrical connection between the bond-sites
of the dies and the corresponding lateral contacts. For example,
these steps can include disposing discrete amounts of conductive
material between the bond-sites and the corresponding lateral
contacts. The process further includes forming a plurality of
second side channels to a second intermediate depth in the molded
portion such that the channels intersect the trenches (block 420).
In certain embodiments, the second side channels can be generally
transverse to the first side trenches. The combination of the
depths of the first side trenches and second side channels is
greater than the thickness of the mold material of the molded
wafer.
The process further includes singulating the first and second dies
(block 425). In certain embodiments, singulating the first and
second dies includes exposes the lateral contacts at an outer
periphery of the mold material surrounding the first and second
dies. Moreover, singulating the first and second dies can include
cutting the mold material in the trenches and forming extension
portions protruding laterally from the mold material surrounding
the first and second dies. In certain embodiments the extension
portions create a castellated edge portion of the mold material
around the dies. The process further includes stacking the first
die on the second die (block 430). In certain embodiments, stacking
the first die on the second die includes aligning the channels
associated with the first die with the channels associated with the
second die. The process can also include attaching a lead frame to
the lateral contacts associated with the first and second dies
(block 435). In certain embodiments, the lead frame includes
multiple lead fingers having attachment portions spaced apart along
a longitudinal axis of each lead finger. Individual lead fingers
can also include alignment portions extending laterally from each
attachment portion. As such, in certain embodiments, attaching the
lead frame can include attaching individual attachment portions of
the lead fingers with corresponding lateral contacts and engaging
the alignment portions of the lead fingers with corresponding
extension portions protruding from the mold material surrounding
the stacked first and second dies.
Any one of the assemblies having the features described above with
reference to FIGS. 1A-4 can be incorporated into any of a myriad of
larger and/or more complex systems, a representative example of
which is system 500 shown schematically in FIG. 5. The system 500
can include a processor 502, a memory 504 (e.g., SRAM, DRAM, flash,
and/or other memory devices), input/output devices 506, and/or
other subsystems or components 508. The assemblies having
electrical connectors described above with reference to FIGS. 1A-4
may be included in any of the components shown in FIG. 5. The
resulting system 500 can perform any of a wide variety of
computing, processing, storage, sensing, imaging, and/or other
functions. Accordingly, representative systems 500 include, without
limitation, computers and/or other data processors, for example,
desktop computers, laptop computers, Internet appliances, hand-held
devices (e.g., palm-top computers, wearable computers, cellular or
mobile phones, personal digital assistants, music players, etc.),
multi-processor systems, processor-based or programmable consumer
electronics, network computers, and minicomputers. Other
representative systems 500 may be housed in a single unit or
distributed over multiple interconnected units (e.g., through a
communication network). The components of the system 500 can
accordingly include local and/or remote memory storage devices and
any of a wide variety of computer-readable media.
From the foregoing it will be appreciated that specific embodiments
have been described herein for purposes of illustration, but that
various modifications may be made without deviating from the
disclosure. For example, one of the stacked assemblies described
above may be combined with another generally similar stacked
assembly. Where the context permits, singular or plural terms may
also include the plural or singular terms, respectively. Moreover,
unless the word "or" is expressly limited to mean only a single
term exclusive from the other items in reference to a list or two
or more items, then the use of "or" in such a list is to be
interpreted as including (a) any single item in the list, (b) all
of the items in the list, or (c) any combination of the items in
the list. Additionally, the term "comprising" is used throughout to
mean including at least the recited feature(s) such that any
greater number of the same feature or additional types of features
are not precluded.
Various modifications may be made without deviating from the
embodiments disclosed herein. For example, features described in
the context of particular embodiments may be combined or eliminated
in other embodiments. Further, although advantages associated with
certain embodiments have been described in the context of those
embodiments, other embodiments may also exhibit such advantages,
and not all embodiments need necessarily exhibit such advantages to
fall within the scope of the disclosure. For example, trenches or
channels of varying widths and depths can be formed in the mold
material. Accordingly, the disclosure is not limited except as by
the appended claims.
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