U.S. patent number 7,577,772 [Application Number 10/935,919] was granted by the patent office on 2009-08-18 for method and system for optimizing dma channel selection.
This patent grant is currently assigned to QLOGIC, Corporation. Invention is credited to Kuangfu D. Chu, Rajendra R. Gandhi, Bradley S. Sonksen.
United States Patent |
7,577,772 |
Sonksen , et al. |
August 18, 2009 |
**Please see images for:
( Certificate of Correction ) ** |
Method and system for optimizing DMA channel selection
Abstract
A host bus adapter coupled to a network and a host computing
system is provided. The host bus adapter includes a direct memory
access ("DMA")mode detection module that receives a DMA channel
identifier information from an arbitration module that receives
requests from plural DMA channels, wherein the DMA mode detection
module includes a DMA counter that counts a number of times a
single DMA channel is exclusively serviced by the arbitration
module and if the DMA counter value is equal to a threshold value,
then the DMA mode detection module enables a single channel mode
during which standard transaction rules are ignored for determining
DMA request lengths for transferring data. The single channel mode
is enabled for a certain duration. The host bus adapter includes a
rule based segmentation logic that may be enabled and/or disabled
by host bus adapter firmware and/or detection of a single channel
mode condition.
Inventors: |
Sonksen; Bradley S. (Rancho
Santa Margarita, CA), Chu; Kuangfu D. (Irvine, CA),
Gandhi; Rajendra R. (Laguna Niguel, CA) |
Assignee: |
QLOGIC, Corporation (Aliso
Viejo, CA)
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Family
ID: |
35520677 |
Appl.
No.: |
10/935,919 |
Filed: |
September 8, 2004 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20060053236 A1 |
Mar 9, 2006 |
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Current U.S.
Class: |
710/22;
710/5 |
Current CPC
Class: |
G06F
13/28 (20130101) |
Current International
Class: |
G06F
13/18 (20060101); G06F 3/00 (20060101) |
Field of
Search: |
;710/22 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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0738978 |
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Oct 1996 |
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EP |
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1059588 |
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Dec 2000 |
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EP |
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WO 95/06286 |
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Mar 1995 |
|
WO |
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WO 00/58843 |
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Oct 2000 |
|
WO |
|
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other.
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Primary Examiner: Tsai; Henry W. H.
Assistant Examiner: Wong; Titus
Attorney, Agent or Firm: Klein, O'Neill & Singh, LLP
Claims
What is claimed is:
1. A host bus adapter coupled to a network and a host computing
system, comprising: a plurality of direct memory access ("DMA")
channels, each DMA channel identified by a unique identifier; an
arbitration module that receives requests from the plurality of DMA
channels for accessing a bus; wherein the arbitration module
arbitrates between the requests and grants access to one of the
plurality of DMA channels; and a direct memory access ("DMA") mode
detection module that receives the unique identifier of a first DMA
channel that is granted access by the arbitration module at any
given time; wherein the DMA mode detection module compares the
unique identifier of the first DMA channel with a unique identifier
from a previous request that was granted immediately before the
first DMA channel grant; and if the unique identifiers match, then
the DMA mode detection module increments a DMA counter value that
maintains a count value for the DMA channel that has been
consecutively granted access within a certain duration; wherein the
DMA mode detection module compares the incremented DMA counter
value with a pre-programmed threshold value; and if the incremented
DMA counter value is at least equal to the pre-programmed threshold
value and no other request from another DMA channel from among the
plurality of DMA channels is pending, then the DMA mode detection
module enables a single channel mode to transfer data for a certain
duration; and during the single channel mode, standard transaction
rules are ignored to determine DMA request lengths to transfer the
data; and wherein the single channel mode is disabled when the DMA
mode detection module detects a pending DMA request from another
DMA channel besides the first DMA channel that was not granted
access to the bus within the certain duration.
2. The host bus adapter of claim 1, wherein the DMA mode detection
module includes a register that stores the pre-programmed threshold
value and the threshold value is programmed using host bus adapter
firmware.
3. The host bus adapter of claim 1, wherein the plurality of DMA
channels include a DMA channel in a receive path of the host bus
adapter.
4. The host bus adapter of claim 1, wherein the plurality of DMA
channels include a DMA channel in a transmit path of the host bus
adapter.
5. The host bus adapter of claim 1 wherein an auto-sensing mode for
the DMA mode detection module is enabled and disabled by firmware
code executed by the host bus adapter; and wherein during the
auto-sensing mode, the DMA detection module detects when the first
DMA channel is the only DMA channel from among the plurality of DMA
channels that is consecutively granted access to the bus within the
certain duration.
6. The host bus adapter of claim 1, further comprising: a rule
based segmentation logic that is disabled after detection of a
single channel mode condition by the DMA mode detection module the
rule based segmentation logic is enabled when the DMA mode
detection module detects if another DMA channel from among the
plurality of DMA channels, besides the first DMA channel, is
requesting bus access.
7. A system for communication between a host computing system and a
plurality of devices over a network, comprising: a host bus adapter
including: a plurality of direct memory access ("DMA") channels,
each DMA channel identified by a unique identifier; an arbitration
module that receives requests from the plurality of DMA channels
for accessing a bus; wherein the arbitration module arbitrates
between the requests and grants access to one of the plurality of
DMA channels; and a direct memory access ("DMA") mode detection
module that receives the unique identifier of a first DMA channel
that is granted access by the arbitration module at any given time;
wherein the DMA mode detection module compares the unique
identifier of the first DMA channel with a unique identifier from a
previous request that was granted immediately before the first DMA
channel grant; and if the unique identifiers match, then the DMA
mode detection module increments a DMA counter value that maintains
a count value for the DMA channel that has been consecutively
granted access within a certain duration; wherein the DMA mode
detection module compares the incremented DMA counter value with a
pre-programed threshold value; and if the incremented DMA counter
value is at least equal to the pre-programmed threshold value and
no other request from another DMA channel from among the plurality
of DMA channels is pending, then the DMA mode detection module
enables a single channel mode to transfer data for a certain
duration; and during the single channel mode, standard transaction
rules are ignored to determine DMA request lengths to transfer the
data; and wherein the single channel mode is disabled when the DMA
mode detection module detects a pending DMA request from another
DMA channel besides the first DMA channel that was not granted
access to the bus within the certain duration.
8. The system of claim 7, wherein the DMA mode detection module
includes a register that stores the pre-programmed threshold value
and the threshold value is programmed using host bus adapter
firmware.
9. The system of claim 7, wherein the plurality of DMA channels
include a DMA channel in a receive path of the host bus
adapter.
10. The system of claim 7, wherein the plurality of DMA channels
include a DMA channel in a transmit path of the host bus
adapter.
11. The system of claim 7, wherein an auto-sensing mode for the DMA
mode detection module is enabled and disabled by firmware code
executed by the host bus adapter; and wherein during the
auto-sensing mode, the DMA detection module detects when the first
DMA channel is the only DMA channel from among the plurality of DMA
channels that is consecutively granted access to the bus within the
certain duration.
12. The system of claim 7, wherein the network is based on fibre
channel.
13. The system of claim 7, wherein the host bit adapter includes a
rule based segmentation logic that is disabled after detection of a
single channel mode condition by the DMA mode detection module and
enabled when the DMA mode detection module detects if another DMA
channel from among the plurality of DMA channels, besides the first
DMA channel is requesting bus access.
14. A host computing system communicating with a plurality of
devices over a network, comprising: a host bus adapter
operationally coupled to the host computing system includes: a
plurality of direct memory access ("DMA ") channels, each DMA
channel identified by a unique identifier; an arbitration module
that receives requests from the plurality of DMA channels for
accessing a bus; wherein the arbitration module arbitrates between
the requests and grants access to one of the plurality of DMA
channels; and a direct memory access ("DMA") mode detection module
that receives the unique identifier of a first DMA channel that is
granted access by the arbitration module at any given time; wherein
the DMA mode detection module compares the unique identifier of the
first DMA channel with a unique identifier from a previous request
that was granted immediately before the first DMA channel grant;
and if the unique identifiers match, then the DMA mode detection
module increments a DMA counter value that maintains a count value
for the DMA channel that has been consecutively granted access
within a certain duration; wherein the DMA mode detection module
compares the incremented DMA counter value with a pre-programmed
threshold value; and if the incremented DMA counter value is at
least equal to the pre-programmed threshold value and no other
request from another DMA channel from among the plurality of DMA
channels is pending, then the DMA mode detection module enables a
single channel mode to transfer data for a certain duration; and
during the single channel mode, standard transaction rules are
ignored to determine DMA request lengths to transfer the data; and
wherein the single channel mode is disabled when the DMA mode
detection module detects a pending DMA request from another DMA
channel besides the first DMA channel that was not granted access
to the bus within the certain duration.
15. The host computing system of claim 14, wherein the DMA mode
detection module includes a register that stores the pre-programmed
threshold value and the threshold value is programmed using host
bus adapter firmware.
16. The host computing system of claim 14, wherein the plurality of
DMA channels include a DMA channel in a receive path of the host
bus adapter.
17. The host computing system of claim 14, wherein the plurality of
DMA channels include a DMA channel in a transmit path of the host
bus adapter.
18. The host computing system of claim 14, wherein an auto-sensing
mode for the DMA mode detection module is enabled and disabled by
firmware code executed by the host bus adapter; and wherein during
the auto-sensing mode, the DMA detection module detects when the
first DMA channel is the only DMA channel from among the plurality
of DMA channels that is granted access to the bus within the
certain duration.
19. The host computing system of claim 14, wherein the host bus
adapter includes a rule based segmentation logic that is disabled
after detection of a single channel mode condition by the DMA mode
detection module and the rule based segmentation logic is enabled
when the DMA mode detection module detects if another DMA channel
from among the plurality of DMA channels, besides the firs DMA
channel, is requesting bus access.
20. A method for transferring data between a host computing system
and a storage system via a host bus adapter ("HBA") coupled to a
network, comprising: (a) arbitrating between a plurality of
requests received from a plurality of direct memory access (DMA)
channels; wherein each DMA channel is identified by a unique
identifier and arbitration module arbitrates between the plurality
of requests (b) granting a request received from a first DMA
channel from among the plurality of DMA channels; (c) comparing the
unique identifier of the first DMA channel with a unique identifier
from a request that was granted immediately before the first DMA
channel request is granted; (d) if the unique identifiers match in
step (c), then incrementing a DMA counter that maintains a count of
a number of times a DMA channel from among the plurality of DMA
channels has been consecutively granted access within a certain
duration; (e) comparing the incremented DMA counter value from step
(d) with a programmed threshold value; (f) if the DMA counter value
is at least equal to the programmed threshold value, then enabling
a single channel mode; wherein during the single channel mode,
standard transaction rules are ignored to determine DMA request
lengths to transfer data between the host computing system and the
storage device; and (g) transferring data in the single channel
mode until a DMA mode detection module detects that another DMA
channel, besides the first DMA channel, from among the plurality of
DMA channels is requesting access to the bus.
21. The method of claim 20, wherein the DMA mode detection module
during an auto-sensing mode detects if the first DMA channel is the
only DMA channel from among the plurality of DMA channels that has
been granted access to the bus within the certain duration.
22. The method of claim 21, wherein the auto-sensing mode is
enabled and disabled by firmware code of the HBA.
23. The method of claim 21, wherein the HBA uses a rule based
segmentation logic to segment data; and the rule based segmentation
logic is disabled after detection of a single channel mode
condition by the DMA mode detection module; and the rule based
segmentation logic is enabled when the DMA mode detection module
detects another DMA channel from among the plurality of DMA
channels, besides the first DMA channel, is requesting bus access.
Description
BACKGROUND
1. Field of the Invention
The present invention relates to computing systems, and more
particularly to optimizing direct memory access ("DMA") channel
arbitration.
2. Background of the Invention
Storage area networks ("SANs") are commonly used where plural
memory storage devices are made available to various host computing
systems. Data in a SAN is typically moved from plural host systems
(that include computer systems, servers etc.) to the storage system
through various controllers/adapters.
Host systems typically include several functional components. These
components may include a central processing unit (CPU), main
memory, input/output ("I/O") devices, and streaming storage devices
(for example, tape drives). In conventional systems, the main
memory is coupled to the CPU via a system bus or a local memory
bus. The main memory is used to provide the CPU access to data
and/or program information that is stored in main memory at
execution time. Typically, the main memory is composed of random
access memory (RAM) circuits. A computer system with the CPU and
main memory is often referred to as a host system.
Host systems often communicate with storage systems via a host bus
adapter ("HBA", may also be referred to as a "controller" and/or
"adapter") using an interface, for example, the "PCI" bus
interface. PCI stands for Peripheral Component Interconnect, a
local bus standard that was developed by Intel Corporation.RTM..
The PCI standard is incorporated herein by reference in its
entirety. Most modern computing systems include a PCI bus in
addition to a more general expansion bus (e.g. the ISA bus). PCI is
a 64-bit bus and can run at clock speeds of 33 or 66 MHz.
PCI-X is another standard bus that is compatible with existing PCI
cards using the PCI bus. PCI-X improves the data transfer rate of
PCI from 132 MBps to as much as 1 GBps. The PCI-X standard was
developed by IBM.RTM., Hewlett Packard Corporation.RTM. and Compaq
Corporation.RTM. to increase performance of high bandwidth devices,
such as Gigabit Ethernet standard and Fibre Channel Standard, and
processors that are part of a cluster.
Various other standard interfaces are also used to move data from
host systems to storage devices. Fibre channel is one such
standard. Fibre channel (incorporated herein by reference in its
entirety) is an American National Standard Institute (ANSI) set of
standards, which provides a serial transmission protocol for
storage and network protocols such as HIPPI, SCSI, IP, ATM and
others. Fibre channel provides an input/output interface to meet
the requirements of both channel and network users.
iSCSI is another standard (incorporated herein by reference in its
entirety) that is based on Small Computer Systems Interface
("SCSI"), which enables host computer systems to perform block data
input/output ("I/O") operations with a variety of peripheral
devices including disk and tape devices, optical storage devices,
as well as printers and scanners.
A traditional SCSI connection between a host system and peripheral
device is through parallel cabling and is limited by distance and
device support constraints. For storage applications, iSCSI was
developed to take advantage of network architectures based on Fibre
Channel and Gigabit Ethernet standards. iSCSI leverages the SCSI
protocol over established networked infrastructures and defines the
means for enabling block storage applications over TCP/IP networks.
iSCSI defines mapping of the SCSI protocol with TCP/IP.
DMA modules are used by HBAs to perform data transfers between
memory locations, or between memory locations and an input/output
port. A DMA module functions without involving a microprocessor by
initializing control registers in the DMA unit with transfer
control information. The transfer control information generally
includes source address (the address of the beginning of a block of
data to be transferred), the destination address, and the size of
the data block. DMA units provide address and bus control signals
to and from a device for a read and/or write cycle.
Specific channels are implemented in a DMA unit to allow storage
devices to transfer data directly to and from memory storage
devices. A channel can be activated by a DMA request signal (DREQ)
from a storage device or a host system. The DMA unit receives the
DREQ, provides a DMA acknowledged signal (DACK), and transfers the
data over the channel to or from the storage device.
HBAs typically use multiple DMA channels and have an arbitration
module that arbitrates for access to the PCI (or PCI-Express) link.
This allows an HBA to arbitrate and switch contexts (between
channels) by actively processing command, status and data. Multiple
channels are serviced in periodic bursts. After each arbitration
cycle there is additional time for re-loading a data pipeline when
connecting to selected channel, even if the selected channel is the
same as the previously selected channel in the previous arbitration
cycle. Hence if multiple channels are not being used, the minimum
arbitration cycle adds latency (of plural clock cycles) and affects
overall performance. The reason for the latency is that certain
resources have to be loaded and updated for every DMA cycle. When
consecutive requests occur from the same DMA channel and no other
channel is requesting access, there is an additional penalty each
time the same channel is serviced because no data is transferred by
another channel during the time when the active channel is
re-initialized (or "re-armed").
A HBA often has to perform frequent context switching between DMA
channels, especially when status, command and data are processed at
the same time. In other instances, the HBA may operate using
predominantly a single DMA channel. This occurs for example, where
a large data transfer occurs and a particular DMA unit gets access.
These instances (i.e. single channel use or frequent context
switching) are not predictable. Conventional HBAs fail to
auto-sense single channel usage and adjust arbitration cycles
accordingly.
Also, industry standards (for example, PCI-Express standard)
provide transaction rules as to when memory read/write requests
must terminate based on maximum payload, maximum read request size
and address/data alignment. Because of these rules, a large DMA
request may have to be segmented into smaller blocks. In
conventional systems, completion for a first data segment is
received before another request is granted for the next segment to
the same DMA channel. This is because only one outstanding request
per DMA channel is allowed. The request-response sequence is
repeated until the entire DMA request is completed. If a single
channel is repeatedly used for a large data transfer, the
request-response-request cycle negatively affects overall
performance.
Therefore, what is required is a system and method that can
automatically sense if the same DMA channel is being used for a
data transfer, disable certain standard request and segmentation
rules for a certain period and efficiently transfer data by
decreasing arbitration frequency.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a host bus adapter coupled
to a network and a host computing system is provided. The host bus
adapter includes a direct memory access ("DMA")mode detection
module that receives a DMA channel identifier information from an
arbitration module that receives requests from plural DMA channels,
wherein the DMA mode detection module includes a DMA counter that
counts a number of times a single DMA channel is exclusively
serviced by the arbitration module and if the DMA counter value is
equal to a threshold value, then the DMA mode detection module
enables a single channel mode during which standard transaction
rules are ignored for determining DMA request lengths for
transferring data. The single channel mode is enabled for a certain
duration.
The host bus adapter includes a rule based segmentation logic that
may be enabled and/or disabled by host bus adapter firmware and/or
detection of a single channel mode condition.
The DMA mode detection module includes a register that stores the
threshold value and the threshold value is programmable. The plural
DMA channels include a DMA channel in a receive and transmit path
of the host bus adapter.
In another aspect of the present invention, a system that allows a
host computing system to communicate with plural devices over a
network is provided. The system includes a host bus adapter
including a DMA mode detection module that receives a DMA channel
identifier information from an arbitration module that receives
requests from plural DMA channels, wherein the DMA mode detection
module includes a DMA counter that counts a number of times a
single DMA channel is exclusively serviced by the arbitration
module and if the DMA counter value is equal to a threshold value,
then the DMA mode detection module enables a single channel mode
during which standard transaction rules are ignored for determining
DMA request lengths for transferring data.
The host bus adapter includes a rule based segmentation logic that
may be enabled and/or disabled by host bus adapter firmware and/or
detection of a single channel mode condition.
The DMA mode detection module includes a register that stores the
threshold value and the threshold value is programmable.
A host computing system that can communicate with plural devices
over a network is provided. The computing system is coupled to a
host bus adapter that includes a DMA mode detection module that
receives a DMA channel identifier information from an arbitration
module that receives requests from plural DMA channels, wherein the
DMA mode detection module includes a DMA counter that counts a
number of times a single DMA channel is exclusively serviced by the
arbitration module and if the DMA counter value is equal to a
threshold value, then the DMA mode detection module enables a
single channel mode during which standard transaction rules are
ignored for determining DMA request lengths for transferring
data.
The host bus adapter includes a rule based segmentation logic that
may be enabled and/or disabled by host bus adapter firmware and/or
detection of a single channel mode condition.
In yet another aspect of the present invention, a method for
transferring data between a host computing system and plural
devices using a HBA is provided. The method includes, determining
if a same DMA channel in the HBA has been exclusively serviced for
a certain duration; and enabling a single channel mode during which
standard transaction rules are ignored for determining DMA request
lengths for transferring data between the host computing system and
the plural devices.
This brief summary has been provided so that the nature of the
invention may be understood quickly. A more complete understanding
of the invention can be obtained by reference to the following
detailed description of the preferred embodiments thereof
concerning the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing features and other features of the present invention
will now be described with reference to the drawings of a preferred
embodiment. In the drawings, the same components have the same
reference numerals. The illustrated embodiment is intended to
illustrate, but not to limit the invention. The drawings include
the following Figures:
FIG. 1A is a block diagram showing various components of a SAN;
FIG. 1B is a block diagram of a host bus adapter that uses DMA mode
selection, according to one aspect of the present invention;
FIG. 1C shows a block diagram of plural DMA units using a DMA mode
selection module, according to one aspect of the present
invention;
FIG. 1D shows a block diagram of the DMA mode selection module,
according to one aspect of the present invention; and
FIG. 2 is a process flow diagram of executable steps for DMA
processing, according to one aspect of the present invention.
The use of similar reference numerals in different figures
indicates similar or identical items.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
To facilitate an understanding of the preferred embodiment, the
general architecture and operation of a SAN, and a HBA will be
described. The specific architecture and operation of the preferred
embodiment will then be described with reference to the general
architecture of the host system and HBA.
SAN Overview:
FIG. 1A shows a SAN system 100 that uses a HBA 106 (referred to as
adapter 106) for communication between a host system with host
memory 101 to various storage systems (for example, storage
subsystem 116 and 121, tape library 118 and 120) using fibre
channel storage area networks 114 and 115. Host memory 101 includes
a driver 102 that co-ordinates all data transfer via adapter 106
using input/output control blocks ("IOCBs"). Servers 117 and 119
can also access the storage sub-systems using SAN 115 and 114,
respectively.
A request queue 103 and response queue 104 is maintained in host
memory 101 for transferring information using adapter 106. Host
system communicates with adapter 106 via a PCI bus 105 through a
PCI core module (interface) 137, as shown in FIG. 1B.
HBA 106:
FIG. 1B shows a block diagram of adapter 106. Adapter 106 includes
processors (may also be referred to as "sequencers") "XSEQ" 112 and
"RSEQ" 109 for receive and transmit side, respectively for
processing data received from storage sub-systems and transmitting
data to storage sub-systems. Transmit path in this context means
data path from host memory 101 to the storage systems via adapter
106. Receive path means data path from storage subsystem via
adapter 106. It is noteworthy, that only one processor is used for
receive and transmit paths, and the present invention is not
limited to any particular number/type of processors. Buffers 111A
and 111B are used to store information in receive and transmit
paths, respectively.
Beside dedicated processors on the receive and transmit path,
adapter 106 also includes processor 106A, which may be a reduced
instruction set computer ("RISC") for performing various functions
in adapter 106.
Adapter 106 also includes fibre channel interface (also referred to
as fibre channel protocol manager "FPM") 113A that includes an FPM
113B and 113 in receive and transmit paths, respectively. FPM 113B
and FPM 113 allow data to move to/from storage systems.
Adapter 106 is also coupled to external memory 108 and 110 via
connection 116A (FIG. 1A) (referred interchangeably, hereinafter)
and local memory interface 122. Memory interface 122 is provided
for managing local memory 108 and 110. Local DMA module 137A is
used for gaining access to move data from local memory
(108/110).
Adapter 106 also includes a serial/de-serializer 136 for converting
data from 10-bit to 8-bit format and vice-versa.
Adapter 106 also includes request queue (0) DMA channel 130,
response queue DMA channel 131, request queue (1) DMA channel 132
that interface with request queue 103 and response queue 104; and a
command DMA channel 133 for managing command information. These DMA
channels are coupled to arbiter 107 that receives plural requests
from DMA channels and grants access to a certain channel.
Both receive and transmit paths have DMA modules 129 and 135 that
are used to gain access to a channel for data transfer in the
receive/transmit paths. Transmit path also has a scheduler 134 that
is coupled to processor 112 and schedules transmit operations.
A host processor (not shown) sets up shared data structures in
buffer memory 108. A host command is stored in buffer 108 and the
appropriate sequencer (i.e., 109 or 112) is initialized to execute
the command.
Various DMA units (or channels, used interchangeably throughout
this specification) (for example, 129, 130, 131, 132, 133 and 135)
send a request to arbiter 107. The requests are analyzed based on
established standard arbitration rules. When a request is granted,
the DMA unit is informed of the grant and memory access is granted
to a particular channel.
DMA Mode Selection Module 107A ("Module 107A")
In one aspect of the present invention, a DMA mode selection module
107A is provided that automatically detects ("auto-senses") when a
particular DMA channel is being granted consecutive (i.e.
back-to-back) access for a certain period of time. Module 107A can
enable a "single channel" mode that circumvents various standard
rules, for example, turn-off data block segmentation, which reduces
the number of arbitration cycles and the turnaround time spent for
the same DMA channel to be re-initialized.
Module 107A also senses when multiple channels are being used again
after a single channel mode is enabled. When this occurs, the
single channel mode is disabled and standard segmentation
techniques are used for a large data transfer.
FIG. 1C shows arbiter 107 being functionally coupled with module
107A. Plural DMA channels (for example, 129 and 135) are coupled
with arbiter 107. Each DMA channel has a request pipeline (for
example, 129B and 135B) and a segmentation module (for example 129A
and 135A). The segmentation module segments a DMA transfer into
segments (or blocks) to meet data transfer rules and/or if a DMA
transfer is too large. Sequencer 109 and 112 send channel task
commands (129C and 135C) to DMA channels 129 and 135, respectively.
The commands are used to generate a request to arbiter 107.
Segmentation modules 129A and 135B also operate based on certain
rules, for example, when and how data blocks should be segmented.
These rules can be turned on or off by the firmware. Some of these
rules are based on data block length and address limitations as
imposed by the PCI-Express standard protocol. Rules may also be
enabled/disabled by detection of a single channel mode condition
that is described below.
When a channel is granted access, the information is passed on to
module 107A. If the same channel is being granted access repeatedly
and there are no competing requests, module 107A enables a single
channel mode select signal 107F. This allows segmentation module to
stop segmenting data blocks (and/or divide data blocks into larger
segments) and transfer data in larger blocks to avoid arbitration
cycle. The single channel mode is enabled for a finite time only so
that once other channel request access, then there is no
backlog.
FIG. 1D shows a block diagram for module 107A. Module 107A's
auto-sensing mode can be enabled or disabled by adapter 106
firmware. Arbiter 107 provides a channel's identifier ("Channel
ID") 107J every time access is granted to a channel. A threshold
register (shown as PST_THR) 107D can be programmed by firmware with
a persistence threshold value. Register 107D is controlled by
firmware using signal/command 107H. Command/signal 107I is used to
load the threshold value.
A DMA sequence counter 107B (DMA_SEQ_CNT) maintains a running count
each time a DMA request is granted by arbiter 107 (shown as 107K).
Counter 107B is enabled by firmware using command/signal 107G.
Compare module 107N compares the Channel ID of a current DMA
request with the Channel ID 107J. If the DMA channel ID 107J is the
same for a current channel (107P) as for the last channel and
counter 107B value (i.e. 107L) is less than register 107D value
(i.e., 107M) as determined by logic 107E, then counter 107B is
increased. If the Channel ID 107J is different then counter 107B is
reset, for example, 1. When 107L is equal to or greater than 107M,
then the single mode select signal 107F is generated and sent to
segmentation logic (for example, 129A or 135A).
FIG. 2 shows a flow diagram of executable process steps for
auto-sensing DMA channel usage and enable a single channel
mode.
The process starts when counter 107B is enabled by firmware in step
S200 by command/signal 107G and in step S201, a threshold value is
loaded in register 107D by command/signal 107I.
In step S202, the process determines if a current DMA channel ID
(107P) is the same as the Channel ID for the previous request
(107J). This is performed by compare module 107N. If the Channel ID
is different, then in step S203 counter 107B is reset.
If the Channel ID is the same, signifying that the same DMA channel
is being serviced, then in step S202A, the DMA counter 107B is
incremented.
In step S204, counter value 107L is compared with threshold value
107M by logic 107E. If 107L is not equal to 107M, then DMA requests
are arbitrated and data blocks segmented using standard rules, and
counter 107B is increased in step S205.
If 107L is equal to 107M, then in step S206 the single DMA channel
mode is enabled. When single channel mode is not enabled then
certain transaction rules are followed. For example, (a) Read
requests must not exceed the maximum read request size; (b) Write
requests must not exceed the maximum payload size; (c) Read and
write requests must not overlap 4 kilo byte ("KB") address
segments; and/or (d) Write requests must terminate at 128 Byte
("B") boundaries as often as possible (i.e., unless a last request
in a sequence that does not end at a 128B address).
If 107L is equal to 107M, then the single channel mode is enabled
by command/signal 107F.
When single channel mode is enabled, the foregoing transaction
rules are not used to determine the beginning and the end of each
DMA request. This will cause the arbitration frequency to decrease
since the size of transfers will increase.
It is noteworthy that single channel mode may only be allowed for a
certain duration by firmware of adapter 106. Normal request length
segmentation/arbitration occurs after single channel mode is
automatically disabled.
Although the present invention has been described with reference to
specific embodiments, these embodiments are illustrative only and
not limiting. Many other applications and embodiments of the
present invention will be apparent in light of this disclosure and
the following claims.
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