U.S. patent number 7,242,213 [Application Number 10/932,477] was granted by the patent office on 2007-07-10 for memory module and method having improved signal routing topology.
This patent grant is currently assigned to Micron Technology, Inc.. Invention is credited to Roy E. Greeff, George E. Pax.
United States Patent |
7,242,213 |
Pax , et al. |
July 10, 2007 |
Memory module and method having improved signal routing
topology
Abstract
A registered memory module includes several memory devices
coupled to a register through a plurality of transmission lines
forming a symmetrical tree topology. The tree includes several
branches each of which includes two transmission lines coupled only
at its ends to either another transmission line or one of the
memory devices. The branches are arranged in several layers of
hierarchy, with the transmission lines in branches having the same
hierarchy having the same length. Each transmission line preferably
has a characteristic impedance that is half the characteristic
impedance of any pair of downstream transmission lines to which it
is coupled to provide impedance matching. A dedicated transmission
line is used to couple an additional memory device, which may or
may not be an error checking memory device, to the register.
Inventors: |
Pax; George E. (Boise, ID),
Greeff; Roy E. (Boise, ID) |
Assignee: |
Micron Technology, Inc. (Boise,
ID)
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Family
ID: |
33511048 |
Appl.
No.: |
10/932,477 |
Filed: |
September 1, 2004 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20050030797 A1 |
Feb 10, 2005 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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10460588 |
Jun 11, 2003 |
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Current U.S.
Class: |
326/30; 327/565;
365/194; 438/253; 326/83 |
Current CPC
Class: |
H05K
1/025 (20130101); G11C 5/063 (20130101); H05K
1/181 (20130101); G11C 5/025 (20130101); G11C
5/04 (20130101); G11C 11/409 (20130101); H05K
2201/09254 (20130101); Y02P 70/611 (20151101); Y02P
70/50 (20151101) |
Current International
Class: |
H03K
19/003 (20060101); G11C 7/08 (20060101); H01L
21/8242 (20060101); H01L 25/00 (20060101) |
Field of
Search: |
;326/30,83,86,85,80
;438/253 ;365/194 ;327/565 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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0849685 |
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Jun 1998 |
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EP |
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2001265539 |
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Sep 2001 |
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JP |
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WO 93/19422 |
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Sep 1993 |
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WO |
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WO 02/27499 |
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Apr 2002 |
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WO |
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Programmable Read-Only Memory, online May 17, 2004
[http://foldoc.doc.ic.ac.uk/foldoc/foldoc/cgi?flash+memory]. cited
by other .
Intel, "Intel 840 Chipset: 82840 Memory Controller Hub (MCH)",
Datasheet, Oct. 1999, pp. 1-178. cited by other .
Micron Technology, Inc., "Synchronous DRAM Module 512MB/1GB
(.times.72, ECC) 168-PIN Registered FBGA SDRAM DIMM", Micron
Technology, Inc., 2002, pp. 1-23, no month. cited by other .
Gillett, R. et al., "Using The Memory Channel Network", Micro IEEE,
vol. 17, Issue 1, Jan.-Feb. 1997 (Abstract Only). cited by other
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Gommans et al., "Applications Drive Secure Lightpath Creation
Across Heterogeneous Domains", Communications Magazine, IEEE, vol.
44, Issue 3, Mar. 2006 (Abstract Only). cited by other .
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other.
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Primary Examiner: Barnie; Rexford
Assistant Examiner: Mai; Lam T.
Attorney, Agent or Firm: Dorsey & Whitney, LLP.
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of pending U.S. patent
application Ser. No. 10/460,588, filed Jun. 11, 2003.
Claims
We claim:
1. A memory module, comprising: a plurality of dynamic random
access memory devices; an active memory component having a
plurality of terminals; and a respective conductor tree coupling
each of the terminals of the active memory component to a terminal
of each of the plurality of memory devices, each of the conductor
trees comprising at least one branch, each branch including a pair
of transmission lines each of which is connected at only its ends
to either one of the memory devices, the respective terminal of the
active memory component, or to an end of another of the
transmission lines, the transmission lines being arranged in a
plurality of hierarchies with the transmission lines in the same
hierarchy have the same length.
2. The memory module of claim 1 wherein the active memory component
comprises a register for storing address and command signals and
outputting the stored address and command signals to the memory
devices.
3. The memory module of claim 1 wherein each of the transmission
lines in each branch has a characteristic impedance, and wherein
the characteristic impedance of each transmission line is
approximately half the characteristic impedance of any transmission
line to which it is coupled downsteam of the active memory
component.
4. The memory module of claim 1, further comprising: an additional
memory device other than the plurality of memory devices; and a
plurality of dedicated transmission lines each coupling a
respective one of several of the terminals of the active memory
component to respective terminals of the additional memory
device.
5. The memory module of claim 4 wherein the additional memory
device comprises an error checking memory device.
6. The memory module of claim 4 wherein the lengths of the
dedicated transmission lines from the active memory component to
the additional memory device are substantially equal to the lengths
of the transmission lines in the tree from the active memory
component to each of the plurality of memory devices.
7. The memory module of claim 1 wherein the transmission lines in
all of the hierarchies have the same length.
8. The memory module of claim 1 wherein the memory module comprises
2.sup.N of the memory devices, and wherein the tree comprise N
hierarchies of branches.
9. The memory module of claim 1 wherein each of the transmission
lines have a characteristic impedance, and wherein the transmission
lines in the same hierarchy have the same characteristic
impedance.
10. The memory module of claim 9 wherein each of the transmission
lines in the same hierarchy have the same electrical
characteristics.
11. The memory module of claim 1 wherein the terminals of the
active memory component comprises output terminals, and the
terminals of the memory devices comprise input terminals.
12. A memory module, comprising: a plurality of memory devices; an
active memory component having a plurality of terminals, the active
memory component comprising a register for storing address and
command signals and outputting the stored address and command
signals to the memory devices; and a respective conductor tree
coupling each of the terminals of the active memory component to a
terminal of each of the plurality of memory devices, each of the
conductor trees comprising at least one branch, each branch
including a pair of transmission lines each of which is connected
at only its ends to either one of the memory devices, the
respective terminal of the active memory component, or to an end of
another of the transmission lines, the transmission lines being
arranged in a plurality of hierarchies with the transmission lines
in the same hierarchy having electrical and physical
characteristics that cause the signal propagation times through the
transmission lines in the same hierarchy to be substantially equal
to each other.
13. The memory module of claim 12 wherein each of the transmission
lines in each branch has a characteristic impedance, and wherein
the characteristic impedance of each transmission line is
approximately half the characteristic impedance of any transmission
line to which it is coupled downstream of the active memory
component.
14. The memory module of claim 12 wherein the plurality of memory
devices comprises a plurality of dynamic random access memory
devices.
15. The memory module of claim 12, further comprising: an
additional memory device other than the plurality of memory
devices; and a plurality of dedicated transmission lines each
coupling a respective one of several of the terminals of the active
memory component to respective terminals of the additional memory
device.
16. The memory module of claim 15 wherein the additional memory
device comprises an error checking memory device.
17. The memory module of claim 15 wherein the signal propagation
times through the dedicated transmission lines from the active
memory component to the additional memory device are substantially
equal to the signal propagation times through the transmission
lines in the tree from the active memory component to each of the
plurality of memory devices.
18. The memory module of claim 12 wherein the transmission lines in
all of the hierarchies have the same signal propagation times.
19. The memory module of claim 12 wherein the memory module
comprises 2.sup.N of the memory devices, and wherein the tree
comprise N hierarchies of branches.
20. The memory module of claim 12 wherein each of the transmission
lines have a characteristic impedance, and wherein the transmission
lines in the same hierarchy have the same characteristic
impedance.
21. The memory module of claim 20 wherein each of the transmission
lines in the same hierarchy have the same electrical
characteristics.
22. The memory module of claim 12 wherein the transmission lines in
the same hierarchy have the same lengths.
23. The memory module of claim 12 wherein the terminals of the
active memory component comprises output terminals, and the
terminals of the memory devices comprise input terminals.
24. A method of coupling signals between an active memory component
in a memory module and a plurality of dynamic random access memory
devices in the memory module, the method comprising coupling a
plurality of the signals between the active memory component and
the memory devices through a plurality of transmission lines in
which each transmission line is connected at only its ends to
either one of the memory devices or to an end of another of the
transmission lines, the transmission lines being arranged in a
plurality of hierarchies with the transmission lines in the same
hierarchy having the same length.
25. The method of claim 24 wherein the active memory component
comprises a register for storing address and command signals and
outputting the stored address and command signals to the memory
devices.
26. The method of claim 24 wherein each of the transmission lines
has a characteristic impedance, and wherein the act of coupling a
plurality of the signals between the active memory component and
the memory devices through a plurality of transmission lines
comprises coupling each of the signals between upstream
transmission lines and downstream transmission lines in which the
characteristic impedance of each downstream transmission line is
twice the characteristic impedance of the upstream transmission
line to which it is coupled.
27. The method of claim 24, further comprising coupling signals
between the active memory component and an additional memory device
mounted on the memory module substrate other than the plurality of
memory devices, the method comprising coupling each of a plurality
of the signals between the active memory component and the
additional memory device through a respective dedicated
transmission line that is not directly connected to any of the
plurality of memory devices.
28. The method of claim 27 wherein the lengths of the dedicated
transmission lines provide substantially the same propagation time
as the length of the transmission lines between the active memory
component and the plurality of memory devices.
29. The method of claim 24 wherein the plurality of memory devices
comprise 2.sup.N of the memory devices, and wherein the act of
coupling a plurality of the signals between the active memory
component and the memory devices through a plurality of
transmission lines comprises arranging the transmission lines in N
levels of hierarchy.
30. The method of claim 24 wherein the act of coupling a plurality
of the signals between the active memory component and the memory
devices through a plurality of transmission lines comprises
coupling a plurality of the signals between from the memory devices
to the active memory component through a plurality of transmission
lines.
31. A method of coupling address and command signals between a
register in a memory module for the storing address and command
signals and a plurality of memory devices in the memory module, the
method comprising coupling a plurality of the signals between the
register and the memory devices through a plurality of transmission
lines in which each transmission line is connected at only its ends
to either one of the memory devices or to an end of another of the
transmission lines, the transmission lines being arranged in a
plurality of hierarchies with the transmission lines in the same
hierarchy having electrical and physical characteristics that cause
the signal propagation times through the transmission lines in the
same hierarchy to be substantially equal to each other.
32. The method of claim 31 wherein each of the transmission lines
has a characteristic impedance, and wherein the act of coupling a
plurality of the signals between the active memory component and
the memory devices through a plurality of transmission lines
comprises coupling each of the signals between upstream
transmission lines and downstream transmission lines in which the
characteristic impedance of each downstream transmission line is
twice the characteristic impedance of the upstream transmission
line to which it is coupled.
33. The method of claim 31 wherein the plurality of memory devices
comprises a plurality of dynamic random access memory devices.
34. The method of claim 31, further comprising coupling signals
between the active memory component and an additional memory device
mounted on the memory module substrate other than the plurality of
memory devices, the method comprising coupling each of a plurality
of the signals between the active memory component and the
additional memory device through a respective dedicated
transmission line that is not directly connected to any of the
plurality of memory devices.
35. The method of claim 34 wherein the dedicated transmission lines
have electrical and physical characteristics that cause the signal
propagation times through the dedicated transmission lines between
the active memory component and the additional memory device be
substantially equal to the signal propagation times through the
transmission lines between the active memory component and each of
the plurality of memory devices.
36. The method of claim 31 wherein the plurality of memory devices
comprise 2.sup.N of the memory devices, and wherein the act of
coupling a plurality of the signals between the active memory
component and the memory devices through a plurality of
transmission lines comprises arranging the transmission lines in N
levels of hierarchy.
37. The method of claim 31 wherein the act of coupling a plurality
of the signals between the active memory component and the memory
devices through a plurality of transmission lines comprises
coupling a plurality of the signals between from the memory devices
to the active memory component through a plurality of transmission
lines.
38. A memory module, comprising: a plurality of memory devices; an
active memory component having a plurality of terminals; and a
respective conductor tree coupling each of the terminals of the
active memory component to a terminal of each of the plurality of
memory devices, each of the conductor trees comprising at least one
branch, each branch including a pair of transmission lines each of
which has a characteristic impedance and is connected at only its
ends to either one of the memory devices, the respective terminal
of the active memory component, or to an end of another of the
transmission lines, the transmission lines being arranged in a
plurality of hierarchies with the transmission lines in the same
hierarchy having electrical and physical characteristics that cause
the signal propagation times through the transmission lines in the
same hierarchy to be substantially equal to each other, the
characteristic impedance of each transmission line being
approximately half the characteristic impedance of any transmission
line to which it is coupled downsteam of the active memory
component.
39. The memory module of claim 38 wherein the plurality of memory
devices comprises a plurality of dynamic random access memory
devices.
40. The memory module of claim 38, further comprising: an
additional memory device other than the plurality of memory
devices; and a plurality of dedicated transmission lines each
coupling a respective one of several of the terminals of the active
memory component to respective terminals of the additional memory
device.
41. The memory module of claim 38 wherein the transmission lines in
all of the hierarchies have the same signal propagation times.
42. The memory module of claim 38 wherein the memory module
comprises 2.sup.N of the memory devices, and wherein the tree
comprise N hierarchies of branches.
43. The memory module of claim 38 wherein each of the transmission
lines in the same hierarchy have the same electrical
characteristics.
44. The memory module of claim 38 wherein the transmission lines in
the same hierarchy have the same lengths.
45. The memory module of claim 38 wherein the terminals of the
active memory component comprises output terminals, and the
terminals of the memory devices comprise input terminals.
46. A memory module, comprising: a plurality of dynamic random
access memory devices; an active memory component having a
plurality of terminals; and a respective conductor tree coupling
each of the terminals of the active memory component to a terminal
of each of the plurality of memory devices, each of the conductor
trees comprising at least one branch, each branch including a pair
of transmission lines each of which is connected at only its ends
to either one of the memory devices, the respective terminal of the
active memory component, or to an end of another of the
transmission lines, the transmission lines being arranged in a
plurality of hierarchies with the transmission lines in the same
hierarchy having electrical and physical characteristics that cause
the signal propagation times through the transmission lines in the
same hierarchy to be substantially equal to each other.
47. The memory module of claim 46, further comprising: an
additional memory device other than the plurality of memory
devices; and a plurality of dedicated transmission lines each
coupling a respective one of several of the terminals of the active
memory component to respective terminals of the additional memory
device.
48. The memory module of claim 46 wherein the transmission lines in
all of the hierarchies have the same signal propagation times.
49. The memory module of claim 46 wherein the memory module
comprises 2.sup.N of the memory devices, and wherein the tree
comprise N hierarchies of branches.
50. The memory module of claim 46 wherein each of the transmission
lines in the same hierarchy have the same electrical
characteristics.
51. The memory module of claim 46 wherein the transmission lines in
the same hierarchy have the same lengths.
52. The memory module of claim 46 wherein the terminals of the
active memory component comprises output terminals, and the
terminals of the memory devices comprise input terminals.
53. A memory module, comprising: a plurality of memory devices; an
active memory component having a plurality of terminals; an
additional memory device other than the plurality of memory
devices; a respective conductor tree coupling each of the terminals
of the active memory component to a terminal of each of the
plurality of memory devices, each of the conductor trees comprising
at least one branch, each branch including a pair of transmission
lines each of which is connected at only its ends to either one of
the memory devices, the respective terminal of the active memory
component, or to an end of another of the transmission lines, the
transmission lines being arranged in a plurality of hierarchies
with the transmission lines in the same hierarchy having electrical
and physical characteristics that cause the signal propagation
times through the transmission lines in the same hierarchy to be
substantially equal to each other; and a plurality of dedicated
transmission lines each coupling a respective one of several of the
terminals of the active memory component to respective terminals of
the additional memory device.
54. The memory module of claim 53 wherein the additional memory
device comprises an error checking memory device.
55. The memory module of claim 53 wherein the signal propagation
times through the dedicated transmission lines from the active
memory component to the additional memory device are substantially
equal to the signal propagation times through the transmission
lines in the tree from the active memory component to each of the
plurality of memory devices.
56. The memory module of claim 53 wherein the transmission lines in
all of the hierarchies have the same signal propagation times.
57. The memory module of claim 53 wherein each of the transmission
lines in the same hierarchy have the same electrical
characteristics.
58. The memory module of claim 53 wherein the transmission lines in
the same hierarchy have the same lengths.
59. The memory module of claim 53 wherein the terminals of the
active memory component comprises output terminals, and the
terminals of the memory devices comprise input terminals.
60. A memory module, comprising: a plurality of memory devices; an
active memory component having a plurality of terminals; and a
respective conductor tree coupling each of the terminals of the
active memory component to a terminal of each of the plurality of
memory devices, each of the conductor trees comprising at least one
branch, each branch including a pair of transmission lines each of
which is connected at only its ends to either one of the memory
devices, the respective terminal of the active memory component, or
to an end of another of the transmission lines, the transmission
lines being arranged in a plurality of hierarchies with the
transmission lines in the same hierarchy having the same electrical
characteristics and electrical and physical characteristics that
cause the signal propagation times through the transmission lines
in the same hierarchy to be substantially equal to each other.
61. The memory module of claim 60 wherein the transmission lines in
the same hierarchy have the same lengths.
62. The memory module of claim 60 wherein the terminals of the
active memory component comprises output terminals, and the
terminals of the memory devices comprise input terminals.
63. A memory module, comprising: a plurality of memory devices; an
active memory component having a plurality of terminals; and a
respective conductor tree coupling each of the terminals of the
active memory component to a terminal of each of the plurality of
memory devices, each of the conductor trees comprising at least one
branch, each branch including a pair of transmission lines each of
which is connected at only its ends to either one of the memory
devices, the respective terminal of the active memory component, or
to an end of another of the transmission lines, the transmission
lines being arranged in a plurality of hierarchies with the
transmission lines in the same hierarchy having the same length and
electrical and physical characteristics that cause the signal
propagation times through the transmission lines in the same
hierarchy to be substantially equal to each other.
64. The memory module of claim 63 wherein the terminals of the
active memory component comprises output terminals, and the
terminals of the memory devices comprise input terminals.
65. A memory module, comprising: a plurality of memory devices each
of which has a plurality of input terminals; an active memory
component having a plurality of output terminals; and a respective
conductor tree coupling each of the output terminals of the active
memory component to one of the input terminal of each of the
plurality of memory devices, each of the conductor trees comprising
at least one branch, each branch including a pair of transmission
lines each of which is connected at only its ends to either one of
the memory devices, the respective output terminal of the active
memory component, or to an end of another of the transmission
lines, the transmission lines being arranged in a plurality of
hierarchies with the transmission lines in the same hierarchy
having electrical and physical characteristics that cause the
signal propagation times through the transmission lines in the same
hierarchy to be substantially equal to each other.
66. A method of coupling signals between a plurality of memory
devices in a memory module and a register for storing address and
command signals and outputting the stored address and command
signals to the memory devices, the method comprising coupling a
plurality of the signals between the register and the memory
devices through a plurality of transmission lines in which each
transmission line is connected at only its ends to either one of
the memory devices or to an end of another of the transmission
lines, the transmission lines being arranged in a plurality of
hierarchies with the transmission lines in the same hierarchy
having the same length.
67. The method of claim 66 wherein each of the transmission lines
has a characteristic impedance, and wherein the act of coupling a
plurality of the signals between the register and the memory
devices through a plurality of transmission lines comprises
coupling each of the signals between upstream transmission lines
and downstream transmission lines in which the characteristic
impedance of each downstream transmission line is twice the
characteristic impedance of the upstream transmission line to which
it is coupled.
68. The method of claim 66, further comprising coupling signals
between the register and an additional memory device mounted on the
memory module substrate other than the plurality of memory devices,
the method comprising coupling each of a plurality of the signals
between the register and the additional memory device through a
respective dedicated transmission line that is not directly
connected to any of the plurality of memory devices.
69. The method of claim 66 wherein the plurality of memory devices
comprise 2.sup.N of the memory devices, and wherein the act of
coupling a plurality of the signals between the register and the
memory devices through a plurality of transmission lines comprises
arranging the transmission lines in N levels of hierarchy.
70. The method of claim 66 wherein the act of coupling a plurality
of the signals between the register and the memory devices through
a plurality of transmission lines comprises coupling a plurality of
the signals between from the memory devices to the register through
a plurality of transmission lines.
71. A method of coupling signals between an active memory component
in a memory module and a plurality of memory devices in the memory
module, the method comprising: coupling a plurality of the signals
between the active memory component and the memory devices through
a plurality of transmission lines in which each transmission line
is connected at only its ends to either one of the memory devices
or to an end of another of the transmission lines, the transmission
lines being arranged in a plurality of hierarchies with the
transmission lines in the same hierarchy having the same length;
and coupling signals between the active memory component and an
additional memory device mounted on the memory module substrate
other than the plurality of memory devices, each of the signals
being coupled between the active memory component and the
additional memory device through a respective dedicated
transmission line that is not directly connected to any of the
plurality of memory devices.
72. The method of claim 71 wherein the lengths of the dedicated
transmission lines provide substantially the same propagation time
as the length of the transmission lines between the active memory
component and the plurality of memory devices.
73. The method of claim 71 wherein the act of coupling a plurality
of the signals between the active memory component and the memory
devices through a plurality of transmission lines comprises
coupling a plurality of the signals between from the memory devices
to the active memory component through a plurality of transmission
lines.
74. A method of coupling signals between an active memory component
in a memory module and a plurality of memory devices in the memory
module, the method comprising coupling a plurality of the signals
between the active memory component and the memory devices through
a plurality of transmission lines in which each transmission line
has a characteristic impedance and is connected at only its ends to
either one of the memory devices or to an end of another of the
transmission lines, the transmission lines being arranged in a
plurality of hierarchies with the transmission lines in the same
hierarchy having electrical and physical characteristics that cause
the signal propagation times through the transmission lines in the
same hierarchy to be substantially equal to each other, the signals
being coupled between the active memory component and the memory
devices through the plurality of transmission lines by coupling
each of the signals between upstream transmission lines and
downstream transmission lines in which the characteristic impedance
of each downstream transmission line is twice the characteristic
impedance of the upstream transmission line to which it is
coupled.
75. The method of claim 74 wherein the plurality of memory devices
comprises a plurality of dynamic random access memory devices.
76. The method of claim 74, further comprising coupling signals
between the active memory component and an additional memory device
mounted on the memory module substrate other than the plurality of
memory devices, the method comprising coupling each of a plurality
of the signals between the active memory component and the
additional memory device through a respective dedicated
transmission line that is not directly connected to any of the
plurality of memory devices.
77. The method of claim 74 wherein the act of coupling a plurality
of the signals between the active memory component and the memory
devices through a plurality of transmission lines comprises
coupling a plurality of the signals between from the memory devices
to the active memory component through a plurality of transmission
lines.
78. A method of coupling signals between an active memory component
in a memory module and a plurality of dynamic random access memory
devices in the memory module, the method comprising coupling a
plurality of the signals between the active memory component and
the memory devices through a plurality of transmission lines in
which each transmission line is connected at only its ends to
either one of the memory devices or to an end of another of the
transmission lines, the transmission lines being arranged in a
plurality of hierarchies with the transmission lines in the same
hierarchy having electrical and physical characteristics that cause
the signal propagation times through the transmission lines in the
same hierarchy to be substantially equal to each other.
79. The method of claim 78, further comprising coupling signals
between the active memory component and an additional memory device
mounted on the memory module substrate other than the plurality of
memory devices, the method comprising coupling each of a plurality
of the signals between the active memory component and the
additional memory device through a respective dedicated
transmission line that is not directly connected to any of the
plurality of memory devices.
80. The method of claim 78 wherein the act of coupling a plurality
of the signals between the active memory component and the memory
devices through a plurality of transmission lines comprises
coupling a plurality of the signals between from the memory devices
to the active memory component through a plurality of transmission
lines.
81. A method of coupling signals between an active memory component
in a memory module and a plurality of memory devices in the memory
module, the method comprising: coupling a plurality of the signals
between the active memory component and the memory devices through
a plurality of transmission lines in which each transmission line
is connected at only its ends to either one of the memory devices
or to an end of another of the transmission lines, the transmission
lines being arranged in a plurality of hierarchies with the
transmission lines in the same hierarchy having electrical and
physical characteristics that cause the signal propagation times
through the transmission lines in the same hierarchy to be
substantially equal to each other; and coupling signals between the
active memory component and an additional memory device mounted on
the memory module substrate other than the plurality of memory
devices, the method comprising coupling each of a plurality of the
signals between the active memory component and the additional
memory device through a respective dedicated transmission line that
is not directly connected to any of the plurality of memory
devices.
82. The method of claim 81 wherein the dedicated transmission lines
have electrical and physical characteristics that cause the signal
propagation times through the dedicated transmission lines between
the active memory component and the additional memory device be
substantially equal to the signal propagation times through the
transmission lines between the active memory component and each of
the plurality of memory devices.
83. The method of claim 81 wherein the act of coupling a plurality
of the signals between the active memory component and the memory
devices through a plurality of transmission lines comprises
coupling a plurality of the signals between from the memory devices
to the active memory component through a plurality of transmission
lines.
84. A method of coupling signals between an active memory component
in a memory module and a plurality of memory devices in the memory
module, the method comprising coupling a plurality of the signals
between the active memory component and the memory devices through
a plurality of transmission lines in which each transmission line
is connected at only its ends to either one of the memory devices
or to an end of another of the transmission lines, the transmission
lines being arranged in a plurality of hierarchies with the
transmission lines in the same hierarchy having electrical and
physical characteristics that cause the signal propagation times
through the transmission lines in the same hierarchy to be
substantially equal to each other, the plurality of the signals
being coupled from the memory devices to the active memory
component through a plurality of transmission lines.
Description
TECHNICAL FIELD
The present invention relates to memory systems, and, more
particularly, to memory modules having transmission lines coupled
to a large number of memory devices.
BACKGROUND OF THE INVENTION
Memory devices are in widespread use in a variety of
processor-based systems, such as computer systems. In some cases,
memory devices can be mounted on the same circuit board as a
processor and a memory controller, which is generally used to
couple the memory devices to the processor. However, in most cases,
the memory devices are part of a memory module in which several
memory devices are mounted on a common substrate, such as a printed
circuit board. The memory modules are generally plugged into
sockets mounted on a motherboard to establish communication with a
memory controller and processor. Such memory modules are commonly
used in computer systems as system memory in which the memory
modules are dynamic random access memory ("DRAMs") devices.
Although the memory devices in a memory module may be coupled
directly to a memory controller, in one type of memory module,
known as a "registered" memory module, the memory devices are
coupled to a register that is, in turn, coupled to the memory
controller. More specifically, in a registered DRAM module, the
command and address lines from the memory controller are coupled to
a register. The register stores memory commands and addresses
coupled through the command and address lines, respectively, and
then couples the commands and addresses to the memory devices. Data
signals are typically coupled directly to and from the memory
devices without being registered. By registering the command and
address signals, they can be coupled to the memory module for a
relatively short period of time since it is not necessary to wait
for the memory devices to latch the command and address signals.
Also, registering the command and address signals avoids excessive
loading of the command and address lines because the command and
address lines are coupled to only a single device, i.e., the
register, rather than to multiple devices, i.e., all of the memory
devices.
The manner in which each of the command and address lines are
routed from the register to the memory devices can significantly
affect the performance of the memory module. One coupling topology,
known as a "daisy chain" topology, is shown in FIG. 1A. In a daisy
chain topology, a first transmission line 10, which may be a
command signal line or an address signal line, extends from a
register 16 to one end of a second transmission line 20 (which is a
single conductor, but functions as separate segments or
transmission lines 20a g). Respective transmission lines 30a h are
coupled to spaced apart locations of the transmission lines 20(a
g). The transmission lines 30a h each extend to an input terminal
of respective memory devices 36a h, which, in this case are DRAM
devices.
A "hybrid tree" topology shown in FIG. 1B differs from the daisy
chain topology of FIG. 1A in that the first transmission line 10 is
coupled to the center of the second transmission line 20a rather
than to one of its ends. In alternative embodiments of a hybrid
tree topology, the first transmission line 10 may be coupled to
locations of the second transmission lines 20(a d) other than
either one end or the center of the second transmission line 20.
Like the daisy chain topology shown in FIG. 1A, respective
transmission lines 30a h are coupled to spaced apart locations of
the transmission lines 20a d and extend to input terminals of the
respective memory devices 36a h.
Still another hybrid tree topology shown in FIG. 1C uses two
separate transmission lines 20a,b coupled to the transmission lines
30a d, 30e h. Transmission lines 20a and 20b are made up of
transmission lines 20aa, 20ab, 20ac, 20ad, 20ba, 20bb, 20bc and
20bd respectively. The transmission lines 20a,b are, in turn,
coupled to the first transmission line 10 through a third
transmission line 40, which joins the first transmission line 10 at
the center of the transmission line 40. Transmission line 40 is
made up of transmission lines 44a and 44b. Transmission lines 44a
and 44b are coupled to the transmission lines 20a,b at the ends of
the transmission line 40 by respective transmission lines
44a,b.
The daisy chain and hybrid tree topologies shown in FIGS. 1A 1C can
provide adequate performance at relatively slow speeds, but they
provide less than optimum performance at higher operating speeds.
In particular, signals coupled through the transmission line 20 (or
transmission lines 20a,b in the case of the topology shown in FIG.
1C) reflect from the junctions with the transmission lines 30a h as
well as from the junction between each of the transmission lines
30a h and its respective memory devices 36a h, respectively. These
reflections produce destructive and constructive interference at
each of the junctions between the transmission line 20 and the
transmission lines 30a h that can seriously degrade signals coupled
to the memory devices 36. The hybrid tree topologies shown in FIGS.
1B and 1C place the transmission lines 30a h closer to the ends of
the transmission line 20 compared to the daisy chain topology shown
in FIG. 1A. Therefore, the hybrid tree topologies tend to provide
better performance than the daisy chain topology. However, the
hybrid tree topologies still provide less than optimum performance.
Further, the hybrid tree topology shown in FIG. 1C also produces
reflections from the junctions between the transmission lines 20a,b
and the transmission lines 44a,b.
Although the signal reflection problems have been described in the
context of registered memory modules, the same problem can exist in
other types of memory modules. For example, in a memory hub module,
signals are coupled from a memory hub in the module to each of
several memory devices in the module. Also, in a buffered memory
module, signals are coupled from respective buffers in the module
to each of several memory devices in the module. Reflections
produced in these types of memory modules can degrade performance
in essentially the same manner as described above.
There is therefore a need for a connection topology for routing
signals to memory devices in memory modules that can avoid signal
degradation caused by reflections generated at the junctions
between transmission lines and memory device terminals and between
different transmission lines.
BRIEF SUMMARY OF THE INVENTION
A signal routing topology and method couples signals between an
active memory component, such as a register, and a plurality of
memory devices using transmission lines. The transmission lines are
each connected at only its ends to either an input terminal of one
of the memory devices or to an end of another of the transmission
lines. The transmission lines form a symmetrical tree having
several levels of hierarchy, with the transmission lines in the
same level of hierarchy having the same length. The transmission
lines are preferably impedance matched to pairs of transmission
lines to which they are coupled. In the event the memory module
contains an odd-numbered memory device, such as an error checking
memory device, the odd-numbered memory device is coupled to the
active memory component through a dedicated transmission line.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A 1C are schematic diagrams showing topologies for routing
signal lines from registers to memory devices in conventional
registered memory modules.
FIG. 2 is a schematic diagram showing one topology for routing
transmission lines from a register to memory devices in a
registered memory module according to one embodiment of the
invention.
FIG. 3 is a schematic diagram showing a topology for routing
transmission lines from a register to memory devices in a
registered memory module having error checking capabilities
according to another embodiment of the invention.
FIG. 4 is a block diagram of a computer system including registered
memory modules in accordance with the present invention.
DETAILED DESCRIPTION
A topology for routing signals from a register to memory devices in
a registered memory module according to one embodiment of the
invention is shown in FIG. 2. The memory module 50 includes a
register 58 and four dynamic random access memory ("DRAM") devices
60a d. A large number of address and command lines are coupled from
the register 58 to the DRAM devices 60a d, although the signal
lines for routing only one of these signals are shown in FIG. 2.
The register 58 includes an output buffer 62 for each signal that
is coupled to a first transmission line 64. The end of the first
transmission line 64 is coupled to a first branch 70 that consists
of two transmission lines 72, 74. The branch 70 is symmetrical in
that both of the transmission lines 72, 74 have the same electrical
and physical characteristics, particularly the same length. The
ends of the transmission lines 72, 74 are coupled to a second pair
of branches 80, 82, respectively. The branches 80, 82 are
symmetrical internally and with each other as they are each formed
by two transmission lines 86, 88 and 90, 92, respectively, having
the same length. Although it is necessary that the transmission
lines 86, 88 and 90, 92 of the respective branches 80, 82 all be of
the same length, it is not necessary that the lengths of these
transmission lines 86, 88, 90, 92 be equal to the lengths of the
transmission lines 72, 74 in the branch 70. Finally, the end of
each of the transmission lines 86, 88, 90, 92 is coupled to a
respective one of the DRAMs 60a d.
In operation, a signal is coupled through the first transmission
line 64 to the transmission lines 72, 74 of the first branch 70. If
these transmission lines are of the same impedance there is a
mismatch and some of the energy reflected and some of the energy is
passed. When the signal reaches the ends of the transmission lines
72, 74, it is again reflected from the junctions with the branches
80, 82, respectively. As a result, the signal is coupled to the
branches 80, 82 with less magnitude. The reflections of the signal
are then coupled back through the transmission lines 72, 74 to the
junction of the transmission line 64. The reflected signals reach
the junction with the transmission line 64 at the same time so that
they appear as a single transmission line coupling to a higher
impedance transmission line. This acts to reflect in phase
increasing the voltage that eventually reaches the DRAMs. In a
similar manner, the signal coupled to the branches 80, 82 have a
relatively large magnitude at the ends of the transmission lines
86, 88 and 90, 92 because of their reflection from an input
terminal of the DRAMs 60a d. An open circuit reflects the signal
resulting in an apparent doubling of the voltage. The signals
reflected from the DRAMs 60a d reach the junctions to the
transmission lines 72, 74 at the same time because the lengths of
the transmission lines 86, 88, 90, 92 are all identical. As a
result, the impedance of the transmission lines 86, 88 and 90, 92
at their junction to the transmission lines 72, 74, respectively,
appear to have a lower impedance coupling to a higher impedance
resulting in an in phase reflection back to the DRAMs resulting in
more signal at the DRAMs. The signals reflected through the
transmission lines 86, 88 and 90, 92 are also coupled through the
transmission lines 72, 74, respectively, of the first branch 70
where they reach the junction to the first transmission line 64 at
the same time. Again another reflection back towards the DRAMs. The
result of all these reflections is a stairstep of increasing
voltage at the DRAMs.
Using a tree of transmission lines in which each branch is entirely
symmetrical maximizes the magnitude of signals coupled to the DRAMs
60a d and minimizes the magnitude of reflections reflected from the
end of each transmission line. By coupling the DRAMs 60a d only to
the ands of the transmission lines, the destructive interference
away from the ends of the transmission lines, which reduces signal
amplitude, is avoided.
The symmetrical tree used in the memory module 50 of FIG. 2
includes branches with only two levels of hierarchy, namely the
first branch 70 with a first level of hierarchy and the second
branches 80, 82 with a second level of hierarchy. However, since
each branch consists of two transmission lines each coupled to
either a transmission line or a memory device at only its end, a
memory module having 2.sup.N of the memory devices will have N
hierarchies of branches.
The reflections from the junctions between the transmission lines
86, 88 and 90, 92 and the transmission lines 72, 74, respectively,
and from the junctions between the transmission lines 72, 74 and
the transmission line 64 can be reduced even further by impedance
matching the transmission lines. More specifically, as is well
known in the art, each transmission line has a characteristic
impedance. As is also well-known in the art, signals coupled
through a transmission line are reflected from impedance
discontinuities in the line. Therefore, such reflections can be
avoided by avoiding impedance discontinuities. If the first
transmission line 64 has an impedance of R (e.g., 17.5 ohms), the
transmission lines 72, 74 in the first branch should each have an
impedance of 2R (i.e., 35 ohms) since two resistors in parallel
have an impedance of half the impedance of each resistor.
Similarly, the transmission lines 86, 88, 90, 92 should each have
an impedance of 4R (i.e., 70 ohms).
Although impedance matching of the transmission lines used in a
symmetrical tree in accordance with the invention is desirable, it
is not necessary. Furthermore, it may not be practical to provide
impedance matching where the tree includes a large number of branch
hierarchies because the practical range of impedance values that
can be obtained is very limited. With commonly used conductive
materials mounted on commonly used substrates, the transmission
lines formed by the conductive materials become excessively wide at
impedance values much less than 15 ohms, and they become
excessively narrow at impedance values much larger than 80
ohms.
Data are commonly stored in a memory module using an even number of
memory devices, and, more commonly, a number of memory devices
equal to powers of two, i.e. 2, 4, 8, etc. However, some memory
modules include error checking and/or correcting ("ECC")
capabilities, which generally requires an additional memory device.
The use of an odd number of memory devices, such as an ECC memory
device, precludes coupling the memory devices through a symmetrical
tree. However, the benefits of a symmetrical tree can be obtained
using the topography shown in FIG. 3. FIG. 3 shows the same
components of a memory module that are shown in FIG. 3 with the
addition of an ECC DRAM 90. Therefore, in the interest of brevity,
all of the component shown in FIG. 3 have been provided with the
same reference numerals, and an explanation of their structure in
operation will not be repeated. Although ECC capabilities can be
obtained using the odd-numbered ECC DRAM 90 as shown in FIG. 3, ECC
capabilities can also be obtained by simply using one of the DRAMs
60a d to store ECC data.
The ECC DRAM 90 is coupled to the output of the buffer 62 through a
dedicated transmission line 94 extending from a location at or near
the buffer 62 to a terminal of the DRAM 90. By placing the junction
between the transmission line 94 and the first transmission line 64
near the buffer 62, the magnitude of any reflections from the
junction that are coupled through the tree is relatively small. The
transmission line 94 preferably has a length that is equal to the
combined length of the transmission lines between the buffer 62 and
the DRAMs 60a d so that a signal from the buffer 62 reaches the ECC
DRAM 90 at the same time the signal reaches the DRAMs 60a d. Also,
any reflections from the DRAMs 60a d reach the buffer 62 at the
same time that any reflection from the ECC DRAM 90 reaches the
buffer 62 so that the transmission lines to ECC DRAM 90 and DRAMs
60a d can be considered to be in parallel. If the output impedance
of buffer 62 is equal to this parallel impedance then signals
reflected from the DRAMs 60a d and 90 are not reflected from the
output of the buffer 62.
A computer system 100 according to one embodiment of the invention
is shown in FIG. 4. The computer system 100 includes a processor
104 for performing various computing functions, such as executing
specific software to perform specific calculations or tasks. The
processor 104 includes a processor bus 106 that normally includes
an address bus, a control bus, and a data bus. The processor bus
106 is typically coupled to cache memory 108, which, is typically
static random access memory ("SRAM"). Finally, the processor bus
106 is coupled to a system controller 110, which is also sometimes
referred to as a bus bridge.
The system controller 110 serves as a communications path to the
processor 104 for a variety of other components. More specifically,
the system controller 110 includes a graphics port that is
typically coupled to a graphics controller 112, which is, in turn,
coupled to a video terminal 114. The system controller 110 is also
coupled to one or more input devices 118, such as a keyboard or a
mouse, to allow an operator to interface with the computer system
100. Typically, the computer system 100 also includes one or more
output devices 120, such as a printer, coupled to the processor 104
through the system controller 110. One or more data storage devices
124 are also typically coupled to the processor 104 through the
system controller 110 to allow the processor 104 to store data or
retrieve data from internal or external storage media (not shown).
Examples of typical storage devices 124 include hard and floppy
disks, tape cassettes, and compact disk read-only memories
(CD-ROMs).
The system controller 110 includes a memory controller 128 that is
coupled to several registered memory modules 130a,b . . . n, which
serve as system memory for the computer system 100. The memory
modules 130 are coupled to the memory controller 128 through a bus
system 134. The memory modules 130 are shown coupled to the memory
controller 128 in a multi-drop arrangement in which the single bus
system 134 is coupled to all of the memory modules 130. However, it
will be understood that other topologies may also be used.
Each of the memory modules 130 includes a register 140 for storing
command and address signals as well as eight memory devices 148,
which, in the example illustrated in FIG. 4, are synchronous
dynamic random access memory ("SDRAM") devices. However, a fewer or
greater number of memory devices 148 may be used, and memory
devices other than SDRAM devices may also be used. The register 140
is coupled to each of the system memory devices 148 through
symmetrical tree 150 in accordance with the present invention. An
error checking and/or correcting memory device is included in the
memory module 130n, in which the topography shown in FIG. 3 is
preferably used.
From the foregoing it will be appreciated that, although specific
embodiments of the invention have been described herein for
purposes of illustration, various modifications may be made without
deviating from the spirit and scope of the invention. For example,
transmission line topologies according to the present invention can
be used to couple signals to memory devices other than DRAMs and to
memory devices from components other than registers. As previously
mentioned, transmission line topologies according to the present
invention can be used to route signals to memory devices from
buffers or memory hubs, for example. Accordingly, the invention is
not limited except as by the appended claims.
* * * * *
References