U.S. patent number 7,173,282 [Application Number 10/857,356] was granted by the patent office on 2007-02-06 for semiconductor device having a crystalline semiconductor film.
This patent grant is currently assigned to Semiconductor Energy Laboratory Co., Ltd.. Invention is credited to Toshiji Hamatani, Masahiko Hayakawa, Jun Koyama, Yasushi Ogata, Hisashi Ohtani, Mitsuaki Osame, Satoshi Teramoto, Shunpei Yamazaki.
United States Patent |
7,173,282 |
Yamazaki , et al. |
February 6, 2007 |
Semiconductor device having a crystalline semiconductor film
Abstract
Nickel is selectively held in contact with a particular region
of an amorphous silicon film. Crystal growth parallel with a
substrate is effected by performing a heat treatment. A thermal
oxidation film is formed by performing a heat treatment in an
oxidizing atmosphere containing a halogen element. During this
step, the crystallinity is improved and the gettering of nickel
elements proceeds. A thin-film transistor is formed so that the
direction connecting source and drain regions coincides with the
above crystal growth direction. As a result, a TFT having superior
characteristics such as a mobility larger than 200 cm.sup.2/Vs and
an S value smaller than 100 mV/dec. can be obtained.
Inventors: |
Yamazaki; Shunpei (Setagaya,
JP), Teramoto; Satoshi (Atsugi, JP),
Koyama; Jun (Sagamihara, JP), Ogata; Yasushi
(Atsugi, JP), Hayakawa; Masahiko (Atsugi,
JP), Osame; Mitsuaki (Atsugi, JP), Ohtani;
Hisashi (Isehara, JP), Hamatani; Toshiji (Atsugi,
JP) |
Assignee: |
Semiconductor Energy Laboratory
Co., Ltd. (Kanagawa-ken, JP)
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Family
ID: |
27572019 |
Appl.
No.: |
10/857,356 |
Filed: |
June 1, 2004 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20050056843 A1 |
Mar 17, 2005 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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08785488 |
Jan 17, 1997 |
6744069 |
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Foreign Application Priority Data
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Jan 19, 1996 [JP] |
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8-26210 |
Jan 20, 1996 [JP] |
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8-26037 |
Jan 26, 1996 [JP] |
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8-32874 |
Jan 26, 1996 [JP] |
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8-32875 |
Jan 27, 1996 [JP] |
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8-32981 |
Feb 20, 1996 [JP] |
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8-58334 |
Mar 17, 1996 [JP] |
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8-88759 |
Nov 19, 1996 [JP] |
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8-324644 |
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Current U.S.
Class: |
257/72;
257/E21.133; 257/E21.192; 257/E21.318; 257/E21.32; 257/E21.413;
257/E21.414; 257/E29.003; 257/E29.151; 257/E29.278;
257/E29.293 |
Current CPC
Class: |
H01L
21/0242 (20130101); H01L 21/02488 (20130101); H01L
21/02532 (20130101); H01L 21/02667 (20130101); H01L
21/02672 (20130101); H01L 21/02686 (20130101); H01L
21/28158 (20130101); H01L 21/3221 (20130101); H01L
21/3226 (20130101); H01L 29/04 (20130101); H01L
29/66757 (20130101); H01L 29/66765 (20130101); H01L
29/78621 (20130101); H01L 29/78675 (20130101); H01L
29/4908 (20130101) |
Current International
Class: |
H01L
29/04 (20060101); H01L 31/036 (20060101) |
Field of
Search: |
;257/72 |
References Cited
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JP |
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JP |
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8-129358 |
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May 1996 |
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JP |
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8-129359 |
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May 1996 |
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JP |
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8-129360 |
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JP |
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JP |
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8-241997 |
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Sep 1996 |
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JP |
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96-005879 |
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Feb 1996 |
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KR |
|
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|
Primary Examiner: Weiss; Howard
Attorney, Agent or Firm: Robinson; Eric J. Robinson
Intellectual Property Law Office, P.C.
Claims
What is claimed is:
1. An active matrix display device comprising: a thin film
transistor formed over a substrate, said thin film transistor
comprising: a semiconductor film comprising crystalline silicon on
an insulating surface; a gate insulating film formed on the
semiconductor film; a gate electrode formed over a channel region
of said semiconductor film with the gate insulating film interposed
therebetween, a first insulating film covering said thin film
transistor, said first insulating film comprising silicon nitride;
a second insulating film formed over said first insulating film,
said second insulating film comprising a resin; a pixel electrode
formed over the second insulating film and electrically connected
to said thin film transistor, wherein said semiconductor film has
surface asperities that are as small as .+-.30 .ANG..
2. The active matrix display device according to claim 1 wherein
said semiconductor film comprises at least two crystals extending
along a first direction and a carrier moving direction in said
channel region is substantially coincident with said first
direction.
3. The active matrix display device according to claim 1 wherein a
thickness of said semiconductor film is 150 450 .ANG..
4. The active matrix display device according to claim 1 wherein an
S-value of said thin film transistor is less than 100 mV/dec.
5. The active matrix display device according to claim 1 further
comprising a third insulating film over the second insulating film
and below said pixel electrode.
6. The active matrix display device according to claim 1 wherein
said active matrix display device is a liquid crystal device.
7. The active matrix display device according to claim 1 wherein
said active matrix display device is an EL display device.
8. A phone comprising an active matrix display device, antenna, a
voice input section and a voice output section, said active matrix
display device comprising: a thin film transistor formed over a
substrate, said thin film transistor comprising: a semiconductor
film comprising crystalline silicon on an insulating surface; a
gate insulating film formed on the semiconductor film; a gate
electrode formed over a channel region of said semiconductor film
with the gate insulating film interposed therebetween, a first
insulating film covering said thin film transistor, said first
insulating film comprising silicon nitride; a second insulating
film formed over said first insulating film, said second insulating
film comprising a resin; a pixel electrode formed over the second
insulating film and electrically connected to said thin film
transistor, wherein said semiconductor film has surface asperities
that are as small as .+-.30 .ANG..
9. The phone according to claim 8 wherein said semiconductor film
comprises at least two crystals extending along a first direction
and a carrier moving direction in said channel region is
substantially coincident with said first direction.
10. The phone according to claim 8 wherein a thickness of said
semiconductor film is 150 450 .ANG..
11. The phone according to claim 8 wherein an S-value of said
semiconductor device is less than 100 mV/dec.
12. The phone according to claim 8 further comprising a third
insulating film over the second insulating film and below said
pixel electrode.
13. The phone according to claim 8 wherein said active matrix
display device is a liquid crystal device.
14. The phone according to claim 8 wherein said active matrix
display device is an EL display device.
15. A camera comprising an active matrix display device, said
active matrix display device comprising: a thin film transistor
formed over a substrate, said thin film transistor comprising: a
semiconductor film comprising crystalline silicon on an insulating
surface; a gate insulating film formed on the semiconductor film; a
gate electrode formed over a channel region of said semiconductor
film with the gate insulating film interposed therebetween, a first
insulating film covering said thin film transistor, said first
insulating film comprising silicon nitride; a second insulating
film formed over said first insulating film, said second insulating
film comprising a resin; a pixel electrode formed over the second
insulating film and electrically connected to said thin film
transistor, wherein said semiconductor film has surface asperities
that are as small as .+-.30 .ANG..
16. The camera according to claim 15 wherein said semiconductor
film comprises at least two crystals extending along a first
direction and a carrier moving direction in said channel region is
substantially coincident with said first direction.
17. The camera according to claim 15 wherein a thickness of said
semiconductor film is 150 450 .ANG..
18. The camera according to claim 15 wherein an S-value of said
semiconductor device is less than 100 mV/dec.
19. The camera according to claim 15 further comprising a third
insulating film over the second insulating film and below said
pixel electrode.
20. The camera according to claim 15 wherein said active matrix
display device is a liquid crystal device.
21. The camera according to claim 15 wherein said active matrix
display device is an EL display device.
22. An active matrix display device comprising: a thin film
transistor formed over a substrate, said thin film transistor
comprising: a semiconductor film comprising crystalline silicon on
an insulating surface, said semiconductor film including at least
source, drain and channel regions; a gate insulating film formed on
the semiconductor film; a gate electrode formed over a channel
region of said semiconductor film with the gate insulating film
interposed therebetween, a first insulating film covering said thin
film transistor, said first insulating film comprising silicon
nitride; a second insulating film formed over said first insulating
film, said second insulating film comprising a resin; a pixel
electrode formed over the second insulating film and electrically
connected to said thin film transistor, wherein said semiconductor
film has surface asperities that are as small as .+-.30 .ANG. and a
crystal growth direction of the semiconductor film substantially
coincides with a direction connecting said source region and said
drain region.
23. The active matrix display device according to claim 22 wherein
said semiconductor film comprises at least two crystals extending
along a first direction and a carrier moving direction in said
channel region is substantially coincident with said first
direction.
24. The active matrix display device according to claim 22 wherein
a thickness of said semiconductor film is 150 450 .ANG..
25. The active matrix display device according to claim 22 wherein
an S-value of said thin film transistor is less than 100
mV/dec.
26. The active matrix display device according to claim 22 further
comprising a third insulating film over the second insulating film
and below said pixel electrode.
27. The active matrix display device according to claim 22 wherein
said active matrix display device is a liquid crystal device.
28. The active matrix display device according to claim 22 wherein
said active matrix display device is an EL display device.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a crystalline thin-film
semiconductor and a manufacturing method thereof. The invention
also relates to a semiconductor device using the above thin-film
semiconductor and a manufacturing method thereof.
2. Description of Related Art
Techniques are known in which a crystalline silicon film is formed
on a glass or quartz substrate and thin-film transistors
(hereinafter referred to as TFTs) are formed by using the silicon
film. Such TFTs are called high-temperature polysilicon TFTs or
low-temperature polysilicon TFTs.
In the case of high-temperature polysilicon TFTs, a crystalline
silicon film is formed by a technique including a heat treatment at
a relatively high temperature of 800 900.degree. C. It can be said
that this technique is derived from an IC manufacturing process
using a single crystal silicon wafer. Naturally, high-temperature
polysilicon TFTs are formed on a quartz substrate, which withstand
the above-mentioned high temperature.
On the other hand, low-temperature polysilicon TFTs are formed on a
glass substrate, which is inexpensive but is apparently lower in
heat resistance than a quartz substrate. To form a crystalline
silicon film for low-temperature polysilicon TFTs, heating at lower
than 600.degree. C. which a glass substrate can withstand or laser
annealing which causes almost no thermal damage on a glass
substrate is performed.
The high-temperature polysilicon TFT is advantageous in that TFTs
having uniform characteristics can be integrated on a
substrate.
On the other hand, the low-temperature polysilicon TFT is
advantageous in that a glass substrate can be used which is
inexpensive and can easily be increased in size.
According to the current manufacturing techniques, there are no
large differences in characteristics between the high-temperature
polysilicon TFT and the low-temperature polysilicon TFT. That is,
in both cases, the mobility is 50 100 cm.sup.2/Vs and the S value
is 200 400 mV/dec. (V.sub.D=1 V).
However, these values are much worse than those of MOS transistors
formed on a single crystal silicon wafer. In general, the S value
of MOS transistors formed on a single crystal silicon wafer is 60
70 mV/dec.
At present, there are active matrix liquid crystal display devices
in which an active matrix circuit and peripheral driver circuits
are integrated on the same substrate by using TFTs. In this type of
configuration, the source driver circuit of the peripheral driver
circuits is required to operate at a frequency higher than a little
more than 10 MHz. However, at present, a circuit using
high-temperature polysilicon TFTs or low-temperature polysilicon
TFTs can provide a margin of operation speed that is as small as
several megahertz.
For this reason, at present, a liquid crystal display device is
constituted by dividing its operation (called "divisional
driving"). However, this method has several problems; for example,
stripes appear on the screen due to, for instance, a slight
deviation in the division timing.
SUMMARY OF THE INVENTION
It is now considered a configuration in which not only peripheral
driver circuits (constituted of a shift register circuit and a
buffer circuit) but also an oscillation circuit, a D/A converter,
an A/D converter, and digital circuits for various kinds of image
processing are integrated on the same substrate.
However, the above-mentioned oscillation circuit, D/A converter,
A/D converter, and digital circuits for various kinds of image
processing are required to operate even at higher frequencies than
the peripheral driver circuits. Therefore, it is very difficult to
constitute such circuits by using high-temperature polysilicon TFTs
or low-temperature polysilicon TFTs as long as they are formed by
the current manufacturing techniques.
On the other hand, integrated circuits of MOS transistors formed on
a single crystal silicon wafer which circuits can operate at more
than 100 MHz have already been put to practical use.
An object of the present invention is to provide a TFT which can
constitute a circuit that is required to perform a high-speed
operation (generally at more than tens of megahertz).
Another object of the invention is to provide a TFT whose
characteristics are equivalent to those of a MOS transistor formed
on a single crystal silicon wafer. It is also intended to provide a
means for manufacturing such a TFT. It is further intended to
provide a semiconductor device having a required function by using
TFTs having so superior characteristics.
According to one aspect of the invention, there is provided a
semiconductor device using a thin-film transistor that uses, as an
active layer, a crystalline silicon film formed on a substrate
having an insulating surface, wherein the crystalline silicon film
has a crystal structure that is continuous in a predetermined
direction, and grain boundaries extending in the predetermined
direction; and the predetermined direction is at a predetermined
angle with a direction connecting a source region and a drain
region of the thin-film transistor.
FIGS. 6 and 7 show an example of a crystalline silicon film having
the above-mentioned crystal structure. FIGS. 6 and 7 are
photographs of obtained by observing the surface of a
250-.ANG.-thick crystalline silicon film with a transmission
electron microscope (TEM). FIG. 7 is an enlargement of part of the
photograph of FIG. 6.
The crystalline silicon film of FIGS. 6 and 7 can be obtained by a
manufacturing process of a first embodiment of the invention which
will be described later.
FIGS. 6 and 7 show a crystal structure that continuously extends
from the bottom left to the top right in these drawings, as well as
many grain boundaries extending substantially parallel with the
above direction.
As is apparent from the crystal structure shown in FIG. 7, this
crystalline silicon film is a collection of many crystallizations
(crystalline silicon grains) each having a crystal structure
extending in the particular direction. The width of the
crystallizations is 500 2,000 .ANG., or from about the thickness of
the crystalline silicon film to 2,000 .ANG..
Many definite grain boundaries are arranged, at intervals,
perpendicularly or substantially perpendicularly (in the direction
from the bottom right to the top left in these drawings) to the
direction in which the crystal structure has continuity; the
crystal structure is discontinuous (continuity is lost) in the
former direction.
The continuity of the lattice structure is substantially maintained
in the direction in which the crystal structure has continuity. In
this direction, the scattering and trapping of carriers during
their movement occur at a much smaller possibility than in the
other directions.
That is, it can be considered that a substantial single crystal
state, in which carriers are not scattered or are hardly scattered
by grain boundaries, is established in the direction in which the
crystal structure has continuity.
The above-mentioned aspect of the invention defines the
relationship between the direction in which the crystal structure
has continuity and the direction connecting the source and drain
regions of a thin-film transistor. To attain a high-speed
operation, it is desired that the direction in which the crystal
structure has continuity coincide or substantially coincide with
the direction connecting the source and drain regions. This
provides a configuration in which carriers can move most
easily.
The characteristics of a thin-film transistor can be controlled by
setting the angle between the above two directions at a proper
value. For example, in the case of forming a number of thin-film
transistor groups, the characteristics of a plurality of groups can
be made different from each other by changing the angle between the
two directions from one group to another.
A thin-film transistor in which the active layer is bent to assume
an N-like or a square-bracket-like, or even an M-like shape, that
is, the line connecting the source and drain regions is bent can be
formed in the following manner. That is, the direction in which the
crystal structure has continuity is so set as to coincide with the
carrier moving direction (as a whole) in the channel region.
Also in this case, the fastest operation can be expected when the
angle between the carrier moving direction and the direction in
which the crystal structure has continuity is set at 0.degree.. It
is apparent that this angle may be set at a proper value other than
0.degree., when necessary.
According to another aspect of the invention, there is provided a
semiconductor device using a thin-film transistor that uses, as an
active layer, a crystalline silicon film formed on a substrate
having an insulating surface, wherein the crystalline silicon film
is anisotropic in a grain boundary extending direction; and the
predetermined direction is at a predetermined angle with a
direction connecting a source region and a drain region of the
thin-film transistor.
According to still another aspect of the invention, there is
provided a semiconductor device using a thin-film transistor that
uses, as an active layer, a crystalline silicon film formed on a
substrate having an insulating surface, wherein the crystalline
silicon film is anisotropic in a grain boundary extending
direction; and the grain boundary extending direction and a carrier
moving direction in a channel region of the thin-film transistor
form a given angle.
To obtain the crystalline silicon film of the invention, it is
necessary to perform a heat treatment after introducing a metal
element that accelerates crystallization of silicon as typified by
nickel into an amorphous silicon film, and further perform a heat
treatment in an atmosphere containing a halogen element.
As the metal element, nickel is the best in terms of
reproducibility and effects. In general, the metal element may be
one or a plurality of elements selected from the group consisting
of Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au.
Where nickel is used, the concentration of nickel left in a final
silicon film is 1.times.10.sup.14 to 5.times.10.sup.18
atoms/cm.sup.3. If the gettering conditions of a thermal oxidation
film are refined, the upper limit of the concentration can be
reduced to 5.times.10.sup.17 atoms/cm.sup.3. The concentration can
be measured by the SIMS (secondary ion mass spectrometry).
In general, the lower limit of the nickel concentration is
1.times.10.sup.16 atoms/cm.sup.3. This is because when a balance
with the cost is considered, it is usually difficult to eliminate
the influences of nickel attached to a substrate and an apparatus
used.
Therefore, when an ordinary manufacturing process is employed, the
concentration of residual nickel is in a range of 1.times.10.sup.16
to 5.times.10.sup.17 atoms/cm.sup.3.
Since metal element moves into a thermal oxidation film in the step
of forming it, metal element has a concentration gradient or
distribution in the thickness direction of a resulting crystalline
silicon film.
It is generally observed that the concentration of the metal
element in the crystalline silicon film increases toward the
boundary of the thermal oxidation film. Under certain conditions,
it is observed that the concentration of the metal element
increases toward a substrate or an undercoat film, i.e., toward the
lower-side boundary.
Where a halogen element is contained in an atmosphere used in
forming the thermal oxidation film, the halogen element assumes a
concentration distribution similar to that of the metal element.
That is, the concentration increases toward the upper surface
and/or lower surface of the crystalline silicon film.
In the invention, it is preferred that the crystalline silicon film
finally has a thickness of 100 750 .ANG.. It is even preferred that
the thickness be 150 450 .ANG.. With the thickness in such ranges,
the unique crystal structure in which the crystallinity is
continuous in one direction as shown in FIGS. 6 and 7 can be
obtained with high reproducibility in a more enhanced manner.
It is necessary to determine the thickness of the final crystalline
silicon film by considering the fact that the thickness is
decreased by the formation of the thermal oxidation film.
According to a further aspect of the invention, there is provided a
manufacturing method of a semiconductor device, comprising the
steps of forming an amorphous silicon film on a substrate having an
insulating substrate; selectively introducing a metal element for
accelerating crystallization of silicon into a portion of the
amorphous silicon film; performing a heat treatment, to thereby
effect crystal growth parallel with the substrate in a direction
from the portion in which the metal element has been introduced to
the other portions; performing a heat treatment at 800.degree.
1,100.degree. C. for 30 minutes or more by an electrical furnace in
an oxidizing atmosphere containing a halogen element, to form a
thermal oxidation film; removing the thermal oxidation film; and
arranging a direction connecting a source region and a drain region
of the semiconductor as to coincide with or substantially coincide
with a crystal growth direction.
The crystalline silicon film of the invention can be obtained by
the above manufacturing process. Further, a MOS thin-film
transistor utilizing the uniqueness of its crystal structure can be
formed.
A metal element can be introduced by various methods, among which
are a method of applying a solution containing the metal element, a
method using CVD, a method using sputtering or evaporation, a
plasma processing method using an electrode that contains the metal
element, and a method using gas absorption.
To introduce a halogen element, there may be used a certain means
for causing an oxidizing atmosphere (for instance, an oxygen
atmosphere) to contain HCl, HF, HBr, Cl.sub.2, F.sub.2, Br.sub.2,
CF.sub.4, or the like.
It is effective to introduce a hydrogen gas into an atmosphere used
in forming a thermal oxidation film, and thereby utilize the action
of wet oxidation.
The temperature is a very important factor in forming a thermal
oxidation film. To obtain a TFT that can operate in itself at more
than several tens of megahertz and has a small S value of less than
100 mV/dec. (described later), it is preferable that the
temperature of a heat treatment for forming a thermal oxidation
film be more than 800.degree. C. It is even preferable that the
temperature be more than 900.degree. C.
The lower limit depends upon a pressure at which the annealing is
performed and a vapor pressure of the halogen compound of the
material to be gettered. That is, when the vapor pressure of the
halogen compound is smaller than the pressure of the annealing
atmosphere, the gettering efficiency is not so high. For example,
the vapor pressure of nickel chloride is 38.9 mmHg at 541.degree.
C. and 820.6 mmHg at 994.degree. C. Accordingly, when the annealing
is performed at the atmospheric pressure (760 mmHg), the effect of
the gettering is significantly increased when the temperature is
994.degree. C.
It is appropriate that the upper limit of the above temperature be
set at about 1,100.degree. C., which is the upper limit a quartz
substrate withstands.
According to another aspect of the invention, there is provided a
manufacturing method of a semiconductor device, comprising the
steps of forming an amorphous silicon film on a substrate having an
insulating substrate; selectively introducing a metal element for
accelerating crystallization of silicon into a portion of the
amorphous silicon film; performing a heat treatment, to thereby
effect crystal growth parallel with the substrate in a direction
from the portion in which the metal element has been introduced to
the other portions; performing a heat treatment at 800.degree.
1,100.degree. C. for 30 minutes or more by an electrical furnace in
an oxidizing atmosphere containing a halogen element, to form a
thermal oxidation film; removing the thermal oxidation film; and
arranging a carrier moving direction in a channel region as to
coincide with or substantially coincide with a crystal growth
direction.
The above manufacturing method pays attention to the carrier moving
direction in the channel region, and defines the relationship
between the carrier moving direction and the crystal growth
direction (i.e., the direction in which the crystal structure has
continuity or grain boundaries extend).
This manufacturing method is effective even in a case where the
line connecting the source and drain regions is bent.
A specific example of the invention will be described below. In the
technique of forming a crystalline silicon film by crystallizing an
amorphous silicon film by heating it, a heat treatment is performed
in a state that nickel is held in contact with a portion of the
surface of the amorphous silicon film, so that crystal growth
proceeds parallel with a substrate from the above portion to the
other portions.
Subsequently, a thermal oxidation film is formed on the surface of
a resulting crystalline silicon film by performing a heat treatment
at 800 1,100.degree. C. for 30 minutes or more by an electrical
furnace in an oxidizing atmosphere containing a halogen
element.
The thermal oxidation film is then removed. A crystalline silicon
film thus obtained has a structure in which grain boundaries extend
in a particular direction as shown in FIGS. 6 and 7 and the crystal
structure is continuous in the same direction.
A TFT having superior characteristics can be obtained by making the
carrier moving direction during an operation coincide with the
direction of the continuous crystal growth.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A 1D and 2A 2E show a manufacturing process of a TFT
according to a first embodiment of the present invention;
FIGS. 3A 3D show a manufacturing process of a TFT according to a
second embodiment of the invention;
FIGS. 4A 4D show a manufacturing process of a TFT according to a
third embodiment of the invention;
FIGS. 5A 5E show a manufacturing process of a TFT according to a
fourth embodiment of the invention;
FIGS. 6 and 7 are electron microscope photographs of a silicon thin
film;
FIGS. 8A 8F schematically show various semiconductor devices using
TFTs; and
FIGS. 9A and 9B schematically illustrate how crystal growth
proceeds.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiment 1
This embodiment is directed to a method of effecting crystal growth
parallel with a substrate (called "lateral growth") by selectively
introducing into an amorphous silicon film a metal element that
accelerates crystallization of silicon.
FIGS. 1A 1D and FIGS. 2A 2E show a manufacturing process according
to this embodiment. First, a 3,000-.ANG.-thick silicon oxide film
as an undercoat film 202 is formed on a quartz substrate 201. The
undercoat film 202 can be omitted if the quartz substrate 201 is
sufficiently smooth and if sufficient cleaning is performed.
Although the use of a quartz substrate is preferable at present,
the invention is not limited to the use of a quartz substrate and
other substrates can also be used as long as they withstand a heat
treatment temperature.
Next, a 600-.ANG.-thick amorphous silicon film 203 as a starting
film of a crystalline silicon film is formed by low-pressure
thermal CVD. It is preferred that the amorphous silicon film 203 be
thinner than 2,000 .ANG..
Thereafter, a 1,500-.ANG.-thick silicon oxide film (not shown) is
formed and then patterned into a mask 204 which has an opening 205.
The amorphous silicon film 203 is exposed in the opening 205.
The opening 205 has a long and narrow rectangular shape in which
the longitudinal direction extends perpendicularly to the paper
surface of FIGS. 1A 1D. It is appropriate that the opening 205 be
wider than 20 .mu.m and have a necessary length in the longitudinal
direction.
After a nickel acetate solution containing nickel (nickel element)
at 10 ppm in terms of weight is applied, and excessive part of the
applied solution is removed by spin drying with the use of a
spinner (not shown).
Thus, there is obtained a state in which nickel exists as indicated
by a broken line 206 in FIG. 1A. In this state, nickel is so held
as to be brought in contact with part of the amorphous silicon film
selectively, i.e., at the bottom of the opening 205.
A heat treatment is performed in this state at 640.degree. C. for 4
hours in a nitrogen atmosphere in which hydrogen is contained at 3%
but the content of oxygen is minimized. As a result, crystal growth
proceeds parallel with the substrate 201 as indicated by arrow 207
in FIG. 1B. FIG. 9B is a top view schematically showing how the
crystal growth proceeds.
This crystal growth proceeds around from the opening 205 from which
nickel has been introduced. This type of crystal growth that is
parallel with the substrate is called lateral growth.
A crystalline silicon film obtained by the lateral growth has a
much smoother surface than a conventional high-temperature or
low-temperature polysilicon film. This is considered due to the
fact that in the former case grain boundaries extend approximately
in the same direction.
General polysilicon films have surface asperities of more than
.+-.100 .ANG.. In contrast, it was observed that silicon films
obtained by lateral growth according to this embodiment have
asperities that are as small as .+-.30 .ANG.. Since the asperities
deteriorate the characteristics of a boundary with a gate
insulating film, they should be as small as possible.
Under the above-mentioned heat treatment conditions for the
crystallization, the lateral growth can proceed over more than 100
.mu.m. Thus, a silicon film 208 having a lateral growth region is
formed.
The heat treatment for the above crystal growth may be performed at
450 1,100.degree. C., the upper limit being restricted by the heat
resistance of the substrate. To obtain a certain lateral growth
length, it is preferred that the heat treatment be performed at
more than 600.degree. C. Even if the temperature is set higher than
600.degree. C., no remarkable improvement is obtained in crystal
growth length or
The silicon oxide mask 204 that was used to selectively introduce
nickel is now removed. Thus, the state of FIG. 1C is obtained.
In this state, nickel does not exist uniformly. In particular,
nickel exists at relatively high concentrations in the opening 205
and the leading portion of the crystal growth indicated by arrows
207. Therefore, in forming an active layer, it is important to
avoid such regions. That is, it is important that an active layer
not include a region where nickel obviously has a higher
concentration than in the other regions.
To improve the crystallinity, laser light irradiation may be
performed in the state of FIG. 2C. The laser light irradiation has
an effect of disperse a cluster of nickel in the film 208, to
thereby facilitate later removal of nickel. The laser light
irradiation at this stage does not cause any further lateral
growth.
The laser light may be excimer laser light having a wavelength in
the ultraviolet range. For example, a KrF excimer laser
(wavelength: 248 nm) or a XeCl excimer laser (wavelength: 308 nm)
may be used.
Next, a heat treatment is performed at 950.degree. C. for 30
minutes or more by an electrical furnace in an oxygen atmosphere
containing HCl at 3 volume %, to form a 200-.ANG.-thick thermal
oxidation film 209. As a result of the formation of the thermal
oxidation film 209, the thickness of the silicon film 208 is
reduced by about 100 .ANG. to about 500 .ANG..
In the above step, silicon elements in an unstable bonding state in
the film 208 are used to form the thermal oxidation film 209, so
that defects in the film 208 are reduced in number and hence a
higher degree of crystallinity is obtained.
At the same time, due to the formation of the thermal oxidation
film 209 and the action of chlorine, nickel elements are gettered
from the film 208.
Naturally nickel is introduced into the thermal oxidation film 209
at a comparatively high concentration, and the nickel concentration
of the silicon film 208 becomes relatively small.
The thermal oxidation film 209 is then removed. Thus, the
crystalline silicon film 208 with a decreased nickel content
remains. As shown in FIGS. 6 and 7, the crystalline silicon film
thus obtained has a crystal structure extending in one direction
(i.e., in the crystal growth direction). That is, a number of long
and thin cylindrical crystallizations extend parallel with each
other in one direction with grain boundaries separating the
crystallizations.
Subsequently, the crystalline silicon film 208 is patterned into a
pattern 210 of a lateral growth region. This island-like region 210
will become a TFT active layer.
The patterning is performed with an orientation that makes the
direction connecting a source region and a drain region at least
substantially coincide with the crystal growth direction. With this
orientation, the carrier movement direction is made equal to the
direction in which crystal lattices extend continuously, to enable
provision of a TFT having superior characteristics.
Thereafter, a 300-.ANG.-thick thermal oxidation film 211 is formed
on the pattern 210 by a heat treatment of 950.degree. C. for 30
minutes or more by an electrical furnace in an oxygen atmosphere
containing HCl at 3%. In this state, the pattern (to become the
active layer) 210 has a total thickness of 350 .ANG. (including the
thickness of the thermal oxidation film 211). A sum of thicknesses
of the thermal oxide films formed is thicker than the final
thickness of the crystalline silicon film.
In the step of forming the thermal oxidation film 211, the same
effects as in forming the thermal oxidation film 209 can be
obtained. The thermal oxidation film 211 will become part of a gate
insulating film of the TFT.
Next, a 1,000-.ANG.-thick silicon oxide film 304 to constitute the
gate insulating film together with the thermal oxidation film 211
is formed by plasma CVD. (FIG. 2A)
A 4,000-.ANG.-thick aluminum film to constitute a gate electrode is
then formed by sputtering. Scandium is included in the aluminum
film at 0.2 wt % to suppress occurrence of hillocks and whiskers in
a later step. Hillocks and whiskers are needle or prickle-like
protrusions as formed by abnormal growth of aluminum.
After the formation of the aluminum film, a dense anodic oxide film
(not shown) is formed in the following manner. The electrolyte is
an ethylene glycol solution containing tartaric acid at 3%.
The aluminum film is used as the anode while platinum is used as
the cathode. In this step, a 100-.ANG.-thick, dense anodic oxide
film is formed on the aluminum film.
The anodic oxide film (not shown) has a role of improving the
adhesion of a resist mask that will be formed later. The thickness
of the anodic oxide film can be controlled by the application
voltage during the anodization.
After a resist mask 306 is formed, the aluminum film is to
patterned into a pattern 305. Thus, the state of FIG. 2B is
obtained.
Anodization is again performed in this state in an electrolyte
which is a 3% aqueous solution of oxalic acid. The aluminum pattern
305 is used as the anode. As a result, a porous anodic oxide film
308 is formed. Since the resist mask 306 is in close contact with
the top face of the aluminum pattern 305, the anodic oxide film 308
is selectively formed on the side face of the aluminum pattern
305.
The thickness of the anodic oxide film 308 can be increased to
several micrometers. In this embodiment, the thickness is set at
6,000 .ANG.. The growth length (i.e., thickness) of the anodic
oxide film 308 can be controlled by the anodization time.
After the resist mask 306 is removed, a dense anodic oxide film is
again formed. That is, anodization is again performed by using the
above-mentioned electrolyte, i.e., an ethylene glycol solution
containing tartaric acid at 3%.
In this step, a dense anodic oxide film 309 is formed as shown in
FIG. 2C because the electrolyte enters into the porous anodic oxide
film 308.
The thickness of the dense anodic oxide film 309 is set at 1,000
.ANG.. The thickness is controlled by the application voltage.
Next, the exposed portions of the silicon oxide film 304 as well as
parts of the thermal oxidation film 300 are etched by dry etching.
The porous anodic oxide film 308 is then removed by using a mixed
acid of acetic acid, nitric acid, and phosphoric acid. Thus, the
state of FIG. 2D is obtained.
Impurity ions are implanted in this state. In this embodiment, P
(phosphorus) ions are implanted by plasma doping to form an
n-channel TFT.
In this step, heavily doped regions 311 and 315 and lightly doped
regions 312 and 314 are formed. This is because the residual
silicon oxide film 310, which serves as a semi-transparent mask,
shields part of ions launched.
The regions doped with impurity ions are then activated by
illuminating those with laser light (or strong light emitted from a
lamp). In this manner, a source region 311, a channel forming
region 313, a drain region 315, and low-concentration impurity
regions 312 and 314 are formed in a self-aligned manner. The region
314 is called a LDD (lightly doped drain) region. (FIG. 2D)
If the dense anodic oxide film is made thicker than 2,000 .ANG.,
offset gate regions as thick as the dense anodic oxide film can be
formed outside the channel forming region 313.
Although offset gate regions are formed even in this embodiment,
they have only little contribution because of their small
dimension, and they are not shown in the drawings to prevent the
drawings from becoming unduly complex.
To make the dense anodic oxide film 309 thicker than 2,000 .ANG.,
an application voltage of more than 200 V is needed. In this case,
sufficient case should be taken for reproducibility and safety.
Next, a silicon oxide film, a silicon nitride film, or a laminate
film thereof is formed as an interlayer insulating film 316.
Alternatively, the interlayer insulating film 316 may be composed
of a silicon oxide film or a silicon nitride film and a resin film
formed thereon.
After contact holes are formed through the interlayer insulating
film 316, a source electrode 317 and a drain electrode 318 are
formed. Thus, a TFT is completed as shown in FIG. 3E.
The TFT of this embodiment exhibits much superior characteristics
that were not obtained conventionally. For example, an NTFT
(n-channel TFT) has a mobility of 200 300 cm.sup.2/V.s and an
S-value of 75 90 mV/dec. (V.sub.D=1 V), and a PTFT (p-channel TFT)
has a mobility of 120 180 cm.sup.2/V.s and an S-value of 75 100
mV/dec. (V.sub.D=1 V).
In particular, the S-value is extremely small, that is, less than
1/2 of the S-values of the conventional high-temperature and
low-temperature silicon TFTs.
Embodiment 2
This embodiment is directed to a case where the gate insulating
film forming method is modified in the manufacturing method of the
first embodiment.
FIGS. 3A 3D show a manufacturing method according to this
embodiment. A crystalline silicon film 208 having a lateral growth
region is formed by the steps of FIGS. 1A and 1B. The thickness of
an amorphous silicon film as a starting film is set at 500
.ANG..
Once the crystalline silicon film 208 is formed, a 200-.ANG.-thick
thermal oxidation film 209 is formed by performing a heat treatment
of 950.degree. C. for 30 minutes or more by an electrical furnace
in an oxygen atmosphere containing HCl at 3%. (FIG. 3A)
After the thermal oxidation film 209 is removed, the crystalline
silicon film 208 is patterned into a pattern 210 which will become
a TFT active layer. (FIG. 3B)
Next, a 1,000-.ANG.-thick gate insulating film 304 is formed by
plasma CVD. (FIG. 3C)
A 300-.ANG.-thick thermal oxidation film 211 is then formed by a
heat treatment of 950.degree. C. for 30 minutes or more by an
electrical furnace in an oxygen atmosphere containing HCl at 3%.
(FIG. 3D)
In this step, the thermal oxidation film grows inside the CVD oxide
film 304 as shown in FIG. 3D. A sum of thicknesses of the thermal
oxide films formed is thicker than the final thickness of the
crystalline silicon film.
When the manufacturing process of this embodiment is employed, the
laminate film of the thermal oxidation film 211 and the CVD oxide
film 304 constitutes a gate insulating film.
When the manufacturing process of this embodiment is employed, the
density of boundary energy states at the boundary between the gate
insulating film and the active layer can be made low.
Embodiment 3
This embodiment is directed to a manufacturing method of an active
matrix circuit region of an active matrix liquid crystal display
device.
FIGS. 4A 4D show a manufacturing process according to this
embodiment. First, the state of FIG. 2D (also shown in FIG. 4A) is
obtained by the process of the first embodiment.
Next, a 2,000-.ANG.-thick silicon nitride film 401 as a first
interlayer insulating film is formed by plasma CVD. A polyimide
resin film 402 is formed thereon by spin coating, to obtain the
state of FIG. 4B. Resin materials other than polyimide, such as
polyamide, polyimideamide and acrylic resin, may also be used.
After contact holes are formed so as to reach the source region 311
and the drain region 315, a source electrode 403 and a drain
electrode 403 are formed each of which is a laminate film of a
titanium film, an aluminum film, and a titanium film. The source
electrode 403 is so formed as to extend from a source line. (FIG.
4C)
Part of the source electrode 403 serves as an electrode for forming
an auxiliary capacitor.
After the formation of the source and drain electrodes 403, a
polyimide resin film 404 as a second interlayer insulating film is
formed. Thus, the state of FIG. 4C is obtained.
Next, after an opening is formed through the resin interlayer
insulating film 404, a black matrix (BM) 405 is formed which is a
laminate film of a titanium film and an aluminum film. The black
matrix 405 serves as an electrode for forming an auxiliary
capacitor as well as a light-shielding film (primary function).
After the formation of the black matrix 405, a polyimide resin film
406 is formed as a third interlayer insulating film. Then, after a
contact hole for the drain electrode 403 is formed, an ITO pixel
electrode 407 is formed.
In this manner, there is obtained a structure in which the
polyimide resin film 406 is interposed between pattern of the black
matrix 405 serving as an auxiliary capacitor and the pixel
electrode 407 pattern.
Embodiment 4
This embodiment is directed to a case where the method of forming a
contact to the gate electrode or a gate line extending from the
gate electrode is modified in the manufacturing method of the first
embodiment.
In the first embodiment (see FIG. 2E) and the third embodiment (see
FIG. 4D), both of the side face and the top face of the gate
electrode are covered with the dense anodic oxide film.
This structure is very effective in suppressing the occurrence of
hillocks and short-circuiting between wiring lines in the case of
forming an electrode made of aluminum. However, this structure has
a problem that it is relatively difficult to form a contact because
the dense anodic oxide film is strong.
This embodiment is intended to solve this problem. FIGS. 5A 5E show
a manufacturing process according to this embodiment. The detailed
manufacturing conditions etc. for forming the components given the
same reference numerals as the corresponding components in the
other embodiments are the same as in those embodiments.
First, an active layer pattern 210 of a crystalline silicon film is
formed as shown in FIG. 5A. Thereafter, a thermal oxidation film
211 and a CVD oxide film 304 are laid one on another. In this
embodiment, the CVD oxide film 304 is formed first and then the
thermal oxidation film 211 is formed.
Once the state of FIG. 5A is obtained, an aluminum film is formed
and a 500-.ANG.-thick silicon nitride film is formed thereon. Then,
patterning is performed by using a resist mask 306, to obtain an
aluminum pattern 305 and a silicon nitride film 501 formed thereon.
(FIG. 5B)
In this state, with the resist mask 306 left as it is, a porous
anodic oxide film 308 is formed and subsequently a dense anodic
oxide film 309 is formed.
These anodic oxide films 308 and 309 are selectively formed on the
side face of the aluminum pattern 307 that will become a gate
electrode. This is because the silicon nitride film 501 is formed
on the top face of the aluminum pattern 307.
The resist mask 306 is then removed. Further, the exposed portions
of the silicon oxide film 304 as well as parts of the thermal
oxidation film 211 are removed.
Thus, the state of FIG. 5C is obtained. Once this state is
obtained, the porous anodic oxide film 308 is removed.
Further, the silicon nitride film 501 is removed to obtain the
state of FIG. 5D. In this state, an impurity for imparting a proper
conductivity type is implanted by plasma doping. As a result, a
source region 311, low-concentration impurity regions 312 and 314,
a channel-forming region 313, and a drain region 315 are formed in
a self-aligned manner.
After the impurity doping, laser light irradiation is performed to
repair the doping damage (annealing) and activate the implanted
impurity.
Thus, the state of FIG. 5D is obtained. Next, an interlayer
insulating film 502 is formed. After contact holes are formed, a
source electrode 317, a gate lead-out electrode 503, a drain
electrode 318 are formed to obtain the state of FIG. 5E.
In this step, the contact hole for the gate electrode 307 can be
formed relatively easily because no silicon oxide film exists on
the top face of the gate electrode 307.
Although in FIG. 5E the source/drain electrodes 317 and 318 and the
gate lead-out electrode 503 are drawn on the same cross-section,
actually the gate lead-out electrode 503 is so formed as to be
connected to an extension of the gate electrode 307.
Embodiment 5
This embodiment is directed to a case where a glass substrate is
used in the manufacturing method of the first embodiment.
In this embodiment, a Corning 1737 glass substrate having a strain
point of 667.degree. C. is used. The heating treatment for
crystallization is performed at 600.degree. C. for 4 hours.
The heating treatment to form a thermal oxidation film is performed
at 640.degree. C. by an electrical furnace in an oxygen atmosphere
containing HCl at 3 volume %. In this case, a resulting thermal
oxidation film has a thickness of 30 .ANG. when the processing time
is 2 hours. The effects of the thermal oxidation film are smaller
than in the case of the first embodiment (heat treatment
temperature: 950.degree. C.)
Embodiment 6
This embodiment is directed to a case where HCl is not contained in
the atmosphere used in forming a thermal oxidation film in the
manufacturing method of the first embodiment. In this case, the
gettering effect of nickel is smaller than in the case where the
atmosphere contains HCl.
Embodiment 7
This embodiment is directed to a case where laser light irradiation
is performed after the formation of a thermal oxidation film in the
manufacturing method of the first embodiment. This effectively
improves the crystallinity.
Embodiment 8
This embodiment is examples of semiconductor devices using TFTs.
FIGS. 8A 8F show various examples of semiconductor devices.
FIG. 8A shows a semiconductor device called a portable information
terminal which can read necessary information from an internal
storage device and display it on an active matrix liquid crystal
display device 2005 that is incorporated in a main body 2001, or
display information obtained by accessing it via telephone lines on
the display device 2005.
An active matrix EL display device may be used instead of the
liquid crystal display device 2005. Various information processing
circuits and a storage circuit are formed on the same substrate as
an active matrix circuit of the display device 2005 by using TFTs,
to together constitute an integrated circuit 2006.
A camera section 2002 attached to a main body 2001 can take in
necessary information upon a manipulation on an operation switch
2004. An image to be taken in by the camera section 2002 is
supplied to the device through an image receiving section 2003.
FIG. 8B shows a display device called a head-mount display. A main
body 2101 of this device is mounted on the head of a user. This
device has a function of displaying an image in front of the eyes
several centimeters apart therefrom with two active matrix liquid
crystal display devices 2102. This device allows the user to see a
virtual image.
FIG. 8C shows a car navigation system. This device has a function
of measuring the position by using a signal coming from an
artificial satellite and received by an antenna 2204. The measured
position is displayed on an active matrix liquid crystal display
device 2202. Information to be displayed is selected by using
operation switches 2203.
An active matrix EL display device may be used instead of the
liquid crystal display device 2202.
FIG. 8D shows a cellular telephone set. A main body 2301 is
equipped with an antenna 2306, a voice input section 2303, and a
voice output section 2302.
A user manipulates operation switches 2305 to make a call. Various
types of image information are displayed on a display device 2304,
which may be either an active matrix liquid crystal display device
or an active matrix EL display device.
FIG. 8E shows a portable video camera. This device has a function
of storing an image that is received by an image receiving section
2406 onto a magnetic tape that is incorporated in a main body
2401.
Various types of digital processing are performed on the image by
an integrated circuit 2407. The integrated circuit 2407 may be a
combination of conventional IC chips or may be constituted by using
TFTs according to the invention. As a further alternative, the
integrated circuit 2407 may be a combination of the above two types
of configurations.
An image received by the image receiving section 2406 or stored in
the internal magnetic tape is displayed on an active matrix liquid
crystal display device 2402. Manipulations on the device are
performed by using operation switches 2404. The device is powered
by a battery 2405.
FIG. 8F shows a projection display device. This device has a
function of projecting onto a screen 2505 an image produced by a
main body 2501.
The main body 2501 has a light source 2502, an active matrix liquid
crystal display device for forming an image by optically modulating
light that is emitted from the light source 2502, and an optical
system 2504 for projecting the image thus formed.
In the above devices, the liquid crystal display device may be
either of a transmission type or of a reflection type except for
the device of FIG. 8B.
A 9-stage ring oscillator was constructed by combining PTFTs and
NTFTs produced according to the invention. Oscillation at more than
400 MHz was attained in this ring oscillator.
In view of the fact that actual circuits are generally designed at
a frequency that is about 10% of the oscillation frequency of a
ring oscillator, it is concluded that a circuit capable of
operating at about 40 MHz can be constructed by using the above
TFTs.
As exemplified above, the invention can provide TFTs which can
constitute a circuit that is required to operate at high speed (in
general, at more than several tens of megahertz).
In particular, the invention provides a very small S value (less
than 100 mV/dec.), which is equivalent to an S value of a MOS
transistor formed on a single crystal silicon wafer.
The invention allows various circuits that are required to operate
at high speed to be integrated on the same substrate by using TFTs.
Further, the invention provides a manufacturing method of such a
configuration.
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