U.S. patent number 7,047,513 [Application Number 10/334,692] was granted by the patent office on 2006-05-16 for method and apparatus for searching for a three-dimensional global path.
This patent grant is currently assigned to Cadence Design Systems, Inc.. Invention is credited to Jonathan Frankle, Steven Teig.
United States Patent |
7,047,513 |
Teig , et al. |
May 16, 2006 |
**Please see images for:
( Certificate of Correction ) ** |
Method and apparatus for searching for a three-dimensional global
path
Abstract
Some embodiments of the invention provide a method of searching
for a three-dimensional global path between first and second sets
of routable elements in a region of a layout that has multiple
layers. The method partitions the region into several sub-regions.
It then performs a path search to identify a path between a first
set of sub-regions that contains the first-set elements and a
second set of sub-regions that contain a second-set element. When
the method performing the path search, it explores expansions along
Manhattan and non-Manhattan routing directions between the
sub-regions on a plurality of layers.
Inventors: |
Teig; Steven (Menlo Park,
CA), Frankle; Jonathan (Los Gatos, CA) |
Assignee: |
Cadence Design Systems, Inc.
(San Jose, CA)
|
Family
ID: |
32302289 |
Appl.
No.: |
10/334,692 |
Filed: |
December 31, 2002 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20040098680 A1 |
May 20, 2004 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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60427131 |
Nov 18, 2002 |
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Current U.S.
Class: |
716/129; 716/130;
716/134; 716/131 |
Current CPC
Class: |
G06F
30/394 (20200101) |
Current International
Class: |
G06F
17/50 (20060101) |
Field of
Search: |
;716/1-18 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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64-015947 |
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Jan 1989 |
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JP |
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02-262354 |
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Oct 1990 |
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JP |
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03-173471 |
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Jul 1991 |
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JP |
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04-000677 |
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Jan 1992 |
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JP |
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05-102305 |
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Apr 1993 |
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JP |
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05-243379 |
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Sep 1993 |
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JP |
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07-086407 |
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Mar 1995 |
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JP |
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09-162279 |
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Jun 1997 |
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JP |
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11-296560 |
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Oct 1999 |
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JP |
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2000-82743 |
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Mar 2000 |
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JP |
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Primary Examiner: Smith; Matthew
Assistant Examiner: Tat; Binh
Attorney, Agent or Firm: Stattler Johansen & Adeli
LLP
Parent Case Text
CLAIM OF BENEFIT TO PRIOR APPLICATION
This patent application claims the benefit of U.S. Provisional
Patent Application 60/427,131, filed Nov. 18, 1902.
Claims
We claim:
1. A method of searching for a three-dimensional global route path
between first and second sets of routable elements in a region of a
layout that has multiple layers, the method comprising: a)
partitioning the region into a plurality of sub-regions; and b)
performing a path search to identify a global route path between a
first set of sub-regions that contains the first-set elements and a
second set of sub-regions that contains a second-set element, c)
wherein performing the path search comprises exploring expansions
along Manhattan and non-Manhattan routing directions between the
sub-regions on a plurality of layers.
2. The method of claim 1, wherein partitioning the region comprises
partitioning each layer of the layout into a plurality of
sub-regions, wherein the sub-regions are reachable along different
routing directions on different layers.
3. The method of claim 2, wherein the sub-regions are reachable
along Manhattan directions on some layers, and are reachable along
diagonal directions on other layers.
4. The method of claim 2, wherein performing the path search
further comprises exploring non-planar expansions between
sub-regions on different layers.
5. The method of claim 4, wherein exploring non-planar expansions
comprises identifying on one layer a first sub-regions that is
reachable from a second sub-region on another layer.
6. The method of claim 5, wherein the layers of the first and
second sub-regions have diagonal routing directions that are not
parallel.
7. The method of claim 6, wherein the diagonal routing directions
of the first and second sub-regions are orthogonal.
8. The method of claim 7, wherein the first and second sub-regions
are not directly overlapping sub-regions.
9. The method of claim 8, wherein the sub-regions are a first group
of sub-regions, wherein partitioning the region further comprises
partitioning the region into a second group of sub-regions, wherein
each second-group sub-region includes a plurality of first-group
sub-regions, wherein the first and second sub-regions are in the
same second-group sub-region.
10. The method of claim 8, wherein the sub-regions are a first
group of sub-regions, wherein partitioning the region further
comprises partitioning the region into a second group of
sub-regions, wherein each second-group sub-region includes a
plurality of first-group sub-regions, wherein the first and second
sub-regions are in different second-group sub-regions.
11. The method of claim 1, wherein exploring expansions comprises:
a) identifying the start of at least one path; b) iteratively
identifying a set of expansions about previously identified paths
until identifying a path that connects the two sets.
12. The method of claim 11 further comprising: wherein each path
terminates in a sub-region; wherein identifying an expansion about
the path comprises identifying sub-regions that are reachable from
the path's terminating sub-region.
13. A method of specifying a global route path in a region of a
layout that has multiple layers, wherein one layer has a first
preferred routing direction and another layer has a second
preferred routing direction, wherein the first and second preferred
routing directions are neither orthogonal nor parallel to each
other, the method comprising: a) identifying first and second sets
of elements to connect by a global route path; and b) identifying a
set of path expansions between the two sets, wherein at least one
of the path expansions is a via expansion between the two layers
with the first and second preferred routing directions, c) wherein
the set of path expansions define the global route path between the
first and second sets of elements.
14. The method of claim 13, wherein identifying the set of path
expansions comprises: a) identifying the start of at least one
path; b) iteratively identifying a set of expansions about
previously identified paths until identifying a path that connects
the two sets.
15. The method of claim 14, wherein iteratively identifying the set
of expansions comprises iteratively identifying a set of expansions
about a current lowest-cost path until identifying a path that
connects the two sets.
16. The method of claim 14 further comprising: specifying a
plurality of nodes in a graph that represents the layout region;
wherein each path terminates on a node; wherein identifying an
expansion about a path comprises identifying nodes that are
reachable from the path's terminating node.
17. The method of claim 16, wherein the graph has one layer
corresponding to each layer of the layout, wherein the nodes are
specified in each layer of the graph, wherein nodes are reachable
along different routing directions on different layers, wherein at
least some of these different routing directions are neither
parallel nor orthogonal to each other.
18. The method of claim 17, wherein nodes are reachable along
Manhattan directions on some layers, and are reachable along
diagonal directions on other layers.
19. The method of claim 14 further comprising: partitioning the
region into a plurality of sub-regions; wherein each path
terminates in a sub-region; wherein identifying an expansion about
the path comprises identifying sub-regions that are reachable from
the path's terminating sub-region.
20. The method of claim 19, wherein partitioning the region
comprises partitioning each layer of the layout into a plurality of
sub-regions, wherein the sub-regions are reachable along different
routing directions on different layers, wherein at least some of
these different muting directions are neither parallel nor
orthogonal to each other.
21. The method of claim 20, wherein the sub-regions are reachable
along Manhattan directions on some layers, and are reachable along
diagonal directions on other layers.
22. The method of claim 21, wherein identifying reachable
sub-regions comprises identifying on one layer a first sub-regions
that is reachable from a second sub-region on another layer,
wherein the layers of the first and second sub-regions have
diagonal routing directions that are not parallel.
23. The method of claim 22, wherein the diagonal routing directions
of the first and second sub-regions are orthogonal.
24. The method of claim 23, wherein the first and second
sub-regions are not directly overlapping sub-regions.
25. The method of claim 23, wherein the sub-regions are a first set
of sub-regions, wherein partitioning the region further comprises
partitioning the region into a second set of sub-regions, wherein
each second-set sub-region includes a plurality of first-set
sub-regions, wherein the first and second sub-regions are in the
same second-set sub-region.
26. The method of claim 23, wherein the sub-regions are a first set
of sub-regions, wherein partitioning the region further comprises
partitioning the region into a second set of sub-regions, wherein
each second-set sub-region includes a plurality of first-set
sub-regions, wherein the first and second sub-regions are in
different second-set sub-regions.
27. A computer readable medium that stores a computer program for
searching for a three-dimensional global route path between first
and second sets of routable elements in a region of a layout that
has multiple layers, the computer program comprising sets of
instructions for: a) partitioning the region into a plurality of
sub-regions; and b) performing a path search to identify a global
route path between a first set of sub-regions that contains the
first-set elements and a second set of sub-regions that contain a
second-set element, c) wherein performing the path search comprises
exploring expansions along Manhattan and non-Manhattan routing
directions between the sub-regions on a plurality of layers.
28. The computer readable medium of claim 27, wherein the set of
instructions for partitioning the region comprises a set of
instructions for partitioning each layer of the layout into a
plurality of sub-regions, wherein the sub-regions are reachable
along different muting directions on different layers.
29. The computer readable medium of claim 28, wherein the
sub-regions are reachable along Manhattan directions on some
layers, and are reachable along diagonal directions on other
layers.
30. The computer readable medium of claim 28, wherein the set of
instructions for performing the path search further comprises a set
of instructions for exploring non-planar expansions between
sub-regions on different layers.
31. The computer readable medium of claim 30, wherein the set of
instructions for exploring non-planar expansions comprises a set of
instructions for identifying on one layer a first sub-regions that
is reachable from a second sub-region on another layer.
32. The computer readable medium of claim 31, wherein the layers of
the first and second sub-regions have diagonal routing directions
that are not parallel.
33. The computer readable medium of claim 32, wherein the diagonal
routing directions of the first and second sub-regions are
orthogonal.
34. The computer readable medium of claim 33, wherein the first and
second sub-regions are not directly overlapping sub-regions.
35. The computer readable medium of claim 34, wherein the
sub-regions are a first group of sub-regions, wherein the set of
instructions for partitioning the region further comprises a set of
instructions for partitioning the region into a second group of
sub-regions, wherein each second-group sub-region includes a
plurality of first-group sub-regions, wherein the first and second
sub-regions are in the same second-group sub-region.
36. The computer readable medium of claim 34, wherein the
sub-regions are a first group of sub-regions, wherein the set of
instructions for partitioning the region further comprises a set of
instructions for partitioning the region into a second group of
sub-regions, wherein each second-group sub-region includes a
plurality of first-group sub-regions, wherein the first and second
sub-regions are in different second-group sub-regions.
Description
FIELD OF THE INVENTION
The invention is directed towards a method and apparatus for
searching for a three-dimensional global path.
BACKGROUND OF THE INVENTION
An integrated circuit ("IC") is a device (e.g., a semiconductor
device) that includes many electronic components, such as
transistors, resistors, diodes, etc. These components are often
interconnected to form multiple circuit components, such as gates,
cells, memory units, arithmetic units, controllers, decoders, etc.
An IC includes multiple layers of wiring that interconnect its
electronic and circuit components. Traditionally, IC's use
preferred direction ("PD") wiring models, which specify a preferred
wiring direction for each of their wiring layers. In preferred
direction wiring models, the preferred direction typically
alternates between successive wiring layers. One example of a PD
wiring model is the PD Manhattan wiring model, which specifies
alternating layers of preferred-direction horizontal and vertical
wiring.
Design engineers design IC's by transforming logical or circuit
descriptions of the IC's into geometric descriptions, called
layouts. IC layouts typically include (1) circuit modules (i.e.,
geometric representations of electronic or circuit IC components)
with pins, and (2) interconnect lines (i.e., geometric
representations of wiring) that connect the pins of the circuit
modules. A net is typically defined as a collection of pins that
need to be connected. A list of all or some of the nets in a layout
is referred to as a net list.
To create layouts, design engineers typically use electronic design
automation ("EDA") applications. These applications provide sets of
computer-based tools for creating, editing, and analyzing IC design
layouts. One EDA tool is a router that defines routes for
interconnect lines that connect the pins of nets. Routing is
generally divided into two phases: global routing and detailed
routing. For each net, global routing generates a "loose" route for
the interconnect lines that are to connect the pins of the net. The
"looseness" of a global route depends on the particular global
router used. After global routes have been created, the detailed
routing creates specific individual routes for each net.
While some commercial global routers today might allow an
occasional diagonal jog, these routers do not typically explore
diagonal routing directions consistently when they are specifying
the routing geometries of the interconnect lines. This, in turn,
increases the total wirelength (i.e., total length of interconnect
lines) needed to connect the nets in the layout. Therefore, there
is a need for a routing method and apparatus that considers
diagonal routing directions. There is also a need for a new way of
identifying and costing routes.
SUMMARY OF THE INVENTION
Some embodiments of the invention provide a method of searching for
a three-dimensional global path between first and second sets of
routable elements in a region of a layout that has multiple layers.
The method partitions the region into several sub-regions. It then
performs a path search to identify a path between a first set of
sub-regions that contains the first-set elements and a second set
of sub-regions that contain a second-set element. When the method
performing the path search, it explores expansions along Manhattan
and non-Manhattan routing directions between the sub-regions on a
plurality of layers.
BRIEF DESCRIPTION OF THE DRAWINGS
The novel features of the invention are set forth in the appended
claims. However, for purpose of explanation, several embodiments of
the invention are set forth in the following figures.
FIG. 1 illustrates a 4.times.4 section of a congestion grid.
FIG. 2 illustrates a section of a length grid that divides each
Gcell created by the congestion grid into four nodes.
FIG. 3 illustrates the four nodes in each Gcell on a particular
layer.
FIGS. 4 7 illustrate the directions of edges on interconnect layers
2 5 in some embodiments of the invention.
FIG. 8 illustrates edges that cross the Gcells created by the
congestion grid.
FIGS. 9 12 illustrate four examples of internal zigs between the
four nodes of a Gcell.
FIG. 13 presents a three-dimensional side view of the example
illustrated in FIG. 9.
FIGS. 14 21 illustrate eight examples of external zigs between the
four nodes of a particular Gcell and the eight nodes in four Gcells
that are adjacent to the particular Gcell.
FIG. 22 presents a three-dimensional side view of the example
illustrated in FIG. 14.
FIG. 23 illustrates a via location in a Gcell.
FIG. 24 illustrates a via location in another Gcell.
FIG. 25 illustrates a process that conceptually represents the
overall flow of the router in some embodiments of the
invention.
FIGS. 26A, 26B, and 26C present three examples that illustrate how
some embodiments compute the capacity of a congestion edge between
two Gcells on a given layer.
FIG. 27 illustrates a route-generation process that the routing
process uses to generate a route for a particular net in some
embodiments of the invention.
FIG. 28 presents one example of shadow nodes.
FIG. 29 illustrates a path-generation process that the
route-generation process uses in some embodiments.
FIG. 30 illustrates an example of a back trace operation used by
the path-generation process of FIG. 29.
FIG. 31 conceptually illustrates a computer system with which one
embodiment of the invention is implemented.
FIG. 32 illustrates an example of a multi-layer global route that
is produced by a router of some embodiments of the invention.
DETAILED DESCRIPTION OF THE INVENTION
In the following description, numerous details are set forth for
purpose of explanation. However, one of ordinary skill in the art
will realize that the invention may be practiced without the use of
these specific details. In other instances, well-known structures
and devices are shown in block diagram form in order not to obscure
the description of the invention with unnecessary detail.
Several embodiments of the invention provide a router that routes a
set of nets in a region of an integrated circuit ("IC") layout.
Each routed net includes a set of routable elements in the
IC-layout region. The routable elements are pins in the embodiments
described below, although they might be other elements in other
embodiments.
In the embodiments described below, the router uses a five-layer
wiring model that has horizontal wiring on wiring layer 1, vertical
wiring on wiring layer 2, horizontal wiring on wiring layer 3,
+45.degree. diagonal wiring on wiring layer 4, and -45.degree.
diagonal wiring on wiring layer 5. One of ordinary skill will
realize that the router can use other wiring models in other
embodiments. In some embodiments, a line is "diagonal" if it forms
an angle other than 0.degree. or 90.degree. with respect to the
layout's Cartesian coordinate axes, which are typically parallel
with the layout's boundary and/or the boundary of the layout's
expected IC. On the other hand, an interconnect line is
"horizontal" or "vertical" if it forms an angle of 0.degree. or
90.degree. with respect to one of the coordinate axes of the
layout.
In the embodiments described below, the router partitions an
IC-layout region into several square sub-regions. For each net
being routed, the router then identifies a global route that
connects the set of sub-regions that contain at least one pin of
the net. Each net's global route is a set of edges (i.e.,
interconnect lines) that connects the set of sub-regions that
contain the net's pins. The identified routes might have
horizontal, vertical, and .+-.45.degree. diagonal edges in the
embodiments described below.
In these embodiments, the edges that are used to define each route
are part of a routing graph used by the router. Section I provides
an overview of this routing graph. Next, Section II provides the
overall flow of the router. Section III then describes
route-generation and path-generation processes used by the router.
Section IV describes a computer system that can be used to
implement some embodiments of the invention.
I. Routing Graph, Congestion Grid, and Length Grid
In some embodiments, the router uses two grids to create a routing
graph. The first grid is a coarser grid that divides the IC layout
into a number of sub-regions, called Gcells. The second grid is a
finer grid that divides each Gcell into four sub-regions. In the
embodiments described below, the Gcells are square. This shape well
supports .+-.45.degree. routing, as any set of .+-.45.degree.
wiring tracks that cut through a square Gcell will fill its
horizontal and vertical boundaries consistently. One of ordinary
skill will realize that other embodiments might use different
shaped Gcells.
On each wiring layer, each of the four sub-regions in each Gcell is
represented by a node at the center of the sub-region. The
embodiments described below use the coarser grid to measure route
congestion in the layout region, and use the finer grid to measure
route lengths. Accordingly, below, the coarser grid is referred to
as the congestion grid, while the finer grid is referred to as the
length grid.
FIGS. 1 and 2 illustrate small sections of the congestion and
length grids. As shown in these figures, intersecting horizontal
and vertical lines form both these grids. FIG. 1 illustrates a
4.times.4 section of the congestion grid 100. This section divides
a portion of an IC region into 16 Gcells 105. In the embodiments
described below, the congestion grid divides the IC region into
many more Gcells (e.g., tens or hundreds of thousands).
FIG. 2 illustrates a section of the length grid 200 that
corresponds to the section of the congestion grid 100 illustrated
in FIG. 1. As shown in this figure, the length grid divides each
Gcell 105 into four nodes 205 on each wiring layer. FIG. 3
illustrates the four nodes in each Gcell on a particular layer.
There are a number of planar and non-planar edges between the nodes
defined by the length grid 200. These edges are referred to as
"node edges" in the discussion below.
A. Planar Edges
A planar node edge connects two adjacent routing-graph nodes. Each
such edge represents a set of wiring tracks along the edge's
particular direction that connect the two sub-regions represented
by the edge's two nodes. Planar node edges have different
directions on different wiring layers. FIGS. 4 through 7 illustrate
the directions of these edges on layers 2 5 in some embodiments.
Some embodiments assume that there are no planar node edges between
routing-graph nodes on layer 1, as this layer is often quite
congested. Some of these embodiments promote all the pins on layer
1 to layer 2. Other embodiments, however, specify planar node edges
on layer 1. In some of these embodiments, the planar node edges on
layer 1 are in the same direction as node edges on layer 3.
FIG. 4 illustrates that on layer 2 a vertical node edge 405 exists
between each pair of vertically adjacent nodes, while FIG. 5
illustrates that on layer 3 a horizontal node edge 505 exists
between each pair of horizontally adjacent nodes. FIGS. 6 and 7
illustrate that on layers 4 and 5, .+-.45.degree. diagonal node
edges exist only between certain pairs of diagonally adjacent
nodes. Specifically, FIG. 6 illustrates that 45.degree. diagonal
node edges exist between northwest nodes 605 and southeast nodes
610 of different Gcells. As shown in this figure, no 45.degree.
diagonal node edges are incident on northeast nodes 615 and
southwest nodes 620. FIG. 7 illustrates that -45.degree. diagonal
node edges exist between northeast node 615 and southwest nodes 620
of different Gcells. As shown in this figure, no -45.degree.
diagonal node edges are incident on northwest nodes 605 and
southeast nodes 610.
In the embodiments described below, each Manhattan node edge on
layer 2 or 3 has a unit length cost (L). In these embodiments, each
diagonal node edge on layer 4 or 5 has a length cost that equals
the unit length cost times the square root of two (L* {square root
over (2)}). Also, the use of a node edge across a Gcell boundary
reduces the capacity of the boundary, and is thereby assessed a
wire congestion cost.
The router examines wire congestion at Gcell boundaries on each
layer available for routing. Specifically, on each
available-routing layer, the router computes capacities at Gcell
boundaries for wiring along the particular layer's direction. On a
particular layer, the wiring resources (i.e., wiring tracks) across
a Gcell boundary can be conceptually represented as a planar
"congestion edge" across that boundary on the particular layer in
the layer's wiring direction.
FIG. 8 presents a two-dimensional diagram that illustrates the
congestion edges on layers 2 5 for the routing directions
illustrated in FIGS. 4 7. FIG. 8 illustrates one horizontal
congestion edge across each vertical boundary between horizontally
adjacent Gcells, one vertical congestion edge across each
horizontal boundary between vertically adjacent Gcells, and two
.+-.45.degree. diagonal congestion edges across each boundary
between each pair of adjacent Gcells. In this example, each
vertical congestion edge is on layer 2, each horizontal congestion
edge is on layer 3, each 45.degree. congestion edge is on layer 4,
and each -45.degree. congestion edge is on layer 5.
The router keeps track of one congestion-grid capacity on each
layer at each boundary between adjacent Gcells. Accordingly, each
congestion edge is associated with all node edges that cross the
same Gcell boundary on the same layer as the congestion edge. As
illustrated in FIGS. 4 7, certain planar node edges cross the Gcell
boundaries. In the embodiments described below, certain non-planar
edges between layers 4 and 5 cross Gcell boundaries. These
non-planar edges are further described in Section I.B.3.
In some embodiments that use the wiring model illustrated in FIGS.
4 7, the association between the congestion edges and the node
edges is as follows. Each horizontal congestion edge on layer 3 is
associated with the pair of horizontal node edges that cross the
same Gcell boundary as the horizontal congestion edge on the layer
3. Each vertical congestion edge on layer 2 is associated with the
pair of vertical node edges that cross the same Gcell boundary as
the vertical congestion edge on layer 2.
Each 45.degree. diagonal congestion edge on layer 4 (1) is
associated with a 45.degree. diagonal node edge that crosses the
same Gcell boundary as the 45.degree. diagonal congestion edge on
layer 4, and (2) can be associated with two non-planar node edges
between layers 4 and 5 that cross the same Gcell boundary as the
45.degree. congestion edge. Each -45.degree. diagonal congestion
edge on layer 5 (1) is associated with a -45.degree. diagonal node
edge that crosses the same Gcell boundary as the -45.degree.
diagonal congestion edge on layer 5, and (2) can be associated with
two non-planar node edges between layers 4 and 5 that cross the
same Gcell boundary as the -45.degree. congestion edge. The
association between .+-.45.degree. congestion edges and non-planar
node edges will be described below in Section I.B.3.
Node edges start and terminate on nodes. Congestion edges, on the
other hand, do not have explicit start and end points in some
embodiments. This is because unlike node edges that are used to
define routes, congestion edges function only to evaluate usage
versus capacity. The router's use of node and congestion edges is
further described below.
B. Non-Planar Edges: Vias.
In the embodiments described below, the router can define routes
that use non-planar node edges. In these embodiments, non-planar
node edges exist (1) between each pair of nodes that are
overlapping and that are in two adjacent routing layers (e.g., are
in layers 2 and 3), (2) between certain pairs of non-overlapping
nodes that are within the same Gcell and that are on adjacent
diagonal layers 4 and 5, and (3) between certain pairs of
non-overlapping nodes that are within adjacent Gcells and that are
on adjacent diagonal layers 4 and 5. Each non-planar node edge
represents a via between the two layers traversed by the edge. A
non-planar edge that is between non-overlapping nodes in layers 4
and 5 also represents wiring to and from the edge's via. Each of
the non-planar edge types will now be described further.
1. Non-Planar Edge between Overlapping Nodes.
The routing graph includes a non-planar node edge between each pair
of overlapping nodes that are on two adjacent routing layers. Each
such non-planar edge represents a via between the edge's two nodes.
Each such edge is assessed a wirelength cost and a via congestion
cost. The wirelength cost equals a via-scalar factor (X) times the
unit length cost (L) (i.e., is assessed a wirelength cost X*L). The
via-scalar factor is 1 in some embodiments, while it is greater or
less than one in other embodiments. The use of any non-planar edge
also incurs a via congestion cost that represents the potential
difficulty in placing too many vias between the two layers
traversed by the non-planar edge in the Gcell associated with the
non-planar edge's via. For a non-planar edge between two
overlapping nodes, the Gcell associated with the edge's vias is the
Gcell containing the two nodes.
2. Non-Planar Edges between Non-Overlapping Nodes in the Same
Gcell: Internal Zigs
Non-planar node edges exist between certain pairs of
non-overlapping nodes that are within the same Gcell and that are
on adjacent diagonal layers 4 and 5. Such non-overlapping nodes are
called internal zigs. FIGS. 9 through 12 illustrate four internal
zigs that some embodiments define between layers 4 and 5 in a
Gcell. Each of these figures presents a two-dimensional top view of
the routing graph. FIG. 13 presents a three-dimensional side view
of the example illustrated in FIG. 9.
In FIGS. 9 and 13, an internal zig 900 goes from a northwest node
905 on layer 4 to a northeast node 910 on layer 5 in a Gcell 920.
On layer 4, 45.degree. node edges run through northwest nodes (such
as node 905) but not through northeast nodes (such as node 910).
Conversely, on layer 5, -45.degree. node edges run through
northeast nodes (such as node 910) but not through northwest nodes
(such as node 905). Accordingly, the internal zig 900 allows a
route running through node 905 or 910 to change layers and
directions. As shown in FIGS. 9 and 13, this zig has three
components. Two of its components are planar segments, where one
segment is a 45.degree. edge that runs northerly from the
sub-region represented by node 905 on layer 4, while the other
segment is a -45.degree. edge that runs southerly to the sub-region
represented by node 910 on layer 5. The third component is a
non-planar component that is at the location where the two planar
components overlap. The non-planar component represents a via,
while the planar components represent wiring to and from the via.
FIGS. 9 and 13 show the location of this intersection (i.e., the
via location) to be on the Gcell boundary. However, in a detailed
route representation of the internal zig 900, this intersection
might occur anywhere within the sub-region 935 illustrated in FIG.
9.
The embodiments described below assess three costs for the internal
zig 900. First, an internal zig is assessed a wirelength cost that
equals a via-scalar factor (X) times the unit length cost (L)
(i.e., is assessed a wirelength cost X*L). Second, an internal zig
is assessed an additional wirelength cost, which is the unit length
cost times the square root of two (i.e., it is L* {square root over
(2)}). This additional wirelength cost represents the approximate
wirelength necessary to traverse to and from the actual via
location. Third, there is a via congestion cost associated with the
internal zig. This via congestion cost represents the potential
difficulty in placing too many vias between the two layers
traversed by the internal zig in the Gcell associated with this
zig's via. The Gcell associated with an internal zig's via is the
Gcell containing the two nodes of the zig.
As mentioned above, the internal zig might not result in a via in
Gcell 920 but might result in a via in Gcell 925 above it.
Accordingly, unlike the embodiments described below, other
embodiments might assess a via congestion cost for the Gcell 925
and/or assess a wire congestion cost to account for the congestion
that the wiring associated with the internal zig might cause across
the boundary between Gcells 920 and 925. As further described below
for external zigs, via and wire congestion costs should be
accounted for together, as the location of the via will determine
the layer on which wires cross the congestion grid. Via congestion
and wire congestion costs are further described below.
The internal zigs 1000, 1100, and 1200 that are illustrated in
FIGS. 10, 11, and 12 are analogous to the internal zig 900, except
that they connect different pairs of nodes in the Gcell 920. These
three zigs are costed in the same manner as the zig 900.
3. Non-Planar Edges between Non-Overlapping Nodes in the Adjacent
Gcells: External Zigs
Non-planar node edges exist between certain pairs of
non-overlapping nodes that are within adjacent Gcells and that are
on adjacent diagonal layers 4 and 5. Such non-overlapping nodes are
called external zigs. FIGS. 14 through 21 illustrate eight external
zigs that some embodiments define between one of four nodes of a
particular Gcell (920) and one of eight nodes in the four Gcells
(1410, 1415, 1420, and 1425) that are adjacent to the particular
Gcell (920). Each of these figures presents a two-dimensional top
view of the routing graph. FIG. 22 presents a three-dimensional
side view of the example illustrated in FIG. 14.
FIGS. 14 and 22 illustrate an external zig 1400 between the node
930 on layer 4 of the Gcell 920 and the node 1405 on layer 5 of the
Gcell 1410, which is adjacent to Gcell 920. On layer 4, 45.degree.
node edges run through southeast nodes (such as node 930) but not
through southwest nodes (such as node 1405). Conversely, on layer
5, -45.degree. node edges run through southwest nodes (such as node
1405) but not through southeast nodes (such as node 930).
Accordingly, the external zig 1400 allows a route running through
node 930 or 1405 to change layers and directions.
This zig traverses has three different components. Two of its
components are planar segments, where one segment is a 45.degree.
edge that runs northerly from the sub-region represented by node
930 on layer 4, while the other segment is a -45.degree. edge that
runs southerly to the sub-region represented by node 1405 on layer
5. The third component is a non-planar component that is at the
location where the two planar components overlap. The non-planar
component represents a via, while the planar components represent
wiring to and from the via.
There are four costs associated with the external zig 1400. First,
an external zig is assessed a wirelength cost that equals a
via-scalar factor (X) times the unit length cost (L) (i.e., is
assessed a wirelength cost X*L). Second, the external zig is
assessed an additional wirelength cost, which is the unit length
cost times square root of two (i.e., it is L* {square root over
(2)}). This extra wirelength cost represents the approximate
wirelength necessary to traverse to and from the actual via
location.
The third and fourth cost components are the via congestion cost
and the wire congestion cost. As mentioned above, the use of any
non-planar edge incurs a via congestion cost that represents the
potential difficulty in placing too many vias between the two
layers traversed by the non-planar edge in the Gcell associated
with the non-planar edge's via. The wire congestion cost, on the
other hand, represents the congestion that the wiring associated
with the external zig causes across the Gcell boundary crossed by
the external zig.
The via and wire congestion costs of an external zig depend on the
actual location of the via represented by the external zig.
However, an external zig specifies only that a via between layers 4
and 5 is placed close to the boundary between two Gcells (e.g.,
Gcells 920 and 1410), and does not specify an actual location of
the via between layers 4 and 5. In other words, an external zig can
be associated with a via location in either of the two Gcells that
it traverses, and can be associated with either of the two diagonal
congestion edges that are defined across the boundary between the
two Gcells. Consequently, in some embodiments, the router
associates the external zig with one of the Gcells and one of the
diagonal congestion edges, in order to assign the via and wire
congestion costs for using the external zig. To do this, the router
first computes two sets of via and wire congestion costs, where (1)
the first set is based on a via location in one Gcell and on a
Gcell boundary-crossing along a particular congestion edge, and (2)
the second set is based on a via location in the other Gcell and on
a Gcell-boundary crossing along the other congestion edge. The
router then identifies the set with the smaller aggregate via and
wire congestion costs. It then specifies the external zig's via
location and congestion edge as the identified set's via location
and congestion edge.
For instance, in FIGS. 14 and 22, the via for the external zig 1400
can be located in Gcell 920 or Gcell 1410. Accordingly, a first set
of via and wire congestion costs V1 and W1 is computed based on an
assumption that a detail route generated from the external zig 1400
would result in a via location in Gcell 920. FIG. 23 illustrates
such a via location. For such a location, the via congestion cost
V1 is computed. The cost V1 represents the increase in the via
congestion between layers 4 and 5 in the Gcell 920. Section III
will describe how via congestion costs are computed in some
embodiments.
As shown in FIG. 23, the via location in Gcell 920 will require a
-45.degree. edge to cross the congestion-grid boundary 1430 between
Gcells 920 and 1410 on layer 5. Hence, for this via location, the
wire congestion cost W1 is computed. The cost W1 represents the
increase in the congestion in the -45.degree. direction on layer 5
across the Gcell boundary 1430. This wire congestion cost is
computed by reference to the capacity and usage of congestion edge
2305, which represents the wiring tracks in the 45.degree.
direction across the Gcell boundary 1430. Section III will describe
how wire congestion costs are computed in some embodiments.
For the external zig 1400, FIG. 24 illustrates a via location in
Gcell 1410. A second set of via and wire congestion costs V2 and W2
is computed for this via location. The via congestion cost V2
represents the increase in the via congestion between layers 4 and
5 in the Gcell 1410. Also, as shown in FIG. 24, this via location
will require a 45.degree. edge to cross the boundary 1430 on layer
4. Hence, for this via location, the wire congestion cost W2
represents the increase in congestion cost in the 45.degree.
direction on layer 4 across the Gcell boundary 1430. This wire
congestion cost is computed by reference to the capacity and usage
of congestion edge 2310, which represents the wiring resources in
the 45.degree. direction across the Gcell boundary 1430.
Once the two sets of costs are computed for the example in FIGS. 14
and 22, two aggregate values A1 and A2 are obtained by using a
linear equation to sum the via and wire costs in each set. For
instance, in some embodiments, A1 equals a*V1+b*W1, while A2 equals
a*V2 +b*W2, where a and b are scalar values. The scalar values a
and b are equal to 1 in some embodiments, while, in other
embodiments, they differ from each other and/or are greater or less
than 1.
After computing the aggregate values, the external zig is
associated with the set that results in the smaller aggregate
value. For instance, if the aggregate value A1 of the first set is
smaller than the second set's aggregate value A2 in the example
illustrated in FIGS. 23 and 24, the via location, edge crossing,
and via and wire congestion costs of the first set are selected as
the via location, edge crossing, and via and wire congestion costs
of the external zig 1400. In other words, the router specifies the
Gcell 920 as the Gcell that contains the via of the external zig
1400. It associates this external zig with the congestion edge 2305
(i.e., with a -45.degree. edge crossing on layer 5). The router
also specifies this external zig's incremental via and wire
congestion costs as the values V1 and W1 (i.e., as the first-set
incremental via and wire congestion costs).
The via and wire congestion costs in and across Gcells are values
that continually evolve as the router embeds more routes. Hence,
each time the router explores using a non-planar edge, the router
uses the above-described approach to select the optimal via
location and edge crossing for an external zig at that time.
The external zigs 1500 2100 that are illustrated in FIGS. 15 21 are
analogous to the external zig 1400, except that they connect
different node pairs. These seven external zigs 1500 2100 are
costed in exactly the same manner as the zig 1400.
C. Route Representation With Respect to the Length and Congestion
Edges
As described below, the router identifies the global route for a
net by performing one or more path searches that identify one or
more route segments that connect one or more pairs of pins/Steiner
points of the net. Each path search tries to identify a path
between two sets of nodes associated with the net along the node
edges. If the path search identifies a path between the two sets,
it embeds the identified path by reference to the node edges that
the path traversed to go from one node set to the other. Hence, the
router ends up defining each net's route in terms of the node
edges.
However, in several instances, the discussion below refers to
congestion edges used by a route or a path, where a path is an
actual or potential portion of a route. A route or path is said to
use a particular congestion edge if it is defined by reference to a
planar or non-planar node edge that crosses the same boundary as
the congestion edge on the same layer as the congestion edge. In
other words, a route or path is said to use a particular congestion
edge when it uses (1) a planar node edge associated with the
particular congestion edge, or (2) a non-planar node edge that the
router has associated with the particular congestion edge for the
route's or path's use of the non-planar node edge.
Even though the embodiments described below define global routes by
reference to the node edges, one of ordinary skill will realize
that other embodiments might define a global route differently. For
instance, some embodiments might define a global route in terms of
the congestion edges.
II. Overall Flow of Router
FIG. 25 illustrates a process 2500 that conceptually represents the
overall flow of the router in some embodiments of the invention. As
shown in this figure, the process 2500 initially uses (at 2505) the
congestion and length grids 100 and 200 to partition the IC layout
region into numerous Gcells, with four nodes on each routing layer
in each Gcell. As described above, these Gcells and nodes define a
routing graph in which the router defines and embeds routes.
Next, the process computes (at 2510) the capacities of congestion
edges between adjacent Gcells. These edges were described above by
reference to FIG. 8. The capacity of a congestion edge is typically
determined by a variety of factors, such as the size of the
sub-regions, the pitch (width and spacing) of the wiring tracks
represented by the edge, and the obstructions near edge.
FIGS. 26A and 26B present two examples that illustrate how the
process 2500 computes the capacity of a congestion edge in some
embodiments. In the description of these examples, "pitch" refers
to the sum of the default wire width and spacing for a given layer,
projected in the wiring direction for that layer onto a Gcell
boundary that it crosses. For a .+-.45-degree wire, this projection
increases width and spacing by a factor of {square root over (2)}
compared to their ordinary values.
To compute the capacity of a congestion edge that crosses a Gcell
boundary on a given layer, the process 2500 (1) defines a
parallelogram about the Gcell boundary, (2) identifies potential
obstacles in the parallelogram, (3) identifies the intersection of
the projection in the layer's wiring direction of the identified
obstacle with the boundary, (4) specifies any identified
intersection as a blocked portion of the boundary, and (5) derives
the congestion-edge capacity from the unblocked portion of the
boundary.
In some embodiments, the process identifies a parallelogram about a
Gcell boundary in the following manner. It identifies a first pair
of parallel sides of the parallelogram by translating the Gcell
boundary onto the midpoint of each of the two Gcells in the
direction of the layer's wiring direction. These two sides will be
parallel to the boundary between the Gcells and will traverse
through the Gcell midpoints. The second pair of the parallelogram's
parallel sides are in the layer's wiring direction and connect to
the parallelogram's first pair of sides (i.e., each side in the
second pair terminates at one end of each side of the first
pair).
FIG. 26A illustrates a parallelogram 2615 that is defined for a
congestion edge 2632 that crosses a Gcell boundary 2630 on layer 4,
while FIG. 26B illustrates a parallelogram 2665 that is defined for
a congestion edge 2634 that crosses a Gcell boundary 2680 on layer
3. The boundary 2630 is between Gcells 2605 and 2610, while the
boundary 2680 is between Gcells 2655 and 2660. The diagonal
congestion edge 2632 is associated with one 45.degree. node edge
that crosses the boundary 2630 on layer 4, while the horizontal
congestion edge is associated with two horizontal node edges that
cross the boundary 2680 on layer 3.
In FIG. 26A, the wiring direction on layer 4 is the 45.degree.
diagonal direction. Accordingly, the boundary 2630 is translated
onto the center of the Gcells 2605 and 2610 in the 45.degree.
diagonal direction. This translation defines two parallel vertical
sides 2620 and 2625 of the parallelogram 2615. These two sides are
parallel to the boundary 2630 and respectively run through the
center of Gcells 2605 and 2610. The other two sides of the
parallelogram are sides 2635 and 2640, which are in the layer's
wiring direction (which is the 45.degree. direction) and connect to
sides 2620 and 2625.
In FIG. 26B, the wiring direction is horizontal. Accordingly, the
boundary 2680 is translated onto the center of the Gcells 2655 and
2660 in the horizontal direction. This translation defined two
parallel vertical sides 2670 and 2675 of the parallelogram 2665.
These two sides are parallel to the boundary 2680 and respectively
run through the center of Gcells 2655 and 2660. The other two sides
of the parallelogram 2665 are sides 2685 and 2690, which are in the
layer's wiring direction (which is the horizontal direction) and
connect to the sides 2670 and 2675.
After identifying the parallelogram about a congestion-edge's Gcell
boundary, the process then identifies each potential obstacle
(e.g., each piece of pin, obstruction, or pre-route metal) that
falls in the parallelogram. For each potential obstacle identified
in the parallelogram, the process then identifies the portion of
the boundary that the obstacle would intersect if the obstacle were
moved across the boundary in the layer's wiring direction. For
instance, FIG. 26A illustrates a pin 2642 on layer 4 that falls
within the parallelogram 2615. As shown in this figure, this pin
would intersect portion 2644 of the boundary if it were moved
across the boundary 2630 in the 45.degree. direction. FIG. 26B
illustrates a pin 2692 on layer 3 that falls within the
parallelogram 2665. As shown in this figure, the pin 2692 would
intersect portion 2694 of the boundary 2680 if it were moved across
this boundary in the horizontal direction.
The process treats all identified intersected portions of the
boundary as blocked segments of the boundary. The process then
estimates the capacity of a congestion edge to be the total length
(T.sub.U) of all unblocked intervals on the congestion edge's
boundary that are at least one pitch long, divided by pitch (P),
i.e., the capacity of the congestion edge equals
##EQU00001##
Some embodiments might not treat each piece of pin, obstruction, or
pre-route metal as a blockage on the interval of boundary onto
which it translates in the routing direction. Also, some
embodiments might differently define the region to examine near a
boundary crossed by a congestion edge. For instance, some
embodiments might define different parallelograms on the diagonal
layers. Instead of the parallelogram 2615 in FIG. 26A, some
embodiments might define a parallelogram 2652 illustrated in FIG.
26C. This parallelogram 2652 has the Gcell centers and the Gcell
boundary endpoints as its four vertices.
After 2510, the process computes (at 2515) the via capacity between
each two adjacent layers in each Gcell. In a given Gcell, the via
capacity between two adjacent layers is computed as a
user-adjustable constant times the maximum of all capacities of
planar congestion edges into the Gcell on either of the layers. The
constant is typically less than 2. In some embodiments, it is
1.7.
After 2515, the process then identifies (at 2518) a set of
potential Steiner points for each net that it is routing. Steiner
points for a net can be found by (1) representing each pin of the
net as a unique (x,y) position given by the centroid of its pin
geometry, (2) assigning an edge cost between any two points in the
plane equal to the octilinear distance between them, and (3)
invoking a procedure given in "A fast and simple Steiner routing
heuristic", by Manjit Borah, Robert Owens, and Mary Jane Irwin,
Discrete Applied Mathematics 90 (1999), pp. 51 67. One manner of
computing the octilinear distance between two points is described
in U.S. patent application Ser. No. 10/174,662, entitled "Method
and Apparatus for Estimating Distances in a Region," and filed on
Jun. 19, 1902. The U.S. patent application Ser. No. 10/174,662 is
incorporated herein by reference. One skilled in the art will
recognize that a variety of other heuristics may be used to
generate Steiner points. Also, the Steiner set for a net might be
an empty set in certain situations.
Next, for each net that it is being routed, the process identifies
(at 2520) a congestion-unaware route that does not account for via
congestion within the Gcells or wire congestion at Gcell
boundaries. The generation of a congestion-unaware route for a net
will be further described below in Section III.
After 2520, the process performs two nested loops. The inner loop
identifies one set of routes for each net being routed, while the
outer loop causes the inner loop to run several (e.g., 8) times to
generate several (e.g., 8) sets of routes. The generated sets of
routes typically differ. These sets often differ because, in the
embodiments described below, the inner loop uses a route-generation
process that employs a costing function that accounts for resources
used by the routes previously identified by the inner loop. The
outer loop runs from 2525 to 2545, while the inner loop runs from
2530 to 2540.
At 2525, the process sorts the nets. In some embodiments, the first
time the process reaches 2525 it sorts the nets in an ascending
order of the lengths of their congestion-unaware routes, which were
identified at 2520. The process then selects (at 2530) a net
according to the order specified at 2525. It then identifies (at
2535) a route for the selected net. To identify this route, the
process typically uses a route generation process that employs a
costing function that accounts for resources used by the routes
previously identified at 2535. No previously identified route
exists for the first net in the first pass of the process 2500
through 2535. However, one or more such routes exist in every
subsequent pass through 2535. The route identification at 2535 will
be further described below in Section III. As mentioned above, the
process 2500 typically uses a route generation process at 2535 to
identify a route for a net. However, in some cases, the process
might not identify a new route at 2535 for a net, but rather might
identify a previous route (e.g., the most recent route) that it
previously identified for the net.
After identifying a route for the selected net, the process
determines (at 2540) whether it has generated a route for all the
nets in the current pass through 2525 2545 (i.e., whether the
selected net is the last net in the order specified in the last
pass through 2525). If not, the process selects (at 2530) the next
net in the order specified in the last pass through 2525,
identifies (at 2535) a route for this net, and then determines (at
2540) whether this net is the last net in the order specified in
the last pass through 2525.
Once the process determines (at 2540) that it has generated a route
for all the nets in its current pass through 2525 2545, the process
determines (at 2545) whether it has generated the desired number
(S) of route sets. If not, the process returns to 2525 to initiate
another pass through the outer loop (i.e., through 2525 to 2545) so
that it can generate another set of routes. For this pass through,
the process can specify (at 2525) the same net order as, or a
different net order than, the previous pass through the outer loop.
Some embodiments specify a different net order for each pass
through the outer loop in an attempt to increase the differences
between the sets of generated routes.
When the process determines (at 2545) that it has generated the
desired number of route sets, the process then identifies (at 2550)
one set of routes from all the generated routes. Different
embodiments use different techniques to select (at 2550) one
combination of routes from the set of identified routes. One
suitable technique is randomized rounding, which is described in
Randomized Algorithm, by Rajeev Motwani and Prabhakar Raghavan,
Cambridge University Press (1995, 1997).
Several other suitable techniques are described in United States
Patent Application entitled "Method and Apparatus for Solving an
Optimization Problem," filed concurrently with the present
application, and filed with Express Mail Number EV169571637US. This
application is incorporated herein by reference. One technique
described in this incorporated application identifies one set of
routes by first specifying a set that has one identified route for
each net. It then iteratively examines all the nets. During the
examination of each particular net, the process iteratively
examines all the identified routes for the particular net. During
the examination of each particular route for each particular net,
the process replaces the current route for the particular net in
the solution set with the particular route if the replacement would
improve the solution set. Under this approach, the set that remains
after all the identified routes of all the nets have been examined
is the set identified at 2550.
After 2550, the process ends.
III. Route Generation
FIG. 27 illustrates a route-generation process 2700 that the
routing process 2500 can use (at 2535) to generate a route for a
particular net in some embodiments. The process 2700 starts (at
2705) by initializing a variable, Route.sub.13 Length, to zero. The
process uses this variable to specify the length of the route that
it tries to construct for the net.
The process then identifies (at 2710) the nodes (i.e., the
length-grid sub-regions on each layer) that contain the particular
net's set of pins and Steiner points. These nodes will be referred
to as the configuration nodes of the particular net. After
identifying the configuration nodes once for a net, some
embodiments store the configuration nodes for the net, so that they
can be retrieved the next time that they are needed. In some cases,
a pin or a Steiner point can be in more than one length-grid
sub-region (i.e., more than one node). Hence, each pin or Steiner
point is associated with a set of nodes. Also, in some embodiments,
each Steiner point is specified only by an x- and y-coordinate.
Hence, it can be on any layer in the routing graph. Accordingly, in
some embodiments, the node on each layer that includes the x- and
y-coordinates of a net's Steiner point is added to the net's
configuration nodes.
After identifying the configuration nodes for the particular net,
the process specifies (at 2715) source and target node sets for a
first path search. In some embodiments, the process specifies the
target set as a node set that is associated with a particular pin
of the net. It then specifies the nodes of all other pins and
Steiner points in the net's configuration that are within a certain
distance of the target set as source nodes. In some embodiments,
this distance is a certain percentage greater than the distance
between the target set and the node in the net's configuration
closest to the target set.
On layers 4 and 5, the net pins might be in nodes that do not have
planar edges running through them. However, such nodes are target
and source nodes that need to be expanded to and from during a path
search. It would be inefficient to reach these nodes only through
non-planar edges. Accordingly, to address this situation, some
embodiments specify one or more nodes that are adjacent to such
nodes on the same layer as "shadow nodes." A shadow node of a
particular node in effect augments the representation of the
particular node's pin in a path search. A particular node's shadow
is a source node when the particular node is a source node, and is
a target node when the particular node is a target node. In other
words, a path can expand from a particular node's shadow node when
the particular node serves as a source node. When the particular
node is a target of a path search, an expansion to the particular
node's shadow node is treated as an expansion to the target
node.
FIG. 28 presents one example of shadow nodes. This figure
illustrates a pin 2805 in a node 2810 on layer 4. Layer 4 has
45.degree. node edges that connect the northwest and southeast
nodes on this layer. Node 2810, however, is a northeast node that
does not have a planar node edge running through it. This node
could be a target or source node. However, it would be difficult to
reach this node since it has no incident planar node edge.
Consequently, to address this situation, some embodiments specify
node 2815 and/or node 2820 as shadow nodes of node 2805. As shadow
nodes, node 2815 and 2820 can be treated as source nodes of a path
search when node 2810 is a source node, and they can be treated as
target nodes of a path search when node 2810 is a target node.
Some embodiments would specify both node 2815 and node 2820 as
shadow nodes of node 2810. Other embodiments would specify only one
of these two nodes as a shadow node. For instance, some of these
embodiments would specify node 2815 as the shadow node since pin
2805 is closer to the node edge 2825 running through node 2815 than
the node edge 2830 running through node 2820. Other embodiments
might take this approach (i.e., might expand only from the shadow
node that is closest to the actual pin) only when one or more node
edges connected to the shadow node is not blocked (e.g., by an
obstacle). When a node edge connecting to the shadow node that is
closest to the actual pin is blocked, some of these embodiments
might select the other adjacent node as an additional shadow
node.
After specifying (at 2715) the source and target sets for a path
search, the process directs (at 2720) a path-generation process to
identify and embed the lowest-cost path between the specified
source and target sets. If the path-search process embeds the
lowest-cost path, the path-generation process increments the
Route_Length by the length of the embedded path. The
path-generation process is further described below by reference to
FIG. 29.
At 2725, the route-generation process determines whether the
path-generation process was able to identify and embed a path
between the specified source and target sets. If not, the process
2700 has failed to find a route for the net. Accordingly, it
returns (at 2730) a notification specifying its failure and then
ends.
The router's response to this notification was not illustrated in
FIG. 25, in order not to obscure the description of the router's
flow with unnecessary details. However, it should be noted that the
router responds differently to this notification in different
embodiments. For instance, in some embodiments, the router can
remove from the routing problem a net that the process 2700 fails
to route. In other embodiments, the router removes the net only if
it repeatedly fails to find a route for the net after re-adjusting
the net order and trying to find a complete routing solution.
If the process determines (at 2725) that the path-generation
process identified and embedded a path, it determines (at 2735)
whether it has routed all the pins of the net. If so, the process
2700 notifies (at 2740) the process 2700 that it has embedded a
route for the net and provides this route and its associated
Route_Length.
If the process 2700 determines (at 2735) that it has not routed all
the pins of the net, the process specifies (at 2745) new source and
target sets for another path search. In some embodiments, the
process specifies (at 2745) as the target node set (1) all the
nodes that are associated with the routed pins and Steiner points,
and (2) all nodes that are currently on the one or more paths that
the path-generation process has embedded for the net during the
current route generation. In some embodiments, the process
specifies (at 2745) as the source node set all nodes associated
with any unrouted pin and Steiner point in the net's configuration
that are within a certain distance of the target set. In some
embodiments, this distance is a certain percentage greater than the
distance between the target set and a node in the net's
configuration that is closest to the target set and that is
associated with a pin or Steiner that has not yet been routed.
After specifying the source and target sets at 2745, the process
2700 returns to 2720 to direct the path-generation process to
identify and embed the lowest-cost path between the specified
source and target sets. The operation of the process 2700 from 2720
was described above.
A. Path Generation.
At 2720, the route-generation process 2700 calls a path-generation
process to identify and embed a path between source and target node
sets in the routing graph. In some embodiments, the router uses an
A* path-generation process 2900 that is illustrated in FIG. 29.
This process has two phases: (1) a path exploration phase, during
which the process identifies a path between the specified source
and target node sets, and (2) a path-embedding phase, during which
the process embeds the identified path.
The process 2900 is an iterative best-first search that at each
iteration tries to extend a partial solution with the best
estimated cost. Specifically, during its path exploration phase,
the process 2900 starts its path search by specifying the start of
one or more paths from one or more source nodes. It then
iteratively identifies one or more path expansions about the lowest
cost path, until it identifies a path that connects a source node
and a target node. Each identified expansion about a path is from a
"current node" (also called "start node") reached by the path being
extended to a "destination node" that neighbors the current
node.
For each expansion, the process computes an {circumflex over (F)}
cost, which is the estimated cost of the path from a source node
through the expansion's destination node to a target node. This
cost can be expressed as: {circumflex over (F)}=G+H. (1) In this
equation, G represents the cost of the path that has reached the
expansion's destination node, while H represents an estimated cost
of a path from the expansion's destination node to the set of
target nodes. In the embodiments described below, the H cost
expresses the lower-bound estimate of the shortest path from the
expansion's destination node to the target set. Accordingly, in
these embodiments, the {circumflex over (F)} cost expresses the
estimated cost of a lowest-cost path from a source node through the
expansion's destination node to a target node. Also, in these
embodiments, the G and hence the {circumflex over (F)} account for
several different types of costs, such as a wirelength, wire
congestion, and via congestion. Each of these costs is further
described below.
As shown in FIG. 29, the process 2900 initially (at 2905)
identifies and sets the H of each source node that the process 2700
specified for the current path search. Each node's H expresses the
estimated distance between the node and the target set in the
current path search. During each search, the process 2900 stores
the H cost for each node after computing this cost, so that it only
has to compute it once for each node reached in each search.
Different embodiments compute a node's H differently. Some
embodiments use a rectilinear bounding box technique that is used
in conventional A* path searches. Other embodiments, however, use
the novel techniques described in the above-incorporated U.S.
patent application Ser. No. 10/174,662. One technique described in
this application identifies two bounding boxes that each enclose
the target set. One bounding box has sides that are parallel to one
of the layout's coordinate axes. The other bounding has sides that
are rotated by 45.degree. with respect to the layout's coordinate
axes. This technique then identifies the distance between the node
and each of the two bounding boxes. It then identifies the node's H
as the longer of the two identified distances.
For each source node, the process 2900 also specifies (at 2905) a
"drop," which is path identifier that represents a path expansion.
Specifically, a drop represents an expansion from a start node to a
destination node by referring to the destination node as its node
and referring back to the drop of the start node. Drops allow the
process 2900 to keep track of the paths that it explores. For each
drop, the process also stores (1) a G cost, which is the cost of a
path from a source node to the drop's node through the sequence of
expansions that led to the drop, and (2) an {circumflex over (F)}
cost, which is the drop's G cost plus the H cost of the drop's node
(i.e., the H cost of the destination node of the expansion for
which the drop was specified). One of ordinary skill will realize
that other embodiments might not use drops or might implement drops
differently.
At 2905, a drop that is defined for a source node refers to the
source node as its node and defines the drop's prior drop as null.
The process sets the G cost of each drop defined at 2905 to zero,
and sets the drop's {circumflex over (F)} cost equal to H cost of
the drop's node. At 2905, the process stores the specified drops in
a storage structure, which, in some embodiments, is a priority
queue (e.g., a heap) that is ordered based on the {circumflex over
(F)} costs of the drops.
Next, at 2910, the process retrieves from the priority queue a drop
with the smallest {circumflex over (F)} cost, and specifies this
drop as the Current_Drop. The process then "closes" (at 2915) the
drop's node. A closed node is a node to which the process can no
longer expand during the path search. Consequently, the closing of
node at 2915 prevents the process 2900 from expanding to this node
during the current path search.
The process then determines (at 2920) whether the Current_Drop's
node is a node in the target set for the current path search. If
not, the process performs a series of operations in a loop from
2930 to 2965, in order to explore all possible expansions about the
Current_Drop. Specifically, at 2930, the process identify one of
the possible expansions about the Current_Drop. Table 1 below lists
all the possible expansions from the Current_Drop's node for a
wiring model that allows routing only on layers 2 5.
TABLE-US-00001 TABLE 1 Drop's Layer Planar Expansion Non-Planar
Expansions 2.sup.nd Layer If drop's node is not on the north or
south Expansion to the node directly above boundary of the layout,
two planar the drop's node. expansions are possible to the two
nodes that are adjacent to the drop's node in the .+-.90.degree.
directions. If the drop's node is on the south or north layout
boundary, then one planar expansion is available to the one node
adjacent to the drop's node in the +90.degree. or -90.degree.
direction. 3.sup.rd Layer If drop's node is not on the east or west
Expansion to nodes directly above and boundary of the layout, two
planar below the drop's node. expansions are possible to the two
nodes that are adjacent to the drop's node in the 0.degree. and
180.degree. directions. If the drop's node is on the east or west
boundary of the layout, then one planar expansion is available to
the one node adjacent to the drop's node in the +180.degree. or
0.degree. direction. 4.sup.th Layer If drop's nose is not on
periphery of the Expansion to nodes directly above and layout and
it is either the northwest or below the drop's node. southeast node
of a Gcell, two planar Also, two internal zig expansions,
expansions are possible to the two nodes where each expansion is to
a node that that are adjacent to the drop's node in the is in layer
5 in the same Gcell as the +45.degree. and -135.degree. directions.
If the drop's drop's node. node is on the periphery of the layout
and Up to two external zig expansions, it is either the northwest
or southeast node where each such expansion is to a of a Gcell,
then zero planar expansion is node that is in layer 5 in another
Gcell possible or one planar expansion is which is adjacent to the
Gcell available to the one node adjacent to the containing the
drop's node. drop's node in the +45.degree. or -135.degree.
direction. There are no planar expansions from a drop's node if
this node is the northeast or southwest node of a Gcell. 5.sup.th
Layer If drop's node is not on periphery of the Expansion to nodes
directly above and layout and it is either the southwest or below
the drop's node. northeast node of a Gcell, two planar Also, two
internal zig expansions, expansions are possible to the two nodes
where each expansion is to a node that that are adjacent to the
drop's node in the is in layer 4 in the same Gcell as the
-45.degree. and +135.degree. directions. If the drop's drop's node.
node is on the periphery of the layout and Up to two external zig
expansions, it is either the southwest or northeast node where each
such expansion is to a of a Gcell, then zero planar expansion is
node that is in layer 4 in another Gcell possible or one planar
expansion is which is adjacent to the Gcell available to the one
node adjacent to the containing the drop's node. drop's node in the
-45.degree. or +135.degree. direction. There are no planar
expansions from a drop node if this node is the southeast or
northwest node of a Gcell.
In some embodiments that use a wiring model that allows routing on
layer 1, the expansion possibilities on layer 1 are similar to the
expansion possibilities on layer 3, except that there are no
non-planar expansions to a layer below. Also, in these embodiments,
the process can expand from a node on layer 2 to a node directly
below on layer 1.
After selecting an expansion at 2930, the process determines (at
2935) whether the destination node of the expansion is a closed
node. If so, the process transitions to 2965, which is further
described below. Otherwise, the process computes (at 2940) a G cost
for the expansion. The computation of this cost is described
further below.
After 2940, the process determines (at 2945) whether the
destination node of the expansion specified at 2930 has been
previously reached in the current path search. If not, the process
(at 2960) computes and stores the destination node's H cost. The
computation of this cost was described above at 2905. At 2960, the
process also specifies a drop for the expansion specified at 2930.
The process associates the specified drop with the expansion's
destination node, and sets the drop's previous drop to the
Current_Drop. The process also (1) sets this specified drop's G
cost to the G cost computed at 2940 for the expansion, and (2) sets
the specified drop's {circumflex over (F)} cost to the sum of the
drop's G cost and the H cost of the drop's node (i.e., the
expansion's destination node). The process then stores (at 2960)
the drop specified at 2960 in the priority queue based on its
{circumflex over (F)} cost. From 2960, the process transitions to
2965, which will be described below.
If the process determines (at 2945) that the specified expansion's
destination node has been previously reached in the current path
search, the process determines (at 2950) whether the identified
expansion's G cost (computed at 2940) is less than the G cost of
the drop in the priority queue that is associated with the
expansion's destination node. If not, the expansion specified at
2930 is not the cheapest expansion to its destination node. Hence,
in this situation, the process stops its examination of the
expansion identified at 2930, and transitions to 2965, which is
further described below.
On the other hand, if the process determines (at 2950) that the
identified expansion's G cost (computed at 2940) is less than the G
cost of the drop in the priority queue that is associated with the
expansion's destination node, the process removes the drop
associated with the destination node from the priority queue, and
specifies a new drop for this node. The process associates the new
drop with the identified expansion's destination node, and sets the
drop's previous drop to the Current_Drop. The process also (1) sets
this newly specified drop's G cost equal to the identified
expansion's G cost (computed at 2940) for the expansion, and (2)
sets the specified drop's {circumflex over (F)} cost to the sum of
the drop's G cost and the H cost of the drop's node (i.e., the H
cost of the expansion's destination node). The process then stores
(at 2955) the newly specified drop in the priority queue based on
its {circumflex over (F)} cost. From 2955, the process transitions
to 2965.
At 2965, the process determines whether there is any expansion
about the Current_Drop's node that it has not yet examined. If so,
the process transitions back to 2930 to identify another expansion,
and then performs the subsequent operations to determine whether to
specify a drop for this newly identified expansion.
When the process determines (at 2965) that it has examined all
expansions about the Current_Drop's node, the process determines
(at 2970) whether the priority queue that stores the drops is
empty. If so, the process has failed to find a path between the
specified source and target sets. Accordingly, it returns (at 2975)
a notification specifying its failure and then ends. On the other
hand, when the process determines (at 2970) that the priority queue
is not empty, the process transitions back to 2910 to retrieve the
drop with the smallest {circumflex over (F)} cost from the priority
queue and then to perform the above-described operations for this
drop.
The process has found a path between the source and target sets
when it determines (at 2920) that the Current_Drop's node is a
target. In this situation, the process transitions from 2920 to
2925. At 2925, the process also embeds the identified path between
the source and target sets. Starting at the Current_Drop on the
target, the embedding "back traces" the sequence of drops that
reached the target and generates an ordered list of (1) nodes
associated with the drops and (2) node edges between these
nodes.
FIG. 30 illustrates an example of a back trace operation. In this
example, the path search has identified a path between a source
node 3005 and a target node 3010. This path has traversed through
layers 3 5. To identify this path, the path search has identified a
series of drops 3015a 3015h. With the exception of the first
source-node drop 3015a that has a null back reference, each drop
has a reference to a previous drop in the path. The back trace
would start at the drop on the target and follow each drop's back
reference to identify all of the path's drops, the nodes associated
with these drops, and the edges between the nodes of successive
drops. In this manner, the back trace would identify an ordered
list of nodes 3020 between the source and target nodes 3005 and
3010, and an ordered list of edges 3025a 3025g between these
nodes.
Some embodiments then define the global route path by reference to
the ordered list of node edges produced through the back trace. In
the example illustrated in FIG. 30, this ordered list would include
edges 3025a 3025g. Other embodiments would identify the global
route path by reference to the ordered list(s) of nodes and node
edges identified in the back trace. In the example illustrated in
FIG. 30, this ordered list(s) would include edges 3025a 3025g and
node 3005, nodes in the set 30020, and node 3010.
At 2925, the process 2900 increments the Route_Length by the length
of the identified global route path. This length is simply the sum
of the length of the node edges identified through the back trace,
where the length of a planar horizontal or vertical node edge is L,
the length of a diagonal node edge is L* {square root over (2)},
the length of a non-planar nodes edge between overlapping nodes is
X*L, and the length of a non-planar edge between non-overlapping
nodes is (X+ {square root over (2)})*L.
At 2925, the process also determines if the source node that it
reached through its back trace at 2925, includes one or more pins
that are marked as unrouted. If the process identifies one or more
such pins at 2925, it then selects one of these pins and marks it
as routed. When there are no such pins in the source node reached
through the back trace, the source node contains at least one
Steiner point that is marked unrouted. Hence, when the source node
does not contain an unrouted pin, the process selects (at 2925) a
previously unrouted Steiner point and marks it as routed.
In some cases, the source and target node sets partially or
completely overlap. In such cases, the path search transitions to
2925 the first time it reaches 2920, and hence it will not identify
any expansions. At 2925, the back trace then simply identifies a
previously unrouted pin or Steiner in a node that is in both the
source and target node sets as a routed pin or Steiner. In other
words, this back trace results in an empty set of global-route node
edges as a pin or Steiner is reached without requiring any node
edges. In this situation, some embodiments define a special
"node-internal" edge between a previously unrouted "point" and a
newly routed "point" in the source/target node, where a point in
this case can be a pin or a Steiner point. Some of these
embodiments use such an edge purely for internal bookkeeping, while
others augment the notion of the global route to include this
node-internal edge. When all of a net's pins are in the same node,
the router only identifies node-internal edges. In such a
situation, the resulting global route can be specified as either
null (e.g., an empty set of node edges), or as a collection of
node-internal edges.
One of ordinary skill will realize that the path-generation process
might be implemented differently in other embodiments. For
instance, in some embodiments, the H cost might not specify a lower
bound on the shortest path between a drop's node and a target set.
In addition, some embodiments might compute the {circumflex over
(F)} cost slightly differently. For instance, some embodiments
might express the {circumflex over (F)} cost as: {circumflex over
(F)}=G+2*H. Such a cost would bias the search process to expand
about the drops that are closer to the target set. Alternative
embodiments might express the {circumflex over (F)} cost as:
{circumflex over (F)}=G+H+ . where represents the estimated
computational effort needed to complete the path from the current
drop. The embodiments that use alternative {circumflex over (F)}
cost might not satisfy the admissibility requirement. Also, instead
of an A* search, other embodiments might perform other types of
path searches.
B. Costing an Expansion
As described above, the path-generation process 2900 computes the G
cost of an expansion at 2940. The embodiments described below use a
cost function with several exponential components that depend on
wirelength, wire-congestion, and via-congestion costs. In costing
an expansion, the congestion components account for all the routes
that the router has identified at 2535 before the current path
search on the edges being considered. In this manner, these
components bias the path search to spread the routes to favor
evenly distributed congestion profiles over those with sharp peaks.
Even though exponential cost terms are described below, one of
ordinary skill will realize that other embodiments might use other
types of costing functions to evaluate the routes.
1. General Exponential Costing Expression
For some embodiments, Equation (A) below provides a cost function
that represents the G cost of an expansion to a destination node
d.
.function..times..times..times..times..function..function..function..func-
tion..times..times..function..function..function..function..times..times..-
times..times..times..function..function..times..times..function..function.-
.times..times..function..function..times..times..function..function.
##EQU00002## In this equation, the first exponential component
represents a wirelength cost, the second exponential component
represents a wire congestion cost, and the third exponential
component represents a via congestion cost. Table 2 provides a
definition for the variables in these components.
TABLE-US-00002 TABLE 2 Term Definition e The base of the natural
logarithm. .epsilon..sub.L, .epsilon..sub.C, .epsilon..sub.V
User-adjustable exponential-multiplier parameters. Y.sub.L,
Y.sub.j, and Y.sub.t Normalizing variables. {circumflex over
(F)}.sub.L (d) The estimated length of the path from a source node
through the expansion's destination node d to a target node. This
estimated length equals the length of the path that has reached the
expansion's destination node d, plus the destination node's H.
H.sub.MIN The minimum H of the set of sources of the current path
search. j One of m congestion edges that are used by the path that
has reached the expansion's destination node d. If the path has not
used any congestion edge, then m equals 0 and the wire congestion
component of Equation (A) is zero. old usage (j) The cumulative
number of times that all the routes previously identified at 2535
use the congestion edge j. In some embodiments, the router computes
and updates the old usage (j) value after each iteration of 2535 of
the process 2500. new usage (j) The cumulative number of times that
the congestion edge j is used by (1) all the routes previously
identified at 2535, and (2) the path that has reached the
expansion's destination node d. New usage (j) equals old usage (j)
plus 1. capacity (j) The estimated number of available tracks of
the congestion edge j. In some embodiments, this capacity is a
value from 0 to 16. This number was computed at 2510 of the process
2500. goal(layer (j)) A target upper bound on the congestion ratio
on the layer that contains edge j. t One of K non-planar edges that
are on the path that has reached the expansion's destination node
d. If the path has not used any non-planar edge, then t equals 0
and the via congestion component of Equation (A) is zero. old usage
(t) In all the routes previously identified at 2535, the number of
non-planar edges that via in the same Gcell as edge t between the
same two layers as edge t. With the exception of external zigs, the
Gcell that contains the via represented by edge t is the Gcell that
contains the two nodes connected by edge t. If edge t is an
external zig, the Gcell of the via associated with the external zig
edge t is the Gcell that results in the smaller aggregate via and
wire congestion costs for this instance of use of the external zig
t, as described in Section I.B.3. After each iteration of 2535 of
the process 2500, the router in some embodiments computes and
updates the via usage values for each pair of adjacent routing
layers in each Gcell. new usage (t) In all the routes previously
identified at 2535, and in the path that has reached the
expansion's destination node d, the number of non-planar edges that
via in the same Gcell as edge t between the same two layers as edge
t. See discussion in the definition of old usage (t) regarding the
Gcell that contains edge t's via. New usage (t) equals old usage
(t) plus 1. capacity (t) The estimated number of vias that can
traverse the same two layers as edge t in this edge's Gcell. In
some embodiments, this capacity is a value from 0 to 27. This
capacity was computed at 2515 of the process 2500. goal(layer pairs
(t)) A target upper bound on the via congestion ratio between the
two adjacent layers traversed by the non-planar edge t.
Each of the three components in Equation (A) includes an
exponential expression. The exponential expressions are normalized
to the same scale by multiplying them by the normalizing factors
Y.sub.L, Y.sub.j, and Y.sub.t. In some embodiments, the multiplier
Y.sub.L is expressed by the following equation:
.times..times..function. ##EQU00003## where (1) Y.sub.LI is a
constant, (2) N is one of the R routes identified thus far at 2535,
(3) length (N) is the length of the route N, and (4) T.E.L stands
for total estimated length and equals the sum of the estimated
length of each net's route. In some embodiments, the total
estimated length is the sum of the lengths of the
congestion-unaware routes (identified at 2520) of all nets; in
other embodiments, it is the sum of a lower_bound on the route
lengths of all the nets (e.g., it is the sum of the bounding box of
each net).
In some embodiments, Y.sub.LI equals 1, while it equals another
value
.times..times. ##EQU00004## in other embodiments. The multiplier
Y.sub.L is a value that is re-computed after the identification of
each route at 2535. Hence, each time that the router is identifying
(at 2535) a route for a net, the multiplier Y.sub.L is based on all
the routes that the router has identified before this iteration of
2535.
The multiplier Y.sub.j is also different in different embodiments.
For instance, in some embodiments, this multiplier equals 1 or some
other constant. Some embodiments might use different constants for
different edges. In other embodiments, this multiplier equals
.function. ##EQU00005## where goal(layer(j)) and capacity(j) are
defined in Table 2 above. In still other embodiments, this
multiplier is represented by the following equation:
##EQU00006## where {overscore (C)}.sub.L is the average
initial-capacity constant on each layer and is represented by:
.times..times..times..times..times..times..times..times..times..function.-
.times..times..times..times..times..times..times..times..times..times.
##EQU00007## Specifying the multiplier Y.sub.j based on the average
initial-capacity cost {overscore (C)}.sub.L centers the initial
capacity costs of the edges about 1.
The multiplier Y.sub.t is also different in different embodiments.
For instance, in some embodiments, this multiplier equals to 1 or
some other constant. Some embodiments might use different constants
for different non-planar edges. In other embodiments, this
multiplier equals
.times..times..function. ##EQU00008## where goal(layer pairs(t))
and capacity(t) are defined in Table 2 above. In still other
embodiments, this multiplier is represented by the following
equation:
##EQU00009## where {overscore (C)}.sub.LP is the average
initial-capacity constant for each layer pair and is represented
by:
.times..times..times..times..times..times..times..times..times..times..ti-
mes..times..times..times..times..function..times..times..times..times..tim-
es..times..times..times..times..times..times..times. ##EQU00010##
Specifying the multiplier Y.sub.t based on the average
initial-capacity constant {overscore (C)}.sub.LP centers the
initial capacity costs of the non-planar edges about 1. One of
ordinary skill will realize that other embodiments might specify
their normalizing constants differently.
In all three components of Equation (A), the base of the
exponential expression is the natural-logarithm base e. Other
embodiments, however, might use a different base. In addition,
other embodiments might formulate differently the exponent of each
exponential expression in Equation (A). In some embodiments, the
exponential multipliers .epsilon..sub.L, .epsilon..sub.C,
.epsilon..sub.V are real numbers between 2 to 16. For instance, in
some embodiments, all three multipliers equal 9, even though these
multipliers do not need to be the same value. As mentioned above,
each of these multipliers is adjustable by the user in some
embodiments.
Each route or path includes a set of node edges, which can be
planar or non-planar. The cost of each planar and non-planar node
edge was described above in Section I. Table 3 reiterates each of
these costs for a route or a path, and describes how each of these
costs is factored in each of the components of Equation (A).
TABLE-US-00003 TABLE 3 Wirelength Via Congestion Node Edge
Component Wire Congestion Component Component Planar Node
Increments If edge f goes from one Gcell No effect. Edge f on
length of route to another (i.e., crosses a Layers 2 and 3 or path
by unit Gcell boundary), then edge f length cost L. is associated
with a congestion edge j, and therefore a new usage (j) is defined
by incrementing old usage (j) by one. Otherwise, no effect. Planar
Node Increments Define new usage (j) by No effect. Edge f on length
of route incrementing old usage (j) by Layers 4 and 5 or path by
one, where node edge f is length cost associated with congestion L
* {square root over (2)}. edge j. Non-Planar Increments No effect.
Define new usage (t) by Node Edge t length of route incrementing
old usage (t) between directly or path by (associated with vias
overlapping length cost between layers a and b in nodes on layers
X*L, where X Gcell g) by one. a and b in Gcell is a via-scalar g.
factor. Internal Zig t Increments No effect. Define new usage (t)
by between non- length of route incrementing old usage (t)
overlapping or path by (associated with vias nodes on layers length
cost X*L between layers a and b in a and b in Gcell plus L *
{square root over (2)}. Gcell g) by one. g. External Zig t
Increments Use the approach described in Define new usage (t) by
between non- length of route Section I.B.3 to associate the
increment old usage (t) by overlapping or path by instance of the
external zig t's one, where old usage (t) is nodes on layers length
cost X*L use with a congestion edge j. the via usage between a and
b in plus L * {square root over (2)}. Define new usage (j) by
layers a and b in the Gcell adjacent Gcells incrementing old usage
(j) by that is assigned to contain g1 and g2. one. via for this
instance of edge t's use, per the approach described above in
Section I.B.3.
One of ordinary skill will realize that other embodiments might use
different exponential cost functions than the one illustrated in
Equation (A). For instance, some embodiments might use an equation
that has the same wire and via congestion components as Equation
(A), but the following wirelength component instead of Equation
(A)'s wirelength component.
.times..times.e.times..times..function..times..times. ##EQU00011##
In this equation, Length(d) is the length of the path p that has
reached the expansion's destination node d. Other embodiments might
use an equation that uses both this wirelength component and the
wirelength component of Equation (A).
2. Deriving Expansion Cost from the G Cost of the Expansion's Start
Node
Equation (A) provides a general expression of the costing function
that represents the G cost of an expansion in some embodiment.
However, in some embodiments, the process 2900 does not actually
use Equation (A) to compute the G cost of an expansion. Instead, it
derives this G cost from the G cost of the Current_Drop in the
following manner.
Assume that the Current_Drop specifies (i.e., is the last drop of)
a path p', while the expansion from the Current_Drop specifies a
current path p, which is an extension of the path p' to the
expansion's destination node. The Current_Drop's G cost,
G(Current_Drop), is the cost of the path p' that has reached the
Current_Drop.
The process 2900 first computes a G.sub.1 cost that is illustrated
in Equation (B) below.
.function.e.function.e.function.' ##EQU00012## In this equation,
{circumflex over (F)}.sub.L(p) equals the length of a path p plus
the destination node's H. It represents an estimated length of a
path from a source node through the expansion's destination node d
to a target node. It is equivalent to {circumflex over
(F)}.sub.L(d), which was described above. {circumflex over
(F)}.sub.L(p') equals the length of a path p' plus the H of the
expansion's start node. It represents an estimated length of a path
from a source node through the expansion's start node to a target
node. The remaining terms of Equation (B) are as described above
for Equation (A). The exponential expression
e.function.' ##EQU00013## represents the wirelength cost of path
p', while the exponential expression
e.function. ##EQU00014## represents the wirelength cost of path p.
Hence, Equation (B) illustrates that the G.sub.1 cost can be
obtained by adding the incremental wirelength cost for the
expansion to the G cost of the Current_Drop, since path p is an
extension of path p' by the current expansion.
The length of the path p can be obtained from the length of the
path p', as illustrated in Table 4 below.
TABLE-US-00004 TABLE 4 Expansion to Destination Node Length of Path
P Planar expansion on layer 2 or 3 Length of p' plus L, where L is
the unit length cost. Planar expansion on layer 4 or 5 Length of p'
plus L * {square root over (2)}. Non-planar expansion between
Length of p' plus X*L, where X overlapping nodes is a via scalar
factor. Internal or External Zigs Length of p' plus (X + {square
root over (2)}) * L.
The G cost of the expansion equals the G.sub.1 cost expressed in
Equation (B) if the expansion is a planar expansion that does not
cross a Gcell boundary. However, if the expansion is a planar
expansion along a node edge f that crosses a Gcell boundary, and
the node edge f is associated with a congestion edge j, then the
expansion's G cost is a G.sub.2 cost expressed in Equation (C).
e.times..times..times..times..function..times..times..function.e.times..t-
imes..times..times..function..times..times..function. ##EQU00015##
As illustrated in this equation, the G.sub.2 cost equals the
G.sub.1 cost expressed in Equation (B) plus an exponential wire
congestion cost for crossing the Gcell boundary. In Equation (C),
the terms are as defined above. The two exponential terms in
Equation (C) represent costs after and before the expansion. Hence,
Equation (C) illustrates that the G.sub.2 cost can be obtained by
adding the incremental wire congestion cost for the expansion to
the G.sub.1 cost.
If the expansion is along a non-planar edge t between two directly
overlapping nodes or is along an internal zig expansion t between
two non-overlapping nodes in a Gcell, the expansion's G cost is a
G.sub.3 cost expressed in Equation (D) below.
e.times..times..times..times..function..times..times..times..times..funct-
ion.e.times..times..times..times..function..times..times..times..times..fu-
nction. ##EQU00016## As illustrated in this equation, the G.sub.3
cost equals the G.sub.1 cost expressed in Equation (B) plus
exponential via congestion cost due to the via expansion. In
Equation (D), the terms are as defined above. The two exponential
terms in Equation (D) represent costs after and before the
expansion. Hence, Equation (D) illustrates that the G.sub.3 cost
can be obtained by adding the incremental via congestion cost for
the expansion to the G.sub.1 cost.
If the expansion is an external zig t that connects two
non-overlapping nodes in two adjacent Gcells, the expansion's G
cost is a G.sub.4 cost expressed in Equation (E) below.
.times.e.times..times..times..times..function..times..times..times..times-
.e.times..times..times..times..function..times..times..function..times.e.t-
imes..times..times..times..function..times..times..times..times..function.-
e.times..times..times..times..function..times..times..times..times..functi-
on. ##EQU00017## As illustrated in this equation, the G.sub.4 cost
equals the G.sub.1 cost expressed in Equation (B) plus exponential
via and wire congestion costs for the via expansion. In Equation
(E), the terms are as described above. The two positive exponential
terms represent costs after the expansion, while the two negative
exponential terms represent costs before the expansion. Hence,
Equation (E) illustrates that the G.sub.4 cost can be obtained by
adding the incremental wire and via congestion costs for the
expansion to the G.sub.1 cost.
To compute the incremental via and wire congestion costs, the path
search process needs to associate this instance of the external zig
t's use with a via location and congestion edge, pursuant to the
approach described in Section I.B.3. Specifically, the process
examines two different via locations and congestion edges for this
use of the external zig t, and associates the external zig with the
via location and edge crossing that results in the smaller
aggregate via and wire congestion costs. The process then uses the
incremental via and wire congestion costs of the associated via
location and edge crossing in Equation (E) to express the cost of
the path p.
For instance, assume that the external zig t is zig 1400 that was
described above by reference to FIGS. 14 and 22 24. Assume further
that for this instance of external zig t, the smaller aggregate via
and wire congestion cost can be obtained by placing the external
zig's via in Gcell 1410. Hence, for this use of the external zig,
the path search process associates this use of the external zig
1400 with the congestion edge 2310, and specifies the Gcell for the
external zig's via as the Gcell 1410. In this situation, the
incremental via congestion cost is based on the old and new usage
values for vias between layers 4 and 5 in Gcell 1410. The
incremental wire congestion cost is based on the old and new usage
values for the congestion edge 2310.
C. Generating a Congestion-Unaware Route for a Net
As described above, the process 2500 identifies (at 2520) the
congestion-unaware route for each net. To generate the
congestion-unaware route for a net, the process can use
route-generation and path-generation processes that are similar to
the above-described route-generation and path-generation processes
2700 and 2900, except for the costing of expansions at 2940. To
generate the congestion-unaware route for a net, some embodiments
cost the expansions at 2940 in a non-exponential manner that
disregards the via and wire congestion costs and focuses solely on
the wirelength cost. For instance, in these embodiments, a planar
expansion in layer 2 or 3 has a G cost that equals the
Current_Drop's G cost plus a unit length cost L. A planar expansion
in layer 4 or 5 has a G cost that equals the Current_Drop's G cost
plus L* {square root over (2)}. A non-planar expansion between two
overlapping nodes has a G cost that equals the Current_Drop's G
cost plus X*L, where X is the via-scaling factor. An internal zig
or an external zig expansion has a G cost that equals the
Current_Drop's G cost plus (X+ {square root over (2)})*L. Some
embodiments disallow expansion on a node edge for which the
associated congestion edge has a capacity less than 1.
IV. Computer System
FIG. 31 conceptually illustrates a computer system with which one
embodiment of the invention is implemented. Computer system 3100
includes a bus 3105, a processor 3110, a system memory 3115, a
read-only memory 3120, a permanent storage device 3125, input
devices 3130, and output devices 3035.
The bus 3105 collectively represents all system, peripheral, and
chipset buses that support communication among internal devices of
the computer system 3100. For instance, the bus 3105
communicatively connects the processor 3110 with the read-only
memory 3120, the system memory 3115, and the permanent storage
device 3125.
From these various memory units, the processor 3110 retrieves
instructions to execute and data to process in order to execute the
processes of the invention. The read-only-memory (ROM) 3120 stores
static data and instructions that are needed by the processor 3110
and other modules of the computer system. The permanent storage
device 3125, on the other hand, is a read-and-write memory device.
This device is a non-volatile memory unit that stores instruction
and data even when the computer system 3100 is off. Some
embodiments of the invention use a mass-storage device (such as a
magnetic or optical disk and its corresponding disk drive) as the
permanent storage device 3125. Other embodiments use a removable
storage device (such as a floppy disk or zip.RTM. disk, and its
corresponding disk drive) as the permanent storage device.
Like the permanent storage device 3125, the system memory 3115 is a
read-and-write memory device. However, unlike storage device 3125,
the system memory is a volatile read-and-write memory, such as a
random access memory. The system memory stores some of the
instructions and data that the processor needs at runtime. In some
embodiments, the invention's processes are stored in the system
memory 3115, the permanent storage device 3125, and/or the
read-only memory 3120.
The bus 3105 also connects to the input and output devices 3130 and
3135. The input devices enable the user to communicate information
and select commands to the computer system. The input devices 3130
include alphanumeric keyboards and cursor-controllers. The output
devices 3135 display images generated by the computer system. For
instance, these devices display IC design layouts. The output
devices include printers and display devices, such as cathode ray
tubes (CRT) or liquid crystal displays (LCD).
Finally, as shown in FIG. 31, bus 3105 also couples computer 3100
to a network 3165 through a network adapter (not shown). In this
manner, the computer can be a part of a network of computers (such
as a local area network ("LAN"), a wide area network ("WAN"), or an
Intranet) or a network of networks (such as the Internet). Any or
all of the components of computer system 3100 may be used in
conjunction with the invention. However, one of ordinary skill in
the art will appreciate that any other system configuration may
also be used in conjunction with the invention.
The above-described router can produce multi-layer global routes
that have horizontal, vertical, and diagonal edges. FIG. 32
provides an example of one such global route. This route 3200
traverses layers 3, 4, and 5. As shown in this figure, this route
includes a via between layers 3 and 4, and an external zig via
between layers 4 and 5.
While the invention has been described with reference to numerous
specific details, one of ordinary skill in the art will recognize
that the invention can be embodied in other specific forms without
departing from the spirit of the invention. For instance, even
though the router described above is a flat global router, one of
ordinary skill will realize that the invention can be practiced
with hierarchical routers, such as a router described in U.S.
patent application Ser. No. 10/013,819, filed on Dec. 7, 2001.
Also, the routes and paths described above are defined with respect
to the node edges illustrated in FIGS. 4 through 7. These routes
and paths, however, can be defined differently. For instance, they
can be defined with respect to a set of edges that are orthogonal
to the edges illustrated in FIGS. 4 through 7.
In addition, many aspects of the invention can be practiced without
the congestion and length grids illustrated in FIGS. 1 and 2.
Alternatively, they can be practiced with different congestion and
length grids, or different structures for these grids. For
instance, in some embodiments, intersecting horizontal and vertical
lines might not form one or both these grids. Also, nodes might not
be defined in the center of the length-grid sub-regions.
Although the router described above uses horizontal, vertical, and
.+-.45 diagonal wiring, many aspects of the invention can be
practiced with a different set of interconnect lines. Also, some
embodiments might use costing equations that are different than
those described in Equations (A) (E) above. For instance, some
embodiments described above express the wirelength cost of a path p
as
e.function. ##EQU00018## Some embodiments might express such a path
cost as
e.function. ##EQU00019## where B is a factor related to the
importance of the net. This factor B is smaller (e.g., it is 1) for
important time-critical nets that need shorter routes, while it is
larger (e.g., it is 3) for non-critical nets that can have longer
routes. Accordingly, this factor causes the path search to try to
identify shorter paths for critical nets, by increasing the
wirelength cost of these nets much faster during path searches than
the wirelength cost of non-critical nets. Other embodiments might
use other exponential and non-exponential expressions in their cost
functions. Thus, one of ordinary skill in the art would understand
that the invention is not to be limited by the foregoing
illustrative details, but rather is to be defined by the appended
claims.
* * * * *