U.S. patent number 7,443,747 [Application Number 10/997,708] was granted by the patent office on 2008-10-28 for memory array bit line coupling capacitor cancellation.
This patent grant is currently assigned to Integrated Device Technology, Inc.. Invention is credited to Chuen-Der Lien, Tzong-Kwang Henry Yeh.
United States Patent |
7,443,747 |
Lien , et al. |
October 28, 2008 |
Memory array bit line coupling capacitor cancellation
Abstract
Capacitive coupling correction circuits are coupled between
adjacent parallel dynamic (pre-charged) or static conductors. The
capacitive coupling correction circuits effectively isolate a low
voltage applied to a first conductor from a high pre-charged
voltage stored on an adjacent second conductor (or vice versa). The
adjacent parallel conductors can be bit lines of a memory cell.
Each capacitive coupling correction circuit can include an inverter
having an input terminal coupled to the first conductor, and an
output terminal coupled to a first plate of a capacitor. A second
plate of the capacitor is coupled to the second conductor. The
capacitance of the capacitor is selected to be identical to a
parasitic capacitance between the first and second conductors. As a
result, there is a zero net voltage effect between the first and
second conductors. The capacitive coupling correction circuits may
be distributed along the length of the first and second
conductors.
Inventors: |
Lien; Chuen-Der (Los Altos
Hills, CA), Yeh; Tzong-Kwang Henry (Palo Alto, CA) |
Assignee: |
Integrated Device Technology,
Inc. (San Jose, CA)
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Family
ID: |
35757196 |
Appl.
No.: |
10/997,708 |
Filed: |
November 23, 2004 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20060028860 A1 |
Feb 9, 2006 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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60600351 |
Aug 9, 2004 |
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Current U.S.
Class: |
365/203;
365/154 |
Current CPC
Class: |
G11C
5/063 (20130101); G11C 7/02 (20130101); G11C
7/12 (20130101); G11C 8/16 (20130101); G11C
11/419 (20130101) |
Current International
Class: |
G11C
7/00 (20060101) |
Field of
Search: |
;365/203,154,149 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Tran; Michael T
Attorney, Agent or Firm: Bever, Hoffman & Harms LLP
Parent Case Text
RELATED APPLICATION
The present application is related to and claims priority of U.S.
Provisional Patent Application Ser. No. 60/600,351 filed by
Chuen-Der Lien and Tzong-Kwang Henry Yeh on Aug. 9, 2004.
Claims
We claim:
1. A circuit comprising: a first conductor; a second conductor
located adjacent to the first conductor, wherein the second
conductor extends in parallel with the first conductor, and wherein
a parasitic capacitance exists between the first and second
conductors; a first capacitor coupling correction circuit coupled
between the first and second conductors, wherein the first
capacitor coupling correction circuit includes a first capacitor
having a first capacitance selected to be approximately equal to
the parasitic capacitance, wherein the first capacitor coupling
correction circuit further comprises a first inverter having an
input terminal coupled to the first conductor, wherein the first
capacitor is coupled between an output terminal of the first
inverter and the second conductor.
2. A circuit comprising: a first conductor, wherein the first
conductor is a first bit line coupled to a column of memory cells;
a second conductor located adjacent to the first conductor, wherein
the second conductor is a second bit line coupled to the column of
memory cells, wherein the second conductor extends in parallel with
the first conductor, without crossing the first conductor, and
wherein a parasitic capacitance exists between the first and second
conductors; and a first capacitor coupling correction circuit
coupled between the first and second conductors, wherein the first
capacitor coupling correction circuit includes a first capacitor
having a first capacitance selected to be approximately equal to
the parasitic capacitance.
3. The circuit of claim 2, wherein the first bit line is coupled to
a first port of each memory cell in the column of memory cells, and
the second bit line is coupled to a second port of each memory cell
in the column of memory cells.
4. The circuit of claim 3, further comprising: a third conductor
adjacent to the first conductor, and extending in parallel with the
first conductor, wherein the third conductor is coupled to the
first port of each memory cell in the column of memory cells; and a
fourth conductor adjacent to the second conductor, and extending in
parallel with the second conductor, wherein the fourth conductor is
coupled to the second port of each memory cell in the column of
memory cells.
5. A circuit comprising: a first conductor; a second conductor
located adjacent to the first conductor, wherein the second
conductor extends in parallel with the first conductor, without
crossing the first conductor, and wherein a parasitic capacitance
exists between the first and second conductors; a first capacitor
coupling correction circuit coupled between the first and second
conductors, wherein the first capacitor coupling correction circuit
includes a first capacitor having a first capacitance selected to
be approximately equal to the parasitic capacitance; and a second
capacitor coupling correction circuit coupled between the first and
second conductors, wherein the second capacitor coupling correction
circuit includes a second capacitor having a second capacitance
selected to be approximately equal to the parasitic
capacitance.
6. A circuit comprising: a first conductor; a second conductor
located adjacent to the first conductor, wherein the second
conductor extends in parallel with the first conductor, and wherein
a parasitic capacitance exists between the first and second
conductors; a first capacitor coupling correction circuit coupled
between the first and second conductors, wherein the first
capacitor coupling correction circuit includes a first capacitor
having a first capacitance selected to be approximately equal to
the parasitic capacitance, wherein the first capacitor coupling
correction circuit further comprises a first inverter having an
input terminal coupled to the first conductor, wherein the first
capacitor is coupled between an output terminal of the first
inverter and the second conductor, and a second capacitor coupling
correction circuit coupled between the first and second conductors,
wherein the second capacitor coupling correction circuit includes a
second capacitor having a second capacitance selected to be
approximately equal to the parasitic capacitance, wherein the
second capacitor coupling correction circuit further comprises a
second inverter having an input terminal coupled to the second
conductor, wherein the second capacitor is coupled between an
output terminal of the second inverter and the first conductor.
7. A circuit comprising: a first conductor; a second conductor
located adjacent to the first conductor, wherein the second
conductor extends in parallel with the first conductor, and wherein
a parasitic capacitance exists between the first and second
conductors; a plurality N of first capacitor coupling correction
circuits coupled between the first and second conductors, wherein
each of the first capacitor coupling correction circuits includes a
capacitor having a capacitance selected to be approximately equal
to 1/N of the parasitic capacitance.
8. The circuit of claim 7, wherein each of the first capacitor
coupling correction circuits comprises: a first inverter having an
input terminal coupled to the first conductor; and the capacitor
coupled between an output terminal of the first inverter and the
second conductor.
9. The circuit of claim 7, wherein the first conductor is a first
bit line coupled to a column of memory cells, and the second
conductor is a second bit line coupled to the column of memory
cells.
10. The circuit of claim 9, wherein the first bit line is coupled
to a first port of each memory cell in the column of memory cells,
and the second bit line is coupled to a second port of each memory
cell in the column of memory cells.
11. The circuit of claim 10, further comprising: a third conductor
adjacent to the first conductor, and extending in parallel with the
first conductor, wherein the third conductor is coupled to the
first port of each memory cell in the column of memory cells; and a
fourth conductor adjacent to the second conductor, and extending in
parallel with the second conductor, wherein the fourth conductor is
coupled to the second port of each memory cell in the column of
memory cells.
12. The circuit of claim 7, further comprising a plurality N of
second capacitor coupling correction circuits coupled between the
first and second conductors, wherein each of the second capacitor
coupling correction circuits includes a capacitor having a
capacitance selected to be approximately equal to 1/N of the
parasitic capacitance.
13. The circuit of claim 12, wherein each of the second capacitor
coupling correction circuits comprises: a second inverter having an
input terminal coupled to the second conductor; and the capacitor
coupled between an output terminal of the second inverter and the
first conductor.
Description
FIELD OF THE INVENTION
The present invention relates to systems that implement parallel
dynamic (pre-charged) nodes and parallel static nodes.
RELATED ART
FIG. 1 is a circuit diagram of a column 100 of a conventional
dual-port static random access memory (SRAM) array. SRAM column 100
includes dual-port SRAM memory cells 101.sub.0 101.sub.N, p-channel
pre-charge transistors 121 122 and 131 132, pre-charge enable lines
PREC.sub.A and PREC.sub.B, word lines WL.sub.A0 WL.sub.AN and
WL.sub.B0 WL.sub.BN and bit lines BL.sub.A BL.sub.A# and BL.sub.B
BL.sub.B#. Bit lines BL.sub.A BL.sub.A# are coupled to a first port
(PORT.sub.A) of each memory cell of column 100, and bit lines
BL.sub.B BL.sub.B# are coupled to a second port (PORT.sub.B) of
each memory cell in column 100.
Dual-port SRAM cell 101.sub.0 includes p-channel pull-up
transistors 111 112, n-channel pull-down transistors 113 114, first
port access transistors 115 116, and second port access transistors
117 118. Transistors 111 114 are configured to form a latch
circuit, which is used to store a data value. The other SRAM cells
in column 100, including SRAM cell 101.sub.N, are identical to SRAM
cell 101.sub.0.
Each of the bit lines BL.sub.A BL.sub.A# and BL.sub.B BL.sub.B#
exhibits a parasitic capacitance to ground, and a parasitic
capacitance between adjacent bit lines. The parasitic capacitance
C.sub.AB between adjacent bit lines BL.sub.A and BL.sub.B is
illustrated as capacitive element 140. The parasitic capacitance
C.sub.A between bit line BL.sub.A and ground is illustrated as
capacitive element 141. The parasitic capacitance C.sub.B between
bit line BL.sub.B and ground is illustrated as capacitive element
142.
The parasitic capacitances C.sub.A, C.sub.B and C.sub.AB can result
in erroneous read operations in certain conditions. For example,
assume that SRAM cell 101.sub.0 stores a logic "1" value, such that
a logic high voltage is stored on node N1, and a logic low voltage
is stored on node N0. To perform a read operation on the second
port (PORT.sub.B), the PREC.sub.B signal is activated low, thereby
turning on pre-charge transistors 131 132, and pre-charging bit
lines BL.sub.B BL.sub.B# to the V.sub.DD supply voltage. After bit
lines have been pre-charged to the V.sub.DD supply voltage, the
PREC.sub.B signal is deactivated high, thereby turning off
pre-charge transistors 131 132. The word line signal on word line
WL.sub.B0 is then activated high for a period of time, thereby
turning on n-channel access transistors 117 and 118. At this time,
the logic high voltage on node N1 tends to maintain the V.sub.DD
voltage on bit line BL.sub.B, and the logic low voltage on node N0
tends to pull down the voltage on bit line BL.sub.B#. For example,
the voltage on bit line BL.sub.B may be equal to a full V.sub.DD
supply voltage of 1.8 Volts, while the voltage on bit line
BL.sub.B# may be pulled down to 1.7 Volts. A sense amplifier (not
shown) detects the small voltage difference across bit lines
BL.sub.B and BL.sub.B# to determine the state of the data value
stored by SRAM cell 101.sub.0.
A write operation can be performed on the first port of SRAM cell
101.sub.N at the same time that the above-described read operation
is performed on the second port of SRAM cell 101.sub.0. For
example, to write a logic "0" value to the first port (PORT.sub.A)
of SRAM cell 101.sub.N, the PREC.sub.A signal is activated low,
thereby turning on pre-charge transistors 121 122, and pre-charging
bit lines BL.sub.A BL.sub.A# to the V.sub.DD supply voltage. After
the bit lines BL.sub.A BL.sub.A# have been pre-charged to the
V.sub.DD supply voltage, the PREC.sub.A signal is deactivated high,
thereby turning off pre-charge transistors 121 122. The signal on
word line WL.sub.AN is then activated high for a period of time,
thereby turning on the n-channel access transistors associated with
the first port of SRAM cell 101.sub.N. The logic "0" data value is
applied to bit lines BL.sub.A BL.sub.A#, such that the V.sub.DD
supply voltage is applied to bit line BL.sub.A#, and the V.sub.SS
ground supply voltage (0 Volts) is applied to bit line
BL.sub.A.
As described above, the parasitic capacitance C.sub.AB electrically
couples adjacent bit lines BL.sub.A and BL.sub.B. That is, the
parasitic capacitance C.sub.AB electrically couples the voltage
drop on bit line BL.sub.A (i.e., from 1.8 Volts to 0 Volts) to bit
line BL.sub.B. As a result, the voltage on bit line BL.sub.B is
undesirably reduced. In some instances, the voltage on bit line
BL.sub.B is reduced low enough to cause an erroneous data value to
be detected on bit lines BL.sub.B BL.sub.B#. More specifically, the
voltage on bit line BL.sub.B can be reduced from the desired value
of 1.8 Volts to a voltage that is lower than the voltage on bit
line BL.sub.B#. For example, the voltage on bit line BL.sub.B can
be reduced to 1.6 Volts, while the voltage on bit line BL.sub.B#
remains at 1.7 Volts. In this case, a logic "0" value is
erroneously read from the second port of memory cell 101.sub.0 on
bit lines BL.sub.B BL.sub.B#.
The above-described problem has been solved in various ways in the
past. In one conventional memory, a metal line is routed down the
center of the SRAM column 100, at the location generally indicated
by dashed region 150. A static voltage, such as V.sub.DD or ground,
is coupled to the metal line. As a result, the parasitic
capacitance C.sub.AB between adjacent bit lines BL.sub.A and
BL.sub.B is minimized. However, the formation of a metal line for
each column of the memory array disadvantageously requires a
relatively large layout area.
In another conventional memory, bit line BL.sub.A is twisted with
bit line BL.sub.A#, and the bit line BL.sub.B is twisted with bit
line BL.sub.B#. FIG. 2 illustrates an SRAM column 200 having
twisted bit lines. Similar elements in FIGS. 1 and 2 are labeled
with similar reference numbers. The bit lines BL.sub.A BL.sub.A#
and BL.sub.B BL.sub.B# are twisted at their midpoints, as
illustrated by the dashed lines. As a result, the parasitic
capacitance C'.sub.AB between bit lines BL.sub.A and BL.sub.B is
reduced (based on the increased spacing between bit lines BL.sub.A
and BL.sub.B in the upper half of the SRAM column 200. The reduced
parasitic capacitance C'.sub.AB results in a reduced electrical
coupling between bit lines BL.sub.A and BL.sub.B. However,
electrical coupling still exists between bit lines BL.sub.A and
BL.sub.B, which can result in the erroneous read conditions
described above. In addition, the bit line twisting requires
additional layout area compared to a non-twisted bit line
arrangement.
It would therefore be desirable to have an improved data
transmission structure that enables adjacent dynamic (pre-charged)
conductive elements to properly transmit data signals in spite of
the parasitic capacitive coupling inherent between these conductive
elements. It would further be desirable if such a structure could
be implemented without significantly increasing the layout area of
a conventional data transmission structure.
SUMMARY
Accordingly, the present invention provides capacitive coupling
correction circuits, which are coupled between adjacent parallel
dynamic (pre-charged) or static conductors. The capacitive coupling
correction circuits effectively isolate a low voltage applied to a
first conductor from a high pre-charged voltage stored on an
adjacent second conductor (or vice versa). The adjacent parallel
conductors can be, for example, bit lines of a memory cell. In a
particular embodiment, each capacitive coupling correction circuit
can include an inverter having an input terminal coupled to a first
conductor, and an output terminal coupled to a first plate of a
capacitor. A second plate of the capacitor is coupled to a second
conductor. The capacitance of the capacitor is selected to be
identical to a parasitic capacitance between the first and second
conductors. As a result, there is a zero net voltage effect between
the first and second conductors. In another embodiment, the
capacitive coupling correction circuits are distributed along the
length of the first and second conductors.
The present invention will be more fully understood in view of the
following description and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of a conventional column of multi-port
SRAM memory cells.
FIG. 2 is a circuit diagram of a conventional column of multi-port
SRAM memory cells that implements twisted bit lines.
FIG. 3 is a circuit diagram of a column of multi-port SRAM memory
cells in accordance with one embodiment of the present
invention.
FIG. 4 is a circuit diagram of a column of multi-port SRAM memory
cells in accordance with another embodiment of the present
invention.
DETAILED DESCRIPTION
FIG. 3 is a circuit diagram of a column 300 of multi-port SRAM
memory cells in accordance with one embodiment of the present
invention. It is understood that any number of SRAM columns,
identical to SRAM column 300, can be combined to form a memory
array. Similar elements in FIGS. 1 and 3 are labeled with similar
reference numbers. Thus, SRAM column 300 includes dual-port SRAM
memory cells 101.sub.0 101.sub.N, p-channel pre-charge transistors
121 122 and 131 132, pre-charge lines PREC.sub.A and PREC.sub.B,
word lines WL.sub.A0 WL.sub.AN and WL.sub.B0 WL.sub.BN, bit lines
BL.sub.A BL.sub.A# and BL.sub.B BL.sub.B#, and parasitic
capacitance elements 140-142, which have been described above in
connection with FIG. 1.
In addition, SRAM column 300 includes capacitive coupling
correction circuits 301 and 302. Capacitive coupling correction
circuit 301 includes inverter 311 and capacitor 312. Inverter 311
has an input terminal coupled to bit line BL.sub.A and an output
terminal coupled to capacitor 312. Capacitor 312 is further coupled
to bit line BL.sub.B. Capacitor 312 is selected to have a
capacitance C.sub.C1, which is matched to the parasitic capacitance
C.sub.AB. In a particular embodiment, capacitive element 140
exhibits a parasitic capacitance C.sub.AB on the order of about 10
femto-Farads.
Similarly, capacitive coupling correction circuit 302 includes
inverter 321 and capacitor 322. Inverter 321 has an input terminal
coupled to bit line BL.sub.B and an output terminal coupled to
capacitor 322. Capacitor 322 is further coupled to bit line
BL.sub.A. Capacitor 322 is selected to have a capacitance C.sub.C2,
which is also matched to the parasitic capacitance C.sub.AB. Each
of inverters 311 and 321 provides an output signal that swings
between the V.sub.DD voltage supply and ground.
Capacitor coupling correction circuit 301 operates as follows. To
write a logic "0" value to memory cell 101.sub.N on the first port
(PORT.sub.A), bit lines BL.sub.A and BL.sub.A# are pre-charged to
the V.sub.DD supply voltage (by enabling transistors 121 122), word
line WL.sub.AN is activated, a logic low voltage is applied to bit
line BL.sub.A and a logic high voltage is applied to bit line
BL.sub.A#. As a result, a logic "0" value is stored in SRAM cell
101.sub.N.
As described above in connection with FIG. 1, the logic low voltage
applied to bit line BL.sub.A is electrically coupled to bit line
BL.sub.B by parasitic capacitance 140, thereby tending to pull down
the voltage on bit line BL.sub.B. However, the logic low voltage on
bit line BL.sub.A is applied to the input terminal of inverter 311.
In response, inverter 311 provides a logic high output signal to
capacitor 312. The logic high voltage applied to capacitor 312
tends to pull up the voltage on bit line BL.sub.B. Because the
capacitance C.sub.C1 of capacitor 312 is matched to the parasitic
capacitance C.sub.AB of capacitive element 140, the voltage on bit
line BL.sub.B is unaffected by the logic low voltage on bit line
BL.sub.A. That is, the amount of charge drawn off of bit line
BL.sub.B as a result of the parasitic capacitance C.sub.AB of
capacitive element 140 is equal to the amount of charge supplied to
bit line BL.sub.B as a result of the capacitance C.sub.C1 of
capacitor 312.
Capacitive coupling correction circuit 302 operates in the same
manner as correction circuit 301, thereby preventing a low voltage
on bit line BL.sub.B from affecting the voltage on bit line
BL.sub.A.
Capacitive coupling correction circuits 301 and 302 advantageously
allow SRAM column 300 to have a smaller size when compared with
conventional the conventional SRAM columns of FIGS. 1 and 2.
FIG. 4 is a circuit diagram of an SRAM column 400 in accordance
with another embodiment of the present invention. Similar elements
in FIGS. 3 and 4 are labeled with similar reference numbers. In the
present embodiment, capacitive coupling correction circuit 301 is
effectively split into a pair of capacitive coupling correction
circuits 401A and 401B, which are located at the top and bottom,
respectively, of the SRAM column 400. Similarly, capacitive
coupling correction circuit 302 is effectively split into a pair of
capacitive coupling correction circuits 402A and 402B, which are
located at the top and bottom, respectively, of the SRAM column
400.
Capacitive coupling correction circuit 401A includes inverter 411A
and capacitor 412A, which are coupled between bit lines BL.sub.A
and BL.sub.B in the same manner as inverter 311 and capacitor 312
in FIG. 3. Similarly, capacitive coupling correction circuit 401B
includes inverter 411B and capacitor 412B, which are also coupled
between bit lines BL.sub.A and BL.sub.B in the same manner as
inverter 311 and capacitor 312 in FIG. 3. Capacitors 412A and 412B
exhibit capacitances C.sub.C1A and C.sub.C1B, respectively. Each of
these capacitances C.sub.C1A and C.sub.C1B is selected to be equal
to one half of the parasitic capacitance C.sub.AB between bit lines
BL.sub.A and BL.sub.B. Collectively, capacitive coupling correction
circuits 401A and 401B operate in the same manner as capacitive
coupling correction circuit 301 (FIG. 3).
Capacitive coupling correction circuit 402A includes inverter 421A
and capacitor 422A, which are coupled between bit lines BL.sub.A
and BL.sub.B in the same manner as inverter 321 and capacitor 322
in FIG. 3. Similarly, capacitive coupling correction circuit 402B
includes inverter 421B and capacitor 422B, which are also coupled
between bit lines BL.sub.A and BL.sub.B in the same manner as
inverter 321 and capacitor 322 in FIG. 3. Capacitors 422A and 422B
exhibit capacitances C.sub.C2A and C.sub.C2B, respectively. Each of
these capacitances C.sub.C2A and C.sub.C2B is selected to be equal
to one half of the parasitic capacitance C.sub.AB between bit lines
BL.sub.A and BL.sub.B. Collectively, capacitive coupling correction
circuits 402A and 402B operate in the same manner as capacitive
coupling correction circuit 302 (FIG. 3).
Capacitive coupling correction circuits 401A 401B and 402A 402B
advantageously distribute the capacitive coupling correction
function over the full length of the bit lines BL.sub.A and
BL.sub.B. In other embodiments, other numbers of capacitive
coupling circuits can be distributed along the length of the bit
lines BL.sub.A and BL.sub.B.
Although the present invention has been described in connection
with a dual-port memory cell, it is understood that the present
invention can be applied to single port memory cells or multi-port
memory cells having more than two ports. Moreover, the present
invention can be applied to any system that implements parallel
line dynamic (pre-charged) or static nodes.
Although the invention has been described in connection with
several embodiments, it is understood that this invention is not
limited to the embodiments disclosed, but is capable of various
modifications, which would be apparent to a person skilled in the
art. Thus, the invention is limited only by the following
claims.
* * * * *