U.S. patent number 7,045,396 [Application Number 10/439,671] was granted by the patent office on 2006-05-16 for stackable semiconductor package and method for manufacturing same.
This patent grant is currently assigned to Amkor Technology, Inc.. Invention is credited to Angel Orabuena Alvarez, Sean Timothy Crowley, Jun Young Yang.
United States Patent |
7,045,396 |
Crowley , et al. |
May 16, 2006 |
Stackable semiconductor package and method for manufacturing
same
Abstract
Leadframe-type semiconductor packages that allow the
semiconductor packages to be stacked on top of each other. One
aspect of the semiconductor package includes a leadframe, a
plurality of electrical connectors, a semiconductor chip, and a
sealing material for encapsulating the above components. The
leadframe has a plurality of leads, with each one of the plurality
of leads running from the top of the semiconductor package to the
bottom of the semiconductor package. Each one of the plurality of
leads has a top portion protruding from the top surface of the
semiconductor package and a bottom portion protruding from the top
surface of the semiconductor package and a bottom portion
protruding from the bottom surface of the semiconductor package.
The leads allow for electrical connection of a second semiconductor
package placed on top of the first semiconductor package. Further,
the protruding parts of the leads form a space between the stacked
semiconductor packages for improved heat dissipation.
Inventors: |
Crowley; Sean Timothy (Phoenix,
AZ), Alvarez; Angel Orabuena (Gilbert, AZ), Yang; Jun
Young (Seoul, KR) |
Assignee: |
Amkor Technology, Inc.
(Chandler, AZ)
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Family
ID: |
19626250 |
Appl.
No.: |
10/439,671 |
Filed: |
May 16, 2003 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20030197290 A1 |
Oct 23, 2003 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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09687531 |
Oct 13, 2000 |
6605866 |
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Foreign Application Priority Data
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Dec 16, 1999 [KR] |
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99-58166 |
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Current U.S.
Class: |
438/123; 257/777;
257/692; 257/E23.047; 257/E23.124; 257/E25.023 |
Current CPC
Class: |
H01L
23/49551 (20130101); H01L 23/3107 (20130101); H01L
25/105 (20130101); H01L 2224/48247 (20130101); H01L
2924/0105 (20130101); H01L 2924/01028 (20130101); H01L
24/45 (20130101); H01L 2224/48245 (20130101); H01L
2224/48091 (20130101); H01L 2924/181 (20130101); H01L
2224/45124 (20130101); H01L 24/48 (20130101); H01L
2224/32245 (20130101); H01L 2924/01046 (20130101); H01L
2224/45144 (20130101); H01L 2924/01013 (20130101); H01L
2225/1058 (20130101); H01L 2225/1041 (20130101); H01L
2924/01039 (20130101); H01L 2225/1029 (20130101); H01L
2924/1532 (20130101); H01L 2224/73265 (20130101); H01L
2924/15311 (20130101); H01L 2924/01079 (20130101); H01L
2224/49433 (20130101); H01L 2924/14 (20130101); H01L
2924/00014 (20130101); H01L 2224/45139 (20130101); H01L
2224/48091 (20130101); H01L 2924/00014 (20130101); H01L
2224/45124 (20130101); H01L 2924/00014 (20130101); H01L
2224/45139 (20130101); H01L 2924/00014 (20130101); H01L
2224/45144 (20130101); H01L 2924/00014 (20130101); H01L
2224/73265 (20130101); H01L 2224/32245 (20130101); H01L
2224/48247 (20130101); H01L 2924/00 (20130101); H01L
2924/181 (20130101); H01L 2924/00012 (20130101); H01L
2224/73265 (20130101); H01L 2224/32245 (20130101); H01L
2224/48247 (20130101); H01L 2924/00012 (20130101); H01L
2924/00014 (20130101); H01L 2224/45015 (20130101); H01L
2924/207 (20130101) |
Current International
Class: |
H01L
21/44 (20060101) |
Field of
Search: |
;257/692,777
;438/123 |
References Cited
[Referenced By]
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Primary Examiner: Wilson; Christian D.
Attorney, Agent or Firm: Stetina Brunda Garred &
Brucker
Parent Case Text
CROSS REFERENCE TO RELATED APPLICATION
The present application is a divisional of U.S. application Ser.
No. 09/687,531 entitled STACKABLE SEMICONDUCTOR PACKAGE AND METHOD
FOR MANUFACTURING SAME filed Oct. 13, 2002, now U.S. Pat. No.
6,605,866.
Claims
What is claimed is:
1. A method of fabricating a semiconductor package, comprising the
steps of: a) providing a leadframe comprising: a die paddle
defining opposed, generally planar top and bottom surfaces; and a
plurality of leads extending at least partially about the die
paddle in spaced relation thereto, each of the leads having an
upper portion defining a generally planar top side and a first end,
a lower portion defining a generally planar bottom side and a
second end, and a middle portion extending between the upper and
lower portions; the transition from the first end to the second end
in each of the leads occurring without the lower portion reversing
direction to extend along the upper portion; b) attaching a
semiconductor chip to the top surface of the die paddle; c)
electrically connecting the semiconductor chip to at least one of
the leads; and d) at least partially encapsulating the leadframe
and the semiconductor chip with a sealing material such that the
bottom sides of the lower portions of the leads and the top sides
of the upper portions of the leads are exposed in the sealing
material.
2. The method of claim 1 wherein: step (c) comprises electrically
connecting the semiconductor chip to the lower portion of at least
one of the leads via a conductive wire; and step (d) comprises
encapsulating the conductive wire with the sealing material.
3. The method of claim 2 wherein step (c) comprises connecting the
conductive wire to a bond side of the lower portion which is
disposed in opposed relation to the bottom side and extends in
generally co-planar relation to the top surface of the die
paddle.
4. The method of claim 1 wherein step (d) comprises partially
encapsulating the leadframe such that the bottom surface of the die
paddle is exposed in the sealing material.
5. The method of claim 4 wherein step (d) comprises filling the
sealing material into a notched portion which extends about the
bottom surface of the die paddle.
6. The method of claim 1 wherein step (d) comprises filling the
sealing material into an etched portion formed within the upper and
lower portions of each of the leads.
7. The method of claim 1 further comprising the steps of: e)
attaching a top section to the top side of the upper section of
each of the leads such that the top section protrudes outwardly
from the sealing material; and f) attaching a bottom section to the
bottom side of the lower section of each of the leads such that the
bottom section protrudes outwardly from the sealing material.
8. The method of claim 7 wherein: step (e) comprises attaching a
solder plate to the top side of the upper section of each of the
leads; and step (f) comprises attaching a solder plate to the
bottom side of the lower section of each of the leads.
9. A method of fabricating a semiconductor package, comprising the
steps of: a) providing a leadframe comprising: a die paddle
defining opposed, generally planar top and bottom surfaces; a first
set of leads extending at least partially about the die paddle in
spaced relation thereto; and a second set of leads extending at
least partially about the leads of the first set in spaced relation
thereto, each of the leads of the first and second sets having an
upper portion defining a generally planar top side and a first end,
a lower portion defining a generally planar bottom side and a
second end, and a middle portion extending between the upper and
lower portions, the transition from the first end to the second end
in each of the leads of the first and second sets occuring without
the lower portion reversing direction to extend along the upper
portion; b) attaching a semiconductor chip to the top surface of
the die paddle; c) electrically connecting the semiconductor chip
to at least one of the leads of each of the first and second sets;
and d) partially encapsulating the leadframe and the semiconductor
chip with a sealing material such that the bottom sides of the
lower portions of the leads of the first and second sets and the
top sides of the upper portions of the leads of the first and
second sets are exposed in the sealing material.
10. The method of claim 9 wherein: step (c) comprises electrically
connecting the semiconductor chip to the lower portion of at least
one of the leads of each of the first and second sets via
conductive wires; and step (d) comprises encapsulating the
conductive wires with the sealing material.
11. The method of claim 10 wherein step (c) comprises connecting
each of the conductive wires to a bond side of the lower portion
which is disposed in opposed relation to the bottom side and
extends in generally co-planar relation to the top surface of the
die paddle.
12. The method of claim 9 wherein step (d) comprises partially
encapsulating the leadframe with the sealing material such that the
bottom surface of the die paddle is exposed in the sealing
material.
13. The method of claim 12 wherein step (d) comprises filling the
sealing material into a notched portion which extends about the
bottom surface of the die paddle.
14. The method of claim 9 wherein step (d) comprises filling the
sealing material into an etched portion formed in the upper and
lower portions of each of the leads of each of the first and second
sets.
15. The method of claim 9 further comprising the steps of: e)
attaching a top section to the top side of the upper section of
each of the leads of the first and second sets such that each of
the top sections protrudes outwardly from the sealing material; and
attaching a bottom section to the bottom side of the lower section
of each of the leads of the first and second sets such that each of
the bottom sections protrudes outwardly from the sealing
material.
16. The method of claim 15 wherein: step (e) comprises attaching a
solder plate to the top side of the upper section of each of the
leads of the first and second sets; and step (f) comprises
attaching a solder plate to the bottom side of the lower section of
each of the leads of the first and second sets.
17. A method of fabricating a chip stack, comprising the steps of:
a) providing first and second semiconductor packages, each of which
comprises: a die paddle defining opposed, generally planar top and
bottom surfaces; a plurality of leads extending at least partially
about the die paddle in spaced relation thereto, each of the leads
having an upper portion defining a generally planar top side and
first end, a lower portion defining a generally planar bottom side,
and a middle portion extending between the upper and lower
portions, the transition from the first end to the second end in
each of the leads occurring without the lower portion reversing
direction to extend along the upper portion; a semiconductor chip
attached to the top surface of the die paddle and electrically
connected to at least one of the leads; and a sealing material at
least partially encapsulating the leadframe and the semiconductor
chip such that the bottom sides of the lower portions of the leads
and the top sides of the upper portions of the leads are exposed in
the sealing material; and b) electrically connecting the top sides
of the upper portions of the leads of the first semiconductor
package to respective ones of the top sides of the upper portions
of the leads of the second semiconductor package.
18. The method of claim 17 further comprising the step of: c)
electrically connecting a third semiconductor package to the bottom
sides of the lower portions of the leads of one of the first and
second semiconductor packages.
19. A method of fabricating a chip stack, comprising the steps of:
a) providing first and second semiconductor packages, each of which
comprises: a die paddle defining opposed, generally planar top and
bottom surfaces; a first set of leads extending at least partially
about the die paddle in spaced relation thereto; a second set of
leads extending at least partially about the leads of the first set
in spaced relation thereto, each of the leads of the first and
second sets having an upper portion defining a generally planar top
side and a first end, a lower portion defining a generally planar
bottom side and a second end, and a middle portion extending
between the upper and lower portions the transition from the first
end to the second end in each of the leads of the first and second
sets occurring without the lower portion reversing direction to
extend along the upper portion; a semiconductor chip attached to
the top surface of the die paddle and electrically connected to at
least one of the leads of each of the first and second sets; and a
sealing material at least partially encapsulating the leadframe and
the semiconductor chip such that the bottom sides of the lower
portions of the leads of the first and second sets and the top
sides of the upper portions of the leads of the first and second
sets are exposed in the sealing material; b) electrically
connecting the bottom sides of the lower portions of the leads of
the first set of the first semiconductor package to respective ones
of the bottom sides of the lower portions of the leads of the first
set of the second semiconductor package; and c) electrically
connecting the bottom sides of the lower portions of the leads of
the second set of the first semiconductor package to respective
ones of the bottom sides of the lower portions of the leads of the
second set of the second semiconductor package.
Description
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packages, leadframe
assemblies therefor, and a method of manufacture, and, more
particularly, but not by way of limitation, to leadframe-type
semiconductor packages that allow the semiconductor packages to be
stacked one atop the other.
2. History of Related Art
It is conventional in the electronics industry to encapsulate one
or more semiconductor devices, such as integrated circuit dies, or
chips, in a semiconductor package. These plastic packages protect a
chip from environmental hazards, and provide a method of and
apparatus for electrically and mechanically attaching the chip to
an intended device. Recently, such semiconductor packages have
included metal leadframes for supporting an integrated circuit chip
which is bonded to a chip paddle region formed centrally therein.
Bond wires which electrically connect pads on the integrated
circuit chip to individual leads of the leadframe are then
incorporated. A hard plastic encapsulating material, or
encapsulant, which covers the bond wire, the integrated circuit
chip and other components, forms the exterior of the package. A
primary focus in this design is to provide the chip with adequate
protection from the external environment in a reliable and
effective manner.
As set forth above, the semiconductor package therein described
incorporates a leadframe as the central supporting structure of
such a package. A portion of the leadframe completely surrounded by
the plastic encapsulant is internal to the package. Portions of the
leadframe extend internally from the package and are then used to
connect the package externally. More information relative to
leadframe technology may be found in Chapter 8 of the book Micro
Electronics Packaging Handbook, (1989), edited by R. Tummala and E.
Rymaszewski, incorporated by reference herein. This book is
published by Van Nostrand Reinhold, 115 Fifth Avenue, New York,
N.Y.
Once the integrated circuit chips have been produced and
encapsulated in semiconductor packages described above, they may be
used in a wide variety of electronic appliances. The variety of
electronic devices utilizing semiconductor packages has grown
dramatically in recent years. These devices include cellular
phones, portable computers, etc. Each of these devices typically
includes a printed circuit board on which a significant number of
such semiconductor packages are secured to provide multiple
electronic functions. These electronic appliances are typically
manufactured in reduced sizes and at reduced costs, which results
in increased consumer demand. Accordingly, not only are
semiconductor chips highly integrated, but also semiconductor
packages are highly miniaturized with an increased level of package
mounting density.
According to such miniaturization tendencies, semiconductor
packages, which transmit electrical signals from semiconductor
chips to printed circuit boards and support the semiconductor chips
on the printed circuit boards, have been designed to have a small
size. By way of example only, such semiconductor packages may have
a size on the order of 1.times.10 mm to 10.times.10 mm.
Even though semiconductor packages have been miniaturized, space on
a printed circuit board remains limited and precious. Thus, there
is a need to find both a method and a semiconductor package design
to maximize the number of semiconductor packages that can be fitted
onto an electronic device, yet minimize the space needed to attach
these semiconductor packages. One method to minimize space needed
to attach the semiconductor packages is to stack the semiconductor
packages on top of each other.
Further, once the semiconductor packages are stacked onto each
other, there is a need to be able to adequately dissipate the heat
generated by the operation of each semiconductor chip in each one
of the semiconductor chip packages.
BRIEF SUMMARY OF THE INVENTION
The various embodiments of the present invention relate to
leadframe-type semiconductor packages that allow the semiconductor
packages to be stacked on top of each other. More particularly, one
aspect of the present invention comprises a semiconductor package
that includes a leadframe, a plurality of electrical connectors, a
semiconductor chip, and a sealing material for encapsulating the
above components. The leadframe has a plurality of leads, with each
one of the plurality of leads running from the top of the
semiconductor package to the bottom of the semiconductor package.
Each one of the plurality of leads has a top portion protruding
from the top surface of the semiconductor package and a bottom
portion protruding from the bottom surface of the semiconductor
package. The leads allow for electrical connection of a second
semiconductor package placed on top of the first semiconductor
package. Further, the protruding parts of the leads form a space
between the stacked semiconductor packages for improved heat
dissipation.
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete understanding of the method and apparatus of the
present invention may be had by reference to the following detailed
description with like reference numerals denoting like elements
when taken in conjunction with the accompanying drawings
wherein:
FIG. 1 is a cross-section of a prior art leadframe-type
semiconductor package;
FIG. 2 is a cross-section of an embodiment of a semiconductor
package constructed in accordance with the principles of the
present invention;
FIG. 3 is a bottom plan view of an embodiment of a semiconductor
package constructed in accordance with the principles of the
present invention;
FIG. 4 is a cross-section of another embodiment of a semiconductor
package constructed in accordance with the principles of the
present invention;
FIG. 5 is a cross-section of another embodiment of a semiconductor
package constructed in accordance with the principles of the
present invention;
FIG. 6 is a bottom plan view of another embodiment of a
semiconductor package constructed in accordance with the principles
of the present invention;
FIG. 7 is a cross-section of another embodiment of a semiconductor
package constructed in accordance with the principles of the
present invention;
FIG. 8 is a bottom plan view of another embodiment of a
semiconductor package constructed in accordance with the principles
of the present invention;
FIG. 9 is a cross-section of a semiconductor package stacked with
an embodiment of a semiconductor package constructed in accordance
with the principles of the present invention;
FIG. 10 is a cross-section of another semiconductor package stacked
with an embodiment of a semiconductor package constructed in
accordance with the principles of the present invention.
FIG. 11 is a cross-section of semiconductor packages stacked in an
alternate configuration according to one embodiment of the present
invention;
FIG. 12 is a cross-section of semiconductor packages stacked in an
alternate configuration according to one embodiment of the present
invention;
FIG. 13 is a cross-section of semiconductor packages stacked in
another alternate configuration according to one embodiment of the
present invention;
FIG. 14 is a cross-section of semiconductor packages stacked in
another alternate configuration according to one embodiment of the
present invention;
FIG. 15 is a side view of one embodiment of a semiconductor package
constructed in accordance with the principles of the present
invention;
FIG. 16 is a side view of one embodiment of a semiconductor package
constructed in accordance with the principles of the present
invention;
FIG. 17 is a side view of one embodiment of a semiconductor package
constructed in accordance with the principles of the present
invention; and
FIG. 18 is a side view of one embodiment of a semiconductor package
constructed in accordance with the principles of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
Prior to discussing the various embodiments of the present
invention, a prior art leadframe-type semiconductor package will be
discussed below in order to better understand MLF-type
semiconductor packages in general.
Referring first to FIG. 1, there is shown a cross-section of a
prior art leadframe-type semiconductor package 40. Semiconductor
package 40 has a leadframe 47 comprising a paddle 42 and a
plurality of leads 44, a semiconductor chip 41, and a plurality of
wires 43. The entire assembly is enclosed in a nonconductive
sealing material 45 such as thermoplastics or thermoset resins,
with thermoset resins including silicones, phenolics, and
epoxies.
Still referring to FIG. 1, semiconductor chip 41 is attached to
paddle 42. A plurality of connecting pads 46 are located on
semiconductor chip 41. A plurality of leads 44 surround, but do not
touch, semiconductor chip 41 and paddle 42. Wires 43 connect the
connecting pads 46 to leads 44. Leads 44 are generally rectangular
in cross-section. Leads 44 are located along the periphery of
semiconductor package 40 for connection with a printed circuit
board (not shown). Sealing material 45 encapsulates leads 44, wires
43, and semiconductor chip 41 except for the bottommost surfaces of
paddle 42 and leads 44. Since sealing material 45 is nonconductive,
if a second prior art semiconductor package (not shown) is stacked
on top of semiconductor package 40, the second prior art
semiconductor package cannot operate because it has no electrical
path to connect to. Thus, it is difficult if not impossible for
prior art leadframe-type semiconductor packages to be stacked on
top of each other and still operate as intended.
Still referring to FIG. 1, in leadframe-type semiconductor
packages, heat generated from the operation of semiconductor chip
41 is dissipated via a lower exposed surface of paddle 42 and the
lower and lateral exposed surfaces of leads 44. Thus, when prior
art leadframe-type semiconductor packages are stacked on each
other--even if the electrical connection problem is solved--the top
of the bottom semiconductor package touches the bottom of the top
semiconductor package and obstructs the heat flow from the second
semiconductor package to the outside, thereby preventing proper
heat dissipation by the second semiconductor package.
Referring to FIG. 2, there is shown a cross-section of
semiconductor package 50, which is an embodiment of a semiconductor
package constructed in accordance with the principles of the
present invention. Semiconductor package 50 has a semiconductor
chip 52, and a plurality of thin wires 53. The components listed
above are enclosed in a nonconductive sealing material 55 made of
thermoplastics or thermoset resins, with the thermoset resins
including silicones, phenolics, and epoxies.
Still referring to FIG. 2, the semiconductor package 50 has a
leadframe 62 comprising a paddle 51 and leads 54. Paddle 51 and
leads 54 are secured to leadframe 62 by a tie bar (not shown).
Paddle 51 has a top surface, a bottom surface, and may, but does
not necessarily have to, have a lateral etched side. The lateral
etched side, if present, increases the locking strength between
paddle 51 and sealing material 55. The top surface of paddle 51 is
attached to semiconductor chip 52 while the bottom surface of
paddle 51 is exposed to the outside of semiconductor package 50.
The exposed bottom surface of paddle 51 is electroplated with a
corrosion-minimizing material such as, for example, tin, gold, tin
lead, tin bismuth, nickel palladium, or an alloy thereof. The
bottom surface of paddle 51 may be attached to a printed circuit
board (not shown) or another semiconductor package constructed in
accordance with the principles of the present invention. Paddle 51
is made of an electrically and heat conducting material such as,
for example, copper. Heat generated from the operation of
semiconductor chip 52 can be dissipated to the outside of
semiconductor package 50 through the bottom surface of paddle
51.
Still referring to FIG. 2, a plurality of leads 54 surround but do
not touch paddle 51. Leads 54 are roughly "S" shaped and are made
of electrically conductive material such as, for example, copper.
Because all leads 54 are generally similar in construction, only
one of the leads 54 will be described in detail below. It should be
understood that the description applies to all leads 54.
Still referring to FIG. 2, lead 54 can be further subdivided into
three portions: upper portion 57, middle portion 58, and lower
portion 59. A small section 60 of the top side of upper portion 57
protrudes out of the top surface of semiconductor package 50.
Similarly, a small section 61 of the bottom side of lower portion
59 protrudes out of the bottom surface of semiconductor package 50.
Sections 60 and 61 are made of an electrically conductive material
such as, for example, a solder plate attached to upper portion 57
and lower portion 59. Sections 60 and 61 are used to physically and
electrically connect semiconductor package 50 to an integrated
circuit board (not shown) or another semiconductor package (not
shown). Further, sections 60 and 61 are also used to form a space
(not shown) between semiconductor package 50 and another
semiconductor package. The space (not shown) facilitates heat
dissipation. Possible configurations for stacking the semiconductor
packages will be described later below.
Semiconductor package 50 has a semiconductor chip 52 attached to
paddle 51 via an adhesive. A plurality of leads 54 electrically
connect to semiconductor chip 52 through the plurality of wires 53.
Each one of the wires 53 has a first end electrically connected to
a bond pad 56 located on a top surface of semiconductor chip 52 and
a second end connected to lower portion 59 of one of the leads 54.
Wires 53 can be made of any electrically conductive material such
as, for example, gold, aluminum, or silver.
Semiconductor chip 52, paddle 51, wires 53, and leads 54 are all
encapsulated by sealing material 55. Sealing material 55 is
nonconductive and can be thermoplastics or thermoset resins, with
thermoset resins including silicones, phenolics, and epoxies.
Sealing material 55 preserves the spatial relationship between
paddle 51, wires 53, and leads 54 of semiconductor package 50.
Sealing material 55 also protects the components of semiconductor
package 50 from damage. More specifically, except for the small
sections 60 and 61, leads 54 are completely enclosed by sealing
material 55, thus preventing another object from touching and
accidentally shorting leads 54. The exposed parts of the
leadframe--small sections 60, 61, and the bottom surface of paddle
51--are coated or electroplated with a protective material such as,
for example, tin, gold, tin lead, tin bismuth, nickel palladium, or
an alloy thereof.
Referring now to FIG. 3, there is shown a bottom plan view of
semiconductor package 50. As shown in FIG. 3, paddle 51 is located
generally in the middle of semiconductor package 50 and surrounded
by the plurality of leads 54. Only the lower portion 59 of the
leads 54 is visible from this bottom plan-view of semiconductor
package 50.
Referring now to FIG. 4, there is shown a cross-section of
semiconductor package 70, which is another embodiment of the
semiconductor package constructed in accordance with the principles
of the present invention. Semiconductor package 70 is generally
similar to semiconductor package 50 in construction except
semiconductor package 70 has etching portions 71 and 72 on leads
75. Etching portions 71 and 72 are formed near an upper portion 73
and lower portion 74 of each one of the leads 75 of semiconductor
package 70. Etching portions 71 and 72 increase the locking
strength between leads 75 and sealing material 55 to minimize the
possibility of leads 75 from becoming detached from semiconductor
package 70. Etching portions 71 and 72 also help to suppress
movement of leads 75 within semiconductor package 70.
Referring now to FIG. 5, there is shown a cross-section of
semiconductor package 76, which is another embodiment of the
semiconductor package constructed in accordance with the principles
of the present invention. In addition to having all of the
components of semiconductor package 50, semiconductor package 76
has two rows 77 and 78 of leads 75 surrounding semiconductor chip
52 and paddle 51.
Referring now to FIG. 6, there is shown a bottom plan view of
semiconductor package 76. As shown by FIG. 6, rows 77 and 78 have
randomly placed leads 75 surrounding paddle 51.
Referring now to FIGS. 7 and 8 together, there is shown a
cross-section and a bottom plan view of semiconductor package 82,
which is another embodiment of a semiconductor package constructed
in accordance with the principles of the present invention.
Semiconductor package 82 differs from the other embodiments of the
present invention in that the leads 75 in rows 84 and 85, as shown
in FIG. 8, are lined up at regular intervals.
Referring now to FIG. 9, there is shown a cross-section of a
semiconductor package 40 stacked onto the semiconductor package 70
of FIG. 4. Semiconductor package 70 is inverted so that the upper
portion 73 of leads 75 can be attached to a printed circuit board
(not shown) or attached to another semiconductor package of the
present invention (not shown) having leads in generally the same
place as semiconductor package 70. The bottom surface of
semiconductor package 70 is now turned up so that lower portion 74
of leads 75 faces upwards. Semiconductor package 40 is then placed
on top of semiconductor package 70 so that leads 44 of
semiconductor package 40 physically connect and electrically
contact with the lower portion 74 of leads 75 of semiconductor
package 70. Because the lower portion 74 of the leads 75 protrudes
slightly out of semiconductor package 70, the protrusion creates a
space 88. This space 88 allows increased heat dissipation by both
semiconductor package 40 and semiconductor package 70. The
semiconductor packages 40 and 50 are held in this stacked position
by applying solder--or any material commonly used in the
art--between the semiconductor packages and/or between a
semiconductor package and a printed circuit board.
Referring now to FIG. 10, there is shown a cross-section of a prior
art semiconductor package 40 stacked onto semiconductor package 70.
The orientation and physical locations of the semiconductor
packages 40, 70 remain the same as the method already discussed
above. However, a plurality of solder plate layers 200 are attached
to the leads 44 of semiconductor package 40 so that solder plate
layers 200 protrude out of the bottom surface of semiconductor
packages 40. A plurality of solder balls 89 are sandwiched between
solder plate layers 200 and small section 61 of the lower portion
74 of leads 75 of semiconductor package 70. The solder balls 89
create a space 90 between semiconductor package 40 and
semiconductor package 70 for heat dissipation.
Referring now to FIG. 11, there is shown a cross-section of stacked
semiconductor packages constructed in accordance with the
principles of the present invention. A first semiconductor package
70a is attached right side up either to a printed circuit board
(not shown) or to another semiconductor package (not shown)
constructed in accordance with the principles of the present
invention.
Still referring to FIG. 11, semiconductor package 70b also has a
plurality of leads 75b. Each one of the leads 75b also has an upper
portion 73b, and a lower portion 74b. Semiconductor package 70b is
inverted and physically and electrically attached to semiconductor
package 70a. Because semiconductor package 70b is inverted, upper
portion 73b of leads 75b comes into physical and electrical contact
with upper portion 73a of leads 75a of semiconductor package 70a.
Electrical current can flow between semiconductor packages 70a and
70b. Semiconductor packages 70a and 70b are held in this stacked
position by applying solder--or any material commonly used in the
art--between the semiconductor packages and/or between a
semiconductor package and a printed circuit board.
Still referring to FIG. 11, additional semiconductor packages can
be stacked onto semiconductor package 70b by physically and
electrically connecting lower portion 74b of lead 75a to a lower
portion of another semiconductor package having leads in generally
the same places as semiconductor package 70b. As shown in FIG. 11,
heat produced by the electrical activities within semiconductor
packages 70a and 70b can dissipate because paddles 51a and 51b do
not touch. It should be noted that a plurality of solder balls (not
shown) may also be sandwiched between upper portion 73a of lead 75a
of semiconductor package 70a and upper portion 73b of lead 75b of
semiconductor package 70a.
Referring now to FIG. 12, there is shown a cross-section of the
stacked semiconductor packages constructed in accordance with the
principles of the present invention. FIG. 12 shows semiconductor
packages 70a, 70b and 40. The bottom surface of semiconductor
package 70a can be physically and electrically connected to another
semiconductor package (not shown) or to a printed circuit board
(not shown). Semiconductor package 70b is stacked onto and
electrically connected to semiconductor package 70a using the
method and configuration disclosed in FIG. 11 above. Semiconductor
package 40 is stacked on top of and electrically connected to
semiconductor package 70b using the method disclosed in FIG. 10
above. Note spaces 103 and 104 between semiconductor packages 70a,
70b, and 40 allow heat dissipation between the semiconductor
packages.
Referring now to FIG. 13, there is shown a cross-section of stacked
semiconductor packages constructed in accordance with the
principles of the present invention. FIG. 13 shows semiconductor
packages 70a, 70b, and 40. Semiconductor packages 70a, 70b are
stacked on each other using the method shown and described in FIG.
11 above. Semiconductor packages 70b, 40 are stacked on each other
using the method shown and described in FIG. 9 above. Semiconductor
package 70a may be attached either to a printed circuit board (not
shown) or to another semiconductor package (not shown) having leads
located generally in the same place as semiconductor package 70a.
Spaces 103,105 between semiconductor packages 70a, 70b, and 40
allow for heat dissipation.
Referring now to FIG. 14, there is shown a stacked semiconductor
packages 82a, 82b both having a cross section similar to the
embodiment illustrated in FIG. 7. Semiconductor package 82a has a
first series of leads 84a and a second series of leads 85a. Both
first and second series of leads 84a, 85a surround the paddle 51a
and semiconductor chip 52a of semiconductor package 82a. Each lead
in the first and second series of leads 84a, 85a has an upper
portion 118a, a middle portion 119a, and a lower portion 120a.
Still referring to FIG. 14, semiconductor package 82b also has a
first series of leads 84b and a second series of leads 85b. Each
lead in the first and second series of leads 84b, 85b also has an
upper portion 118b, a middle portion 119b, and a lower portion
120b. The first and second series of leads 84b and 85b are arranged
at generally the same location as the first and second series of
leads 84a, 85a of semiconductor package 82a.
Still referring to FIG. 14, semiconductor packages 82a, 82b are
stacked on each other by inverting semiconductor package 82b so
that the upper portion 118b of each lead in the first and second
series of leads 84b, 85b comes into physical contact and is
electrically connected with the lower portion 120a of each lead in
the first and second series of leads 84a, 85a of semiconductor
package 82a. Upper portion 120b of each lead in the first and
second series of leads 84b, 85b in semiconductor package 82b can
either be physically attached to and electrically connected with a
printed circuit board (not shown) or another semiconductor package
(not shown) having leads located generally at the same place as
semiconductor package 82a. A semiconductor package of the present
invention having leads at generally the same place as semiconductor
package 82a can also be attached to semiconductor package 82a.
Thereafter, a semiconductor package 40 (FIG. 1) or another
semiconductor package constructed in accordance with the principles
of the present invention can be stacked onto the entire stack.
Semiconductor packages 82a and 82b are held in their stacked
position by applying solder--or any other material commonly used in
the art--between the semiconductor packages and/or between a
semiconductor package and a printed circuit board.
Still referring to FIG. 14, a space 121 is created when
semiconductor package 82a is physically attached to semiconductor
package 82b. The heat generated by the semiconductor chips 52a, 52b
in semiconductor packages 82a, 82b, respectively, can be dissipated
through space 121. Though not shown, a plurality of solder balls
can be sandwiched between upper portions 118b and the lower
portions 120a.
Referring now to FIGS. 15 through 18, there is shown in side views
a semiconductor in varying stages of manufacture according to a
method for manufacturing the semiconductor packages constructed in
accordance with the principles of the present invention. For
illustrative purposes, the method for manufacturing semiconductor
package 50 (FIG. 2) will be described below. Variations in the
method for manufacturing other embodiments will be noted. To
manufacture semiconductor package 50, a semiconductor chip 52 is
first obtained (FIG. 15). Then, semiconductor chip 52 is attached
to a paddle 51 via an adhesive (FIG. 16). It should be noted that
other types of leadframes of other embodiments of the present
invention may be used. Then, wires 53 are connected from
semiconductor chip 52 to the plurality of leads 54 (FIG. 17). In
FIG. 18, a sealing material 55 encapsulates the leadframe,
semiconductor chip 52, and wires 53 of semiconductor package 50.
Small sections 60, 61 are attached to the upper and lower portions
57, 59 of leads 54. Excess sealing material 55 is trimmed to the
desired shape and length by hand or by using a trimming machine.
Finally, the exposed portions of the leadframe (leads 54 and paddle
51) are coated or electroplated with a corrosion-minimizing
material such as, for example, tin, gold, tin lead, nickel
palladium, tin bismuth, or other similar materials.
Although a preferred embodiment of the method and apparatus of the
present invention has been illustrated in the accompanying Drawings
and described in the foregoing Detailed Description, it will be
understood that the invention is not limited to the embodiment
disclosed, but is capable of numerous rearrangements, modifications
and substitutions without departing from the spirit of the
invention as set forth and defined by the following claims.
The following applications are all being filed on the same date as
the present application and all are incorporated by reference as if
wholly rewritten entirely herein, including any additional matter
incorporated by reference therein:
TABLE-US-00001 Attorney First Named Docket No. Title of Application
Inventor 45475-00015 Semiconductor Package Having Kil Chin Lee
Increased Solder Joint Strength 45475-00016 Clamp and Heat Block
Assembly for Young Suk Chung Wire Bonding a Semiconductor Package
Assembly 45475-00018 Near Chip Size Semiconductor Sean Timothy
Package Crowley 45475-00019 Semiconductor Package Sean Timothy
Crowley 45475-00021 Stackable Semiconductor Package Jun Young Yang
and Method for Manufacturing Same 45475-00024 Method of and
Apparatus for Hyung Ju Lee Manufacturing Semiconductor Packages
45475-00028 Semiconductor Package Having Sung Sik Jang Improved
Adhesiveness and Ground Bonding 45475-00029 Semiconductor Package
Leadframe Young Suk Chung Assembly and Method of Manufacture
It is thus believed that the operation and construction of the
present invention will be apparent from the foregoing description
of the preferred exemplary embodiments. It will be obvious to a
person of ordinary skill in the art that various changes and
modifications may be made herein without departing from the spirit
and the scope of the invention.
* * * * *