U.S. patent number 6,771,134 [Application Number 10/136,474] was granted by the patent office on 2004-08-03 for frequency control for clock generating circuit.
This patent grant is currently assigned to Intel Corporation. Invention is credited to Edward A. Burton, Chee How Lim, Hong-Piao Ma, Greg F. Taylor, Keng L. Wong.
United States Patent |
6,771,134 |
Wong , et al. |
August 3, 2004 |
Frequency control for clock generating circuit
Abstract
A clock generating circuit is provided that includes a plurality
of distributed ring oscillators to drive a clock distribution
network. Multiplexing devices may select a length or delay of each
of the ring oscillators. The variable length or delay may thereby
adjust the frequency of the clock generating circuit.
Inventors: |
Wong; Keng L. (Portland,
OR), Ma; Hong-Piao (Portland, OR), Taylor; Greg F.
(Portland, OR), Lim; Chee How (Hillsboro, OR), Burton;
Edward A. (Hillsboro, OR) |
Assignee: |
Intel Corporation (Santa Clara,
CA)
|
Family
ID: |
29268949 |
Appl.
No.: |
10/136,474 |
Filed: |
May 2, 2002 |
Current U.S.
Class: |
331/57; 327/159;
331/34 |
Current CPC
Class: |
G06F
1/08 (20130101); G06F 1/10 (20130101); H03L
7/0995 (20130101); H03L 7/18 (20130101) |
Current International
Class: |
G06F
1/08 (20060101); G06F 1/10 (20060101); H03L
7/08 (20060101); H03L 7/099 (20060101); H03L
7/18 (20060101); H03L 7/16 (20060101); H03B
027/00 () |
Field of
Search: |
;331/57,1A,17,34
;327/150,156-159,564,565,293,295,296,297 ;326/93 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
Gyu Moon et al., "A New GHZ CMOS Cellular Oscillator Network", 1998
IEEE, pp. II-89-92..
|
Primary Examiner: Callahan; Timothy P.
Assistant Examiner: Luu; An T.
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor &
Zafman LLP
Claims
What is claimed is:
1. A clock generating circuit comprising at least one oscillator to
drive a clock distribution network, the at least one oscillator
including a first device to adjust a frequency of the at least one
oscillator, the at least one oscillator further including a second
device to select between a synchronous mode to drive the clock
distribution network and an asynchronous mode to drive the clock
distribution network.
2. The circuit of claim 1, wherein the first device comprises a
multiplexing device to adjust a length of the at least one
oscillator.
3. The circuit of claim 2, further comprising a digital control
circuit to apply a select signal to the multiplexing device.
4. The circuit of claim 3, wherein the select signal is further
based on a reference frequency.
5. The circuit of claim 2, wherein the at least one oscillator
includes a first set of inversion circuits having a first length
and a second set of inversion circuits having a second length.
6. The circuit of claim 5, wherein the multiplexing device selects
between the first set of inversion circuits and the second set of
inversion circuits.
7. The circuit of claim 6, wherein the first set of inversion
circuits includes inversion circuits from the second set of
inversion circuits.
8. The circuit of claim 5, further comprising a plurality of load
circuits to apply loads to at least some of the inversion
circuits.
9. The circuit of claim 1, wherein in the synchronous mode, the
clock distribution network is driven based on-a signal output from
a phase lock loop circuit and in the asynchronous mode, the clock
distribution network is driven based on the at least one
oscillator.
10. The circuit of claim 1, wherein the clock generating circuit is
provided within a core of an integrated circuit.
11. A circuit comprising: a clock distribution network; and at
least one variable-length ring oscillator coupled to the clock
distribution network, wherein in a synchronous mode, the clock
distribution network is driven based on a signal output from a
phase lock loop circuit and in an asynchronous mode, the clock
distribution network is driven based on a plurality of
variable-length oscillators.
12. The circuit of claim 11, wherein the at least one
variable-length ring oscillator comprises a device to select a
length of the oscillator.
13. The circuit of claim 12, wherein the device comprises a
multiplexing device.
14. The circuit of claim 13, further comprising a digital control
circuit to apply a select signal to the multiplexing device.
15. The circuit of claim 14, wherein the select signal is further
based on a reference frequency.
16. The circuit of claim 11, wherein the at least one
variable-length ring oscillator includes a first set of inversion
circuits having a first length and a second set of inversion
circuits having a second length.
17. The circuit of claim 16, wherein a selecting device selects
between the first set of inversion circuits and the second set of
inversion circuits.
18. The circuit of claim 16, wherein the first set of inversion
circuits includes inversion circuits from the second set of
inversion circuits.
19. The circuit of claim 11, wherein the at least one
variable-length ring oscillator includes a plurality of load
circuits to apply loads to the oscillator.
20. The circuit of claim 11, wherein the circuit is provided within
a core of an integrated circuit.
21. The circuit of claim 11, further comprising a latch element to
receive a clock signal from the clock distribution network.
22. A circuit comprising: a clock distribution network; at least
one oscillator coupled to the clock distribution network, the at
least one oscillator including a first device to select a delay of
the at least one oscillator, the at least one oscillator further
including a second device to select between a synchronous mode to
drive the clock distribution network and an asynchronous mode to
drive the clock distribution network; and an element to receive a
clock signal from the clock distribution network.
23. The circuit of claim 22, wherein the first device comprises a
multiplexing device.
24. The circuit of claim 23, further comprising a digital control
circuit to apply a select signal to the multiplexing device.
25. The circuit of claim 24, wherein the select signal is based on
a reference frequency.
26. A method of generating a clock signal comprising: driving the
clock distribution network using at least one ring oscillator
circuit; adjusting a frequency of the at least one ring oscillator
circuit; and selecting between a synchronous mode to drive the
clock distribution network and an asynchronous mode to drive the
clock distribution network.
27. The method of claim 26, wherein adjusting the frequency of the
at least one ring oscillator circuit comprises adjusting a length
of the at least one ring oscillator circuit.
28. The method of claim 27, wherein the adjusting is based on a
reference frequency.
29. The method of claim 26, wherein adjusting the frequency of the
at least one ring oscillator circuit comprises adjusting a delay of
the at least one ring oscillator circuit.
Description
FIELD
The present invention relates generally to microprocessor circuits,
and more specifically to internal clocks in microprocessor
circuits.
BACKGROUND
Electronic devices, such as microprocessors, are steadily operating
at faster and faster speeds. As microprocessors run at higher and
higher speeds, the power delivered to the microprocessors by a
power supply starts to become an issue. Voltage drops (or droops)
may occur as power is delivered from a power source to individual
components and devices on the die of a microprocessor. For example,
devices on a die may receive only 1.0 volt from a power source that
is supplying 1.2 volts due to a voltage droop. Decoupling
capacitors may be used on a die to help reduce voltage droop.
However, decoupling capacitors cost area on the die and also cost
power due to gate oxide leakage.
Power source voltage droops affect the speed at which an electronic
device (e.g., microprocessor or integrated circuit) may operate.
During normal operation of a microprocessor (or any sequential
machine), noise may be generated from instantaneous switching.
Voltage supply noise modulates the delay of data paths. Voltage
droops reduce the maximum frequency of operation of the
microprocessor. For example, as a voltage droop magnitude
increases, the operating frequency of the microprocessor decreases.
Thus, a large change in processor activity may cause substantial
supply voltage transients resulting in performance loss.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and a better understanding of the present invention
will become apparent from the following detailed description of
example embodiments and the claims when read in connection with the
accompanying drawings, all forming a part of the disclosure of this
invention. While the foregoing and following written and
illustrated disclosure focuses on disclosing example arrangements
and embodiments of the invention, it should be clearly understood
that the same is by way of illustration and example only and that
the arrangements and embodiments are not limited thereto.
The following represents brief descriptions of the drawings in
which like reference numerals represent like elements and
wherein:
FIG. 1 is a block diagram of an integrated circuit according to one
arrangement;
FIG. 2 is a schematic diagram of a clock distribution network
according to one arrangement;
FIG. 3 is a diagram of one stage of a clock distribution network
according to one arrangement;
FIG. 4 is a block diagram of a clock generating circuit according
to an example embodiment of the present invention;
FIG. 5 is a diagram of a clock generating circuit according to an
example embodiment of the present invention;
FIG. 6 is a diagram showing the clock generating circuit of FIG. 5
along with elements to be clocked according to an example
embodiment of the present invention;
FIG. 7 is a diagram of a clock generating circuit according to an
example embodiment of the present invention;
FIG. 8 is a diagram of a clock generating circuit according to an
example embodiment of the present invention;
FIG. 9 is a diagram of a clock generating circuit according to an
example embodiment of the present invention;
FIG. 10 is a diagram of a start/stop circuit according to an
example embodiment of the present invention;
FIG. 11 is a graph showing a Vcc voltage signal that varies due to
noise;
FIG. 12 is a diagram showing a clock generating circuit according
to an example embodiment of the present invention;
FIG. 13 is a diagram showing a clock generating circuit according
to an example embodiment of the present invention;
FIG. 14 is a diagram showing a clock generating circuit according
to an example embodiment of the present invention; and
FIG. 15 is a diagram showing a closed loop methodology for digital
frequency control according to an example embodiment of the present
invention.
DETAILED DESCRIPTION
In the following detailed description, like reference numerals and
characters may be used to designate identical, corresponding or
similar components in differing figure drawings. Further, in the
detailed description to follow, example values may be given,
although embodiments of the present invention are not limited to
the same. While values may be described as HIGH or LOW, these
descriptions of HIGH and LOW are intended to be relative to the
discussed arrangement and/or embodiment. That is, a value may be
described as HIGH in one arrangement although it may be LOW if
provided in another arrangement. Arrangements and embodiments may
be shown in block diagram form in order to avoid obscuring the
invention, and also in view of the fact that specifics with respect
to implementation of such block diagram arrangements and
embodiments may be highly dependent upon the platform within which
the present invention is to be implemented. That is, such specifics
should be well within the purview of one skilled in the art. Where
specific details (e.g., circuits) are set forth in order to
describe example embodiments of the invention, it should be
apparent to one skilled in the art that the invention can be
practiced without, or with variation of, these specific details. It
should also be apparent that differing combinations of hard-wired
circuitry may be used to implement embodiments of the present
invention. That is, embodiments of the present invention are not
limited to any specific combination of hardware.
Embodiments of the present invention may also be described with
respect to signals being input or output from different circuit
components. It is understood that while the discussion identifies a
signal, the signal may be transmitted over a signal line or similar
type of mechanism. Further, the terminology signal may also
correspond to a signal line as shown in the drawings. Well-known
power/ground and address connections to components may not be shown
within the figures for simplicity of illustration and discussion,
and so as not to obscure the invention.
While the following discussion may be presented with respect to
implementation in a microprocessor, embodiments of the present
invention are not limited to that specific implementation.
Implementations for generating clock signals for various digital
devices such as integrated circuits, discrete logic devices, memory
devices, devices either on the same or separate chips,
communications devices, etc., are also within the scope of the
present invention.
In order to better describe embodiments of the present invention
being pursued in the present patent application, various
embodiments and arrangements may initially be described. These
initial embodiments may be pursued in related U.S. Patent
Application No. (Attorney Docket No. 219.41237X00), filed
simultaneously with this application.
Embodiments of the present invention may provide a circuit that
includes a clock distribution network and a multiplexing device
coupled to the clock distribution network to select between a
synchronous mode and an asynchronous mode. A plurality of
distributed ring oscillators may asynchronously drive the clock
distribution network in the asynchronous mode. The distributed ring
oscillators may be coupled to a power supply such that they track
the critical paths. A phase lock loop circuit (located external to
the core circuit) may synchronously drive the clock distribution
network in the synchronous mode. In the following discussion, the
terminology asynchronously driving the clock distribution network
may be used with reference to the asynchronous mode. In the
asynchronous mode, the clock distribution network may be driven
asynchronously relative to an external clock. The clock
distribution network may be synchronously driven although it is
asynchronous with respect to an external clock.
Embodiments of the present invention may thereby provide power
supply control on a microprocessor. This allows performance to be
recovered since the performance may be dependent on the average
power supply level rather than minimizing power supply droop. The
core clock frequency may instantaneously track the worst-case
speedpath over Vcc noise. The instantaneous performance of the
processor core may vary over time in response to Vcc transient.
FIG. 1 is a block diagram of an integrated circuit according to one
arrangement. Other arrangements are also possible. More
specifically, FIG. 1 shows an integrated circuit 100 having a core
101, an interface 105, and a clock generator 102. The core 101 may
include circuitry and logic to perform the designated functions of
the integrated circuit, while the interface 105 may provide an
interface between the core 101 and the remainder of the system and
its system bus(es). For instance, if the integrated circuit 100
includes a processor, the core 101 may include one or more
decoders, scheduling logic, execution units, reorder buffers,
memory order buffers, register files, cache memory, etc., for use
in executing instructions. The interface 105 may include external
bus controller logic and programmable interrupt controller
logic.
The clock generator 102 may generate the clock signals in response
to a system clock signal 110. The clock generator 102 may include a
phase lock loop (PLL) circuit. The clock signals may be coupled to
the core 101 and the interface 105. The clock generator 102 may
generate the bus clock signal(s) 103 and the core clock signal(s)
104.
FIG. 2 illustrates a clock distribution network 200 according to
one arrangement. Other arrangements are also possible. The clock
distribution network 200 distributes a clock signal to chip
components such as the core 101 (shown in FIG. 1). As illustrated,
a feedback clock signal and a reference clock signal may be applied
to a PLL 210, which may be provided within the clock generator 102.
The clock distribution network 200 may include a plurality of
drivers 220, 230, 240, 250, 260, 270 and 280 to drive large
capacitances, such as attributable to registers and latches, with
the output signal of the voltage-controlled oscillator of the phase
lock loop (PLL). The drivers 220, 230, 240, 250, 260, 270 and 280
may contain inverters (not shown). Hence, the capacitances may be
switched at the clock frequency. The capacitances 265, 275, 285,
290, 295 and 255 may be the capacitances attributable to the
components of the chip. In addition to these capacitances, the gate
capacitances of the driver inverters may also be switched at the
clock frequency. If the total capacitance for the clock network is
represented as C and the clock network switches at the clock
frequency, f, the amount of power dissipated may be represented as
CV.sup.2 f, where V is the supply voltage. This amount of power may
be a significant portion of the total power utilized by the chip
due to a relatively large C and a relatively high f.
FIG. 3 is a diagram of one stage of a clock distribution network
according to one arrangement. Other arrangements are also possible.
More specifically, FIG. 3 shows one stage of a clock distribution
network 300 that may be provided within the core 101 (FIG. 1). FIG.
3 shows the terminal stage with multiple drivers driving a common
and continuous grid. The clock distribution network 300 may also be
provided within other entities. The core clock distribution network
300 may include signal traces 310 (shown vertically in the drawing
figure) and signal traces 320 (shown horizontally in the drawing
figure). The core clock distribution network 300 may also include a
plurality of drivers coupled to the signal traces 310 and 320. For
ease of illustration, only a first driver 330 is labeled in FIG. 3.
The drivers operate to provide clock signals (such as core clock
signals) to the clock distribution network 300 and thereby provide
clock signals to respective elements (such as latches and
registers) of the core 101 (not shown in FIG. 3).
FIG. 4 is a block diagram of a clock generating circuit according
to an example embodiment of the present invention. Other
embodiments and configurations are also within the scope of the
present invention. In this embodiment, the clock generating circuit
may be provided within the core 101 although the clock generating
circuit may also be located in other locations that include a clock
distribution network. More specifically, FIG. 4 shows a clock
generating circuit 400 coupled between a first signal trace 312 and
a second signal trace 322. The first signal trace 312 may be one of
the signal traces 310 and the second signal trace 322 may be one of
the signal traces 320. However, embodiments of the present
invention are also applicable to the signal trace 312 and the
signal trace 322 being configured into a clock distribution network
different from the clock distribution network shown in FIG. 3. FIG.
4 only shows one clock generating circuit although the plurality of
clock generating circuits may be distributed throughout the clock
distribution network.
FIG. 4 also shows a power supply (or power supply device) 350
provided external to the core 101, such as in a periphery (i.e.,
the I/O) of the integrated circuit about the core 101 (FIG. 1). The
power supply 350 may be coupled by a power distribution network 355
to the clock generating circuit 400. Although not shown in FIG. 4,
a plurality of clock generating circuits 400 may be provided about
the clock distribution network in a similar manner as each of the
drivers provided about the clock distribution network 300 in FIG.
3. In other words, the clock distribution network may include a
plurality of clock generating circuits 400 each coupled between
signal traces and each powered by the power supply 350 through the
power distribution network 355.
FIG. 5 is a diagram of a clock distribution circuit according to an
example embodiment. FIG. 5 shows more specific circuit elements
(such as inverter circuits and a multiplexing device) each of which
may be powered by the power supply 350 coupled via the power
distribution network 355. As shown, a plurality of inverter
circuits 410, 420, 440, 450 and 460 and a multiplexing device 430
(or selecting device) may be coupled as a ring oscillator (or ring
oscillator circuit) between the signal trace 312 and the signal
trace 322. That is, the inverter circuit 410 receives a signal from
the signal trace 322. The signal propagates through the inverter
circuit 420, through the multiplexing device 430, through the
inverter circuits 440, 450 and 460 and is output to the signal
trace 312 from the last stage of the ring oscillator (such as the
inverter circuit 460). In other words, the input signal to the ring
oscillator and the output signal of the ring oscillator are to the
clock distribution network.
FIG. 5 shows five stages of a ring oscillator circuit coupled
between signal traces. The ring oscillator circuit may include any
odd number of stages so as to produce an oscillating circuit
between signal traces. That is, while FIG. 5 shows five inverter
circuits, embodiments of the present application are also
applicable to other numbers of inverter circuits coupled in series
so as to produce a ring oscillator circuit. Furthermore, circuit
elements other than inverter circuits may also be used to form the
ring oscillator.
The multiplexing device (or selecting device) 430 is coupled
between the inverter circuit 420 and the inverter circuit 440. The
multiplexing device 430 selects between inputs on a signal line 432
and a signal line 434. The multiplexing device 430 may receive an
input signal on the signal line 434 from the inverter circuit 420.
The multiplexing device 430 may receive input signals on the signal
line 432 from a phase lock loop (PLL) circuit provided external to
the core 101, for example. That is, the phase lock loop circuit may
provide a clock signal along the signal line 432 to the
multiplexing device 430.
The multiplexing device 430 may receive a select signal to select
between an asynchronous mode and a synchronous mode. In the
synchronous mode, the clock signal on the signal line 432 passes
through the multiplexing device 430, and subsequently passes
through the inverter circuits 440, 450 and 460. The resulting
signal is output to the signal trace 312 (i.e., the clock
distributing network). This thereby results in the clock
distribution network operating based on a synchronous signal
provided by the PLL located external to the core 101. On the other
hand, the multiplexing device 430 may operate in the asynchronous
mode based on the select signal. In the asynchronous mode, the
signal on the signal line 434 (from the inverter circuit 420)
passes through the multiplexing device 430 and subsequently passes
through the inverter circuits 440, 450 and 460. The resulting
signal is output to the signal trace 312 (i.e., the clock
distribution network). The signal may also propagate back along the
signal trace 322 to the inverter circuits 410 and 420 and be
subsequently passed through the multiplexing device 430 since the
multiplexing device 430 is still operating in the asynchronous
mode. Accordingly, the select signal applied to the multiplexing
device 430 may operate the clock generating circuit in either a
synchronous mode or an asynchronous mode. Although not shown in
FIG. 5, each of the clock generating circuits provided about the
clock distribution network may include elements (such as inverter
circuits and multiplexing devices) similar to the elements shown in
FIG. 5. Each of the respective multiplexing devices may separately
receive a similar select signal so as to provide the appropriate
mode for the entire clock distribution network.
The multiplexing device 430 may be considered part of the ring
oscillator. The multiplexing device 430 may be a pass-through
element, which makes it logically passive for the loop. However,
the multiplexing device 430 may contribute to delay (and therefore
period) and Vcc sensitively of the delay of the loop.
FIG. 6 is a diagram showing the clock generating circuit of FIG. 5
along with elements to be clocked according to an example
embodiment of the present invention. Other embodiments and
configurations are also within the scope of the present invention.
For ease of illustration, FIG. 6 only shows two clock generating
circuits, namely a first clock generating circuit (in which the
components are labeled A) and a second clock generating circuit (in
which the components are labeled B). Both the first clock
generating circuit and the second clock generating circuit may be
similar to the clock generating circuit shown in FIG. 5 although
other embodiments for a clock generating circuit are also within
the scope of the present invention.
More specifically, the first clock generating circuit includes
inverter circuits 410A, 420A, 440A, 450A and 460A as well as a
multiplexing device 430A. Similarly, the second clock generating
circuit includes inverter circuits 410B, 420B, 440B, 450B and 460B
as well as a multiplexing device 430B. The first clock generating
circuit may be coupled between the signal trace 312 and the signal
trace 322. The second clock generating device may be coupled
between a signal trace 314 (such as one of the signal traces 310)
and the signal trace 322. FIG. 6 shows elements of the core 101
such as a D flip-flop circuit 510, logic 520 and a D flip-flop
circuit 530. The D flip-flop circuits 510 and 530 may be clocked by
the clock distribution network, such as clock signals on the signal
trace 322. The logic 520 may include any type of latch, mechanism
or state machine to perform a desired function in the core 101.
FIG. 7 is a diagram of a clock generating circuit according to an
example embodiment of the present invention. Other embodiments and
configurations are also within the scope of the present invention.
In this embodiment, portions of the ring oscillator may be shared
between a first clock generating circuit and a second clock
generating circuit. More specifically, the inverter circuits 410
and 420 may be commonly used for both a first clock generating
circuit (formed by at least the inverter circuits 440A, 450A and
460A) and a second clock generating circuit (formed by at least
inverter circuits 440C, 450C and 460C). For ease of illustration,
the multiplexing device for use in the ring oscillator is not shown
in FIG. 7 although the multiplexing device may be provided after
the inverter circuit 420 in one embodiment. The first clock
generating circuit may output a clock signal on the signal trace
312 and the second clock generating circuit may output a clock
signal on the signal trace 312.
FIG. 8 is a diagram of a clock generating circuit according to
another example embodiment of the present invention. Other
embodiments and configurations are also within the scope of the
present invention. In this embodiment, elements of the ring
oscillator may be shared between clock generating circuits. In this
embodiment, adjacent ring oscillators may be "horizontally" coupled
to share elements such as inverter circuits. For example, each of
inverter circuits 502, 504, 506, 508 and 510 are shared between
adjacent ring oscillators. This may help reduce wire delays. The
clock signals may be output from the last stage of each ring
oscillator circuit to a signal trace such as the signal trace 322.
In this example, inverter circuits 512, 514, 516, 518 and 520 are
the last stage of each ring oscillator. Although not shown in FIG.
8, multiplexing devices may be provided prior to the last inverter
circuit of each ring oscillator circuit.
FIG. 9 is a diagram of a clock generating circuit according to
another example embodiment of the present invention. Other
embodiments and configurations are also within the scope of the
present invention. In this embodiment, elements of the ring
oscillators may be shared between clock generating circuits. In
this embodiment, adjacent ring oscillators may be "horizontally"
coupled to share elements. Ring oscillators may also be
"vertically" coupled to share elements. The clock signals may be
output from the last stage of the ring oscillator circuits to
different signal traces. In this example, inverter circuits 542,
544, 546 and 548 are the last stage of each ring oscillator.
Although not shown in FIG. 9, multiplexing devices may be provided
prior to the last inverter circuit of each ring oscillator
circuit.
As discussed above, the synchronous mode's signal may originate
from a phase lock loop circuit located external from the core and
be distributed within the clock distribution network. On the other
hand, the asynchronous mode's signal may originate from itself. In
a stopped state, all the ring oscillators may be de-asserted by an
enable signal to one of the oscillator stages, which may be a NAND
gate, for example. When an enable input is asserted high, then
oscillation may begin. The enable signal to all the oscillators may
be asserted simultaneously to start all the oscillators
together.
More specifically, FIG. 10 shows a start/stop circuit according to
an example embodiment of the present invention. Other embodiments
and configurations are also within the scope of the present
invention. The start/stop circuit operates to start driving the
clock distribution network and to stop driving the clock
distribution network. FIG. 10 shows a multiplexing device 610 to
select between a synchronous mode and an asynchronous mode based on
a synchronous/asynchronous select signal, which is also used as the
select signal for the multiplexing device of each of the ring
oscillator circuits. FIG. 10 also shows portions of the clock
distribution network 620 (such as respective signal traces) coupled
to inputs of NAND gates 640, 650 and 660. Other inputs to the NAND
gates 640, 650 and 660 may be from signal lines between stages of
each ring oscillator circuit. The output of each of the NAND gates
640, 650 and 660 is to one input of the multiplexing device (such
as the multiplexing device 430) of each ring oscillator circuit.
Accordingly, the circuit shown in FIG. 10 provides start/stop
capabilities in the asynchronous mode.
In the synchronous mode, the PLL may drive the clock distribution
network, and the core clock. When the asynchronous mode is
selected, then the clock distribution network may be driven by the
asynchronous start signal (shown as async_start), which is
initially low and thus the core clock may be stopped. The
async_start signal may be asserted to start the asynchronous mode
oscillator. Since this signal travels down the clock distribution
network, a simultaneous start may occur. This may be the same for
subsequent stops/starts.
FIG. 11 is a graph showing the Vcc voltage signal on a die. As
shown, the Vcc signal may vary due to reasons such as noise. The
noise may impart Vcc modulation with peaks and valleys. FIG. 11
also shows a minimum Vcc(t) value that is located at a value no
greater than the largest valley of the Vcc signal. In this
arrangement, the frequency of the core would be at the lowest Vcc
droop. Embodiments of the present invention allow the die to
operate at an average Vcc(t) value. That is, the frequency of the
core may track Vcc instantaneously. As clearly shown in FIG. 11,
the average Vcc(t) value is higher than the minimum Vcc(t) value.
This allows the performance to be based on the average power supply
level rather than the minimum power supply level. This also reduces
the need to minimize the power supply droop as in disadvantageous
and costly arrangements.
Embodiments of the present invention have been described with
regard to a method and apparatus to couple a core frequency to an
instantaneous power supply such that the core frequency tracks the
power supply (Vcc) to maintain functionality of the core logic in
the face of severe supply noise. Embodiments of the present
invention may include distributed oscillators to drive a common
clock distribution network. The distributed oscillators may filter
out the uncorrelated noise and respond to global supply noise.
Embodiments of the present invention may further provide an
asynchronous core I/O interface flexible enough to allow a wide
range of instantaneous frequency ratios between the core and the
I/O. An I/O ring around the core may run on a phase lock loop
circuit synchronizing the I/O to the external world and thereby
presenting a synchronous interface to the outside. An internal core
phase lock loop circuit may drive the internal core clock in a
synchronous mode to facilitate testing.
Embodiments of the present invention may provide a clock
distribution network driven by a regular array of identical
oscillators. This uniform structure may ensure that all the
oscillators toggle simultaneously to produce a clock that reaches
any point on the die at a coherent frequency with minimal skew
between points. Each oscillator may include a ring oscillator made
out of an odd number of inversion stages. These stages may be CMOS
technology so that the elements of the ring oscillator track the
power supply and temperature in the same fashion as the core
datapath logic. The ring oscillator length may also be adjustable.
The ring oscillator may be adjusted to a length that produces a
period just long enough to ensure functionality of the worst-case
core speedpath under any power supply and temperature condition. As
Vcc-Vss increases, the worst speedpath may need less time to
evaluate, and the oscillator frequency may proportionately increase
to keep track. On the other hand, as Vcc-Vss decreases, the worst
speedpath may require more evaluation time and that increases in
time may be provided by the slower oscillator frequency. As a
result, the instantaneous oscillator frequency may track the worst
speedpath, thus ensuring functionality over any (voltage,
temperature) condition. Some amount of margin may counter any
locally uncorrected noise in voltage and temperature.
One alternate mode may employ the PLL as a clock source. This
allows testing of the microprocessor in the traditional synchronous
mode, in which machine behavior is predictable on a cycle-by-cycle
basis.
The preceding arrangements and embodiments have been described in
U.S. Patent Application (Attorney Docket No. 219.41237X00), filed
simultaneously with this application. The following embodiments may
be pursued in this patent application, although these embodiments
are also applicable and combinable with the embodiments and
features described above.
As discussed above, a free-running oscillator may be used to run
the microprocessor core and may extract a maximum performance.
However, a microprocessor having a rated frequency may be more
marketable. Thus, while the instantaneous frequency may be allowed
to wander while the processor tracks the power supply noise, a
microprocessor may also have a rated average frequency that
reflects its average performance.
Embodiments of the present invention may allow an asynchronous core
to be frequency governed to a constant average frequency and
thereby run at a constant (i.e., unthrottled) performance. This may
allow speed grading of parts during manufacturing. This may also
allow continuous binning in which the bin size is arbitrary. This
differs from disadvantageous arrangements in which the bin size may
be limited by fixed bus ratio steps as allowed by a PLL circuit.
Furthermore, a spread spectrum may be imparted on the oscillator by
introducing a suitable modulation.
As discussed above, especially with respect FIGS. 4 and 5, a
regular clock distribution network may be driven by a regular array
of identical oscillators. Each oscillator may include a ring
oscillator made out of an odd number of inversion stages. These
stages may be CMOS technology so that the elements track power
supply and temperature in the same fashion as the core datapath
logic.
In accordance with embodiments of the present invention, the length
of each of the ring oscillators may be adjustable. That is, the
ring oscillator length may be adjusted to a length that produces a
period long enough to ensure functionality of the worst case core
speedpath under any power supply and temperature condition. In
order to provide the extra margin, the length of the oscillator may
be extra long. Additionally, fine adjustment (or fine tuning) may
be made to either the drive strength or loading of one or more
stages of the oscillator.
A digital frequency lock loop (DFLL) circuit may be used to lock
the core frequency to a desired bus-to-core frequency ratio. The
DFLL may count the internal core clock and attempt to guide the
internal core frequency to a long-term lock point that is a
predetermined ratio with respect to the external frequency. This
can be accomplished in a course fashion by alternating between n
and n+2 stages for each ring oscillator, where n is an odd number.
By changing the duty cycle of staying in n vs n+2 mode, an accurate
long-term frequency may be achieved.
The DFLL may be a logic circuit that takes a comparator output
(between the core frequency divided by N versus the reference
frequency). The result of the comparison may then be low-pass
filtered through digital averaging means, over a plurality of
cycles. More specifically, the low-pass filter time constant may be
set to be slower than the slowest droop time constant, which may be
the third droop. The average core frequency when locked may be N
times the reference frequency, where N is a real positive number.
The DFLL may include a frequency comparator, a digital control
circuit and oscillators with speed select. The DFLL may be
physically located on the die.
FIG. 12 is a diagram of a clock generating circuit 700 according to
an example embodiment of the present invention. Other embodiments
and configurations are also within the scope of the present
invention. The clock generating circuit 700 shown in FIG. 12 may
correspond to the clock generating circuit 400 (shown in FIG. 4)
and/or may be used in correspondence with each of the arrangements
and/or embodiments shown in FIGS. 5-10. Although not shown in FIG.
12, a plurality of clock generating circuits 700 may be provided
about the clock distribution network in a similar manner as each of
the drivers provided about the clock distribution network shown in
FIG. 3.
FIG. 12 shows that the clock generating circuit 700 includes the
multiplexing device 430 and the inverter circuits 440, 450 and 460
coupled to the signal trace 312 in a similar manner as in FIG. 5.
FIG. 12 additionally shows that the clock generating circuit 700
includes inverter circuits 702, 704, 706, 708, 710 and 712 coupled
in series from the signal trace 322. The clock generating circuit
700 also includes a multiplexing device 750. Accordingly, the clock
generating circuit shown in FIG. 12 may include a plurality of
inverter circuits as well as a plurality of multiplexing
devices.
In similar manner as discussed above with respect to FIG. 5, the
multiplexing device 430 may receive input signals on the signal
line 432 from a PLL circuit provided external to the core 101, for
example. That is, the PLL circuit may provide a clock signal along
the signal line 432 to the multiplexing device 430. The
multiplexing device 430 may also receive input signals on the
signal line 434 from the multiplexing device 750 as will be
described.
The multiplexing device 750 may receive input signals along each of
signal lines 705, 709 and 713. For example, the inverter circuit
704 outputs the signals that are input to the multiplexing device
750 along the signal line 705. Similarly, the inverter circuit 708
outputs the signals that are input to the multiplexing device 750
along the signal line 709 and the inverter circuit 712 outputs the
signals that are input to the multiplexing device 750 along the
signal line 713.
The multiplexing device 750 may receive a select signal from a
digital control circuit such as a digital frequency lock loop
(DFLL) circuit 800. The select signal selects one of the inputs of
the multiplexing device 750 and allows signals on the selected
signal line to pass through the multiplexing device 750. The signal
passing through the multiplexing device 750 passes along the signal
line 434 to one input of the multiplexing device 430.
Similar to that discussed above with respect to FIG. 5, the
multiplexing device 430 may also receive a select signal to select
between an asynchronous mode and a synchronous mode. That is, the
select signal input to the multiplexing device 430 selects one of
the inputs of the multiplexing device 430 (such as from the PLL on
signal line 432 or the asynchronous mode signal on the signal line
434) and allows signals on the selected one of the signal lines 432
or 434 to pass through the multiplexing device 430 to the inverter
circuit 440.
The clock generating circuit 700 allows the digital control circuit
(provided within the DFLL circuit 800) to select a length of each
ring oscillator. For example, if the DFLL circuit 800 desires a
short ring oscillator, then the select signal applied to the
multiplexing device 750 may select the signal line 705 so that the
signal passes through the multiplexing device 750 to the
multiplexing device 430. That is, the signal that passes from the
signal trace 322 and through the inverter circuits 702 and 704 may
be input to the multiplexing device 750. On the other hand, if the
DFLL circuit 800 desires a longer ring oscillator, then the select
signal applied to the multiplexing device 750 may select the signal
line 709 so that the signal passes through the multiplexing device
750. If the DFLL circuit 800 desires an even further ring
oscillator, then the select signal applied to the multiplexing
device 750 may select the signal line 713 so that the signal passes
along the signal line 713 and through the multiplexing device
750.
FIG. 13 is a diagram of a clock generating circuit according to
another example embodiment of the present invention. Other
embodiments and configurations are also within the scope of the
present invention. The clock generating circuit shown in FIG. 13
closely corresponds to the clock generating circuit 700 shown in
FIG. 12. Thus, similar features between FIG. 12 and FIG. 13 may not
be discussed.
FIG. 13 shows that the clock generating circuit includes a
multiplexing device 760 and a multiplexing device 770. The
multiplexing device 770 may receive input signals on a signal line
772 from a PLL circuit provided external to the core 101, for
example. That is, the PLL circuit may provide a clock signal along
the signal line 772 to the multiplexing device 770. The
multiplexing device 770 may also receive input signals along each
of signal lines 709 and 713. The inverter circuit 708 outputs the
signals that are input to the multiplexing device 770 along the
signal line 709. The inverter circuit 712 outputs the signals that
are input to the multiplexing device 770 along the signal line 713.
The inverter circuit 704 outputs the signals that are input to the
multiplexing device 760 along the signal line 705.
The multiplexing device 770 may receive a select signal(s) to
select one of the inputs of the multiplexing device 770 and allows
signals on the selected signal line to pass through the
multiplexing device 770. The signal passing through the
multiplexing device 770 passes along the signal line 762 to one
input of the multiplexing device 760.
The multiplexing device 760 may also receive a select signal to
select one of the inputs of the multiplexing device 760 and allow
signals on the selected one of the signal lines 762 and 705 to pass
through the multiplexing device 760 to the inverter circuit
440.
The digital control circuit provided within the DFLL 800 may select
a length of each ring oscillator. That is, the digital control
circuit may appropriately apply the select signals to the
multiplexing devices 770 and 760 to obtain a desired length (or
delay) for each ring oscillator.
Several techniques may be used to affect fine delay control. One
such method is to couple a passgate (e.g. latch or flip-flop
circuit) in series with a capacitor load to each inverter circuit.
When the passgate is turned on, the capacitor may be presented to
the inverter circuit, and the inverter stage may be slowed down. On
the other hand, when the passgate is turned off, the capacitor is
not seen by the inverter circuit, and the inverter circuit delay
may become faster. FIG. 14 shows one example embodiment of this
fine delay circuit.
More specifically, FIG. 14 shows an example of a clock generating
circuit according to another example embodiment of the present
invention. Other embodiments and configurations are also within the
scope of the present invention. FIG. 14 shows load circuits 784,
788, 792 and 796 that are coupled subsequently to each of the
inverter circuits 782, 786, 790 and 794, respectively. The load
circuits 782, 788, 792 and 796 may be arrays of passgate-capacitor
loads, for example. Each inverter stage may be loaded by the array
of passgate-capacitor loads, thereby affecting super-fine delay
control. For the four load circuits 784, 786, 792 and 796 shown in
FIG. 14, if each stage has four passgate-capacitor loads, then the
clock generating circuit has sixteen (4.times.4) fine delay steps.
Other numbers of load circuits and passgate-capacitor loads are
also within the scope of the present invention. The DFLL (not shown
in FIG. 14) may be coupled to the load circuits 784, 786, 792 and
796 to apply the fine delay control.
FIG. 15 shows an example of a DFLL circuit that uses a closed loop
to adjust the frequency of the ring oscillator circuits according
to an example embodiment of the present invention. Other
embodiments and configurations are also within the scope of the
present invention. More specifically, FIG. 15 shows that an
external clock (or system clock) may be input to the core (such as
the core 101) and be input to a comparator 810 (such as a frequency
comparator). Another input of the comparator 810 may be a signal
based on the core clock signals (output from the ring oscillator
circuits) that passes through the divide by N circuit 830. The
comparator 810 outputs a signal to the DFLL controller 820, which
operates to appropriately apply select signals to the ring
oscillator circuits (shown as VCOs 850). Based on the respective
select signals, as discussed above, the DFLL controller 820 may
control an operating frequency of the VCOs 850. This operates in a
closed loop so that the DFLL controller 820 may appropriately
adjust the core clock signals over time to a desired frequency.
A bus-to-core frequency ratio may be arbitrary. A typical PLL-based
synchronous core design, the bus-to-core frequency ratio may be an
integer, or the bus-to-core frequency may be a simple low integer
fraction. Embodiments of the present invention allow the
bus-to-core frequency ratio to be any positive real number. This
may differ from a PLL-based synchronous core design in which the
bus-to-core frequency ratio may be an integer or the bus-to-core
frequency may be a simple low integer fraction. This may enhance
marketability of the product. For power management, a continuous
bus-to-core ratio allows finer control of core speed. This also
allows more efficient throttling (i.e., a better derated
performance at a derated power).
By imposing a modulation pattern on the (n, n+2) switching, an
effective spread spectrum method may be achieved. This intentional
jitter may reduce the peak noise of the microprocessor and help
meet FCC emission limits without losing performance.
A frequency monitor may be a useful component. The frequency
monitor may be in the form of a jitter detector locked to the
processor's average frequency. By instantaneously comparing core
clock periods to the averaged reference, an instantaneous clock
period may be computed. This may be used as a debug aid to check
the effect of spread spectrum modulation.
Embodiments of the present invention have been described with
respect to a clock generating circuit and a clock distribution
network. The clock distribution network is intended to include
clock distribution grids and clock distribution trees and their
equivalence. The clock generating circuit may be provided in areas
(other than the core) that include any type of clock distribution
network.
Any reference in this specification to "one embodiment", "an
embodiment", "example embodiment", etc., means that a particular
feature, structure, or characteristic described in connection with
the embodiment is included in at least one embodiment of the
invention. The appearances of such phrases in various places in the
specification are not necessarily all referring to the same
embodiment. Further, when a particular feature, structure, or
characteristic is described in connection with any embodiment, it
is submitted that it is within the purview of one skilled in the
art to effect such feature, structure, or characteristic in
connection with other ones of the embodiments. Furthermore, for
ease of understanding, certain method procedures may have been
delineated as separate procedures; however, these separately
delineated procedures should not be construed as necessarily order
dependent in their performance, i.e., some procedures may be able
to be performed in an alternative ordering, simultaneously,
etc.
Although embodiments of the present invention have been described
with reference to a number of illustrative embodiments thereof, it
should be understood that numerous other modifications and
embodiments can be devised by those skilled in the art that will
fall within the spirit and scope of the principles of this
invention. More particularly, reasonable variations and
modifications are possible in the component parts and/or
arrangements of the subject combination arrangement within the
scope of the foregoing disclosure, the drawings and the appended
claims without departing from the spirit of the invention. In
addition to variations and modifications in the component parts
and/or arrangements, alternative uses will also be apparent to
those skilled in the art.
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