Arithmetic circuit for finite field GF (2m)

Abstract

An arithmetic unit which performs all basic arithmetic operations in a finite field GF(2.sup.m) and includes an arithmetic processor, an arithmetic logic unit and a control unit is disclosed. The arithmetic unit of the present invention is structured with a low circuit complexity, so that an error-correcting decoder applying this calculating processor can be greatly simplified.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an arithmetic circuit for performing all arithmetic operations in a finite field GF(2.sup.m).

2. Description of the Related Art

In recent years, finite fields have attracted much attention in computer and communication applications. For instance, forward error-correction codes have been widely used in digital communications. However, to design an error-correction circuit with both a high operation speed and a low circuit complexity, it is a necessity to have a multi-function arithmetic circuit. Therefore, there is a trend, when designing the multi-function arithmetic circuit, to reduce its complexity, shorten its calculating delay and increase its operation speed. As any skilled person knows, addition, multiplication, division, exponentiation and inverse multiplication are the most basic arithmetic operations in a finite field. To perform these arithmetic operations, several kinds of circuits have been proposed on different bases, such as dual basis, normal basis and standard basis. Usually, arithmetic operations on dual basis and normal basis need extra transformations, while arithmetic operations on standard basis need no more transformations. Consequently, the arithmetic circuit of the present invention applies the standard basis although some arithmetic operations are best implemented on dual basis or normal basis.

In a finite field GF(2.sup.m), an adder on standard basis is easily implemented by m XOR gates, and a parallel-in-parallel-out multiplier on standard basis is first implemented by B. A. Laws, Jr and C. K. Rushforth, see "A cellular-array multiplier for finite fields GF(2.sup.m)" in IEEE trans. Corput., vol.C-20, pp. 1573-1578, 1971. Further, to increase the operation speed of the cellular-array multiplier, another systolic-array product-sum multiplier is also disclosed by C. S. Yeh, Irving S. Reed and T. K. Truong, see "Systolic multipliers for finite fields GF(2.sup.m)" in IEEE trans. Comput., vol. C-33, pp.357-360, 1984. Comparing the operation speeds of these two multipliers, a multiplication needs 2.sup.m gate delays in the cellular-array multiplier and one celltime delays (about two gate delays) in the systolic-array product-sum multiplier. However, the circuit complexity of the systolic-array product-sum multiplier is far more complicated than that of the cellular-array multiplier. Also, the first input of the systolic-array product-sum multiplier has a latency (about 3 m celltime delays) before the first output is obtained, it is also improper to apply the systolic-array product-sum multiplier in a pipeline-structured circuit.

Theoretically, division in a finite field GF(2.sup.m) is implemented by a multiplication and an inverse multiplication, i.e., A/B=A*B.sup.-1, where A and B are elements in the finite field GF(2.sup.m). Inverse multiplication can be implemented by using a ROM table, applying Euclid's rule or combining a series of multiplications. Nowadays, inverse multiplication is mostly implemented on normal basis because square can be implemented by a simple cyclic shifting. Similarly, exponentiation can be also implemented by using a ROM table or combining a series of multiplication. Following is a list of references: [1] B. A. Laws, m Jr., and C. K. Rushforth, "A cellular-array multipliers for finite fields GF(2.sup.m)," IEEE Trans. Comput., vol. C-20, pp. 1573-1578, 1971. [2] C. -S. Yeh, Irving S. Reeds and T. K. Truong, "Systolic multipliers for finite fields GF(2.sup.m)," IEEE Trans. Comput., vol. C-33, pp. 357-360, 1984. [3] C. C. Wang, T. K. Truong, H. M. Shao, L. J. Dentsch, J. K. Omura, and I. S. Reed. "VLSI architectures for computing multiplications and inverses in GF(2.sup.m)." IEEE Trans. Comput., vol. C-34, pp. 709-716, 1985. [4] H. Okano, and H. Imai "A construction method of high-speed decoders using ROM's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon codes," IEEE Trans. Comput., vol. C-36, pp. 1165-1171, 1987. [5] K. Araki, I. Fujita, and M. Morisue "Fast inverter over finite field based in Euclid's algorithm," Trans. IEICE, vol. E-72, pp. 1230-1234, November 1989. [6] P. A. Scott, S. J. Simmons, S. E. Tavares, and L. E. Peppard, "Architectures for exponentiation in GF(2.sup.m)," IEEE J. Selected Areas in Commun., vol. 6, No. 3, pp. 578-586, April 1988. [7] C. C. Wang, and D. Pei, "A VLSI design for computing exponentiations in GF(2.sup.m) and its application to generate pseudorandom number sequences," IEEE Trans. Comput., vol. C-39, No.2 pp. 258-262, February 1990.

Wei has also proposed another cellular-array power-sum circuit in 1996, for performing AB.sup.2 +C, where A, B and C are elements in the finite field GF(2.sup.m). Under this structure, other arithmetic circuits for performing exponentiation, inverse multiplication and division are also disclosed.

However, the mentioned arithmetic circuits are respectively designed for a specific arithmetic operation, which is never enough, for example, a forward error-correction decoder. In a finite field GF(2.sup.m), an arithmetic circuit with high-speed, low complexity, and versatile features is required. For example, the decoding process of Peterson's direct solution method for decoding the 3-error-correcting Reed-Solomon code are: (i) Calculate the syndrome value of the received word,

S.sub.i =r(.alpha..sup.i)=r.sub.0 +r.sub.1.multidot.(.alpha..sup.i)+r.sub.2.multidot.(.alpha..sup.i).sup.2 + . . . r.sub.n-1.multidot.(.alpha..sup.i).sup.n-1, where i=1, 2, 3, 4, 5, 6. (ii) Determine error-location polynomial .sigma.(X) from the syndrome values. For example, if there are 3 errors in the received word, the error-location polynomial

##EQU1## (iii) Find the roots of the error-location polynomial .sigma.(X) to obtain error locators. (iv) Calculate error values at each error locator. For example, if the error locators are X.sub.1, X.sub.2 and X.sub.3, the error values are respectively: ##EQU2##

Thus, the received word can be corrected with reference to the calculated error value, and the decoding procedure is accomplished, (see "Error-Control Techniques for Digital Communication" by A. M. Michelson and A. H. Levesque in 1985 and "Error Control Coding" by S. Lin and D. J. Costellor in 1983).

To solve the above mentioned problems, it is an object of the present invention to provide an arithmetic circuit which can perform all arithmetic operations in the finite field, including addition, multiplication, division, exponentiation and inverse multiplication.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an arithmetic circuit, which can perform all basic arithmetic operations in a finite field GF(2.sup.m), including addition, multiplication, division, exponentiation and inverse multiplication. The arithmetic circuit of the present invention is structured with a low circuit complexity, so that an error-correction decoder applying this arithmetic circuit can be greatly simplified.

BRIEF DESCRIPTION OF THE DRAW

Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiment with reference to the accompanying drawings, in which:

FIG. 1 is a structure diagram showing an arithmetic circuit of the present invention;

FIG. 2A is a structure diagram showing a calculating processor in the arithmetic circuit of the present invention;

FIG. 2B is a circuit diagram showing the [i,j] identity cell in the calculating processor in FIG. 2A;

FIG. 3 is a circuit diagram showing a calculator of the present invention when m=4;

FIG. 4A is a structure diagram showing a general calculating processor in the arithmetic circuit of the present invention;

FIG. 4B is a circuit diagram showing the [i,j] identity cell in the general calculating processor in FIG. 4A;

FIG. 5 is a circuit diagram showing a general calculating processor in the arithmetic circuit of the present invention when m=3.about.10.

FIG. 6 is a circuit diagram showing a primitive-polynomial generator in the arithmetic circuit of the present invention;

FIG. 7 is a circuit diagram showing a size controller in the arithmetic circuit of the present invention;

FIG. 8 is a structure diagram showing an arithmetic processor in the arithmetic circuit of the present invention;

FIG. 9 is a flow diagram showing the arithmetic processor when performing loading;

FIG. 10 is a flow diagram showing the arithmetic processor when performing multiplication;

FIG. 11 is a flow diagram showing the arithmetic processor when performing exponentiation;

FIG. 12 is a flow diagram showing the arithmetic processor when performing inverse multiplication; and

FIG. 13 is a circuit diagram showing an arithmetic logic unit in the arithmetic circuit of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A finite field is first explained as follows.

Finite Field GF(2.sup.m)

A finite field GF(2.sup.m) consists of 2.sup.m elements {0,1=.alpha..sup.0 =.alpha..sup.n, .alpha..sup.1, .alpha..sup.2, . . . , .alpha..sup.n-1 }, where n=2.sup.m-1 and .alpha. is a primitive element which is a root of the primitive polynomial. If the smallest position integer n for which an irreducible polynomial F(x) with degree m divides X.sup.n +1 is n=2.sup.m -1, the polynomial F(x) is called a primitive polynomial. In this case, the primitive polynomial of the finite field GF(2.sup.m) is expressed as F(x)=x.sup.m +f.sub.m-1 x.sup.m-1 +f.sub.m-2 x.sup.m-2 + . . . +f.sub.1 x+1, where f.sub.i =0 or 1 and i=1.about.m-1.

Generally, elements in a finite field GF(2.sup.m) can be represented in two ways. One is the power representation, i.e., GF(2.sup.m)={0,1,.alpha..sup.1,.alpha..sup.2, . . . , .alpha..sup.n-1 }, wherein 1=.sup.0 =.sup.n. The primitive element a is a root of the primitive polynomial. F(x), F(.alpha.)=0. Therefore, .alpha..sup.n +1=0 and then .alpha..sup.n =1, because X.sup.n +1 can be completely divided by F(x). This makes the finite field GF(2.sup.m) is closed under the addition and multiplication. That is, outcomes of addition and multiplication over GF(2.sup.m) are also elements in the finite field GF(2.sup.m). Further, another modulo polynomial .alpha..sup.m =f.sub.m-1.alpha..sup.m-1 +f.sub.m-2.alpha..sup.m-2 + . . . +f.sub.1.alpha.+1 can be also obtained when F(.alpha.)=0. By this, an element in the finite field GF(2.sup.m) can be also expressed as a polynomial with degree m-1 or less, which is called polynomial representation. This is very useful because a polynomial with degree m-1 can be implemented by an m-bit vector. Following is a list of references. [1] T. R. N. Rao and E. Fujiwara, Error-Control Coding for Computer Systems. NJ: Pretice-Hall, 1989. [2] R. E. Blahut, Theory and Practice of Error Control Codes. Reading, M A: Addison-Wesley, 1983. [3] A. M. Michelson, A. H. Levesque, Error-Control Techniques for Digital Communication. John Wiley & Sons, Inc., 1985. [4] S. Lin, and D. J. Costellor, Jr., Error Control Coding. Prentice Hall, 1983.

Arithmetic Unit (AU)

This arithmetic unit includes an arithmetic processor (AP), an arithmetic logic unit (ALU) and control circuits. Therein the arithmetic processor is structured on a calculating processor (CP) which can perform the A*B and A*B.sup.2 operations in the finite field GF(2.sup.m), where A and B are elements in the finite field GF(2.sup.m). Based on this calculating processor, multiplication, division, exponentiation and inverse multiplication can be performed on this calculating processor. The major job of the arithmetic logic unit is provided to perform addition in the finite field GF(2.sup.m). Adding the control circuits, all arithmetic operations in the finite field GF(2.sup.m) can be completed using this arithmetic unit, see FIG. 1.

Calculating Processor (CP)

This calculating processor is provided to perform A*B and A*B.sup.2 in the finite field GF(2.sup.m), which includes an array of m.times.m identity cells. Each identity cell includes three two-input AND gates, one two-input XOR gate, one three-input XOR gate and a multiplexer (see FIG. 2A and FIG. 2B). In this calculating processor, what arithmetic operation this calculating processor wants to perform is decided by a control signal Control. Assume two input elements A and B are respectively expressed as:

And the primitive polynomial F(x)=x.sup.m +f.sub.m-1 x.sup.m-1 + . . . +f.sub.2 x.sup.2 +f.sub.1 x+f.sub.0, where f.sub.i (0<=i<=m-1) are the coefficients of the primitive polynomial. This calculating processor performs the A*B operation when Control=0. At this time, f'.sub.i =0, 0<=i<=m-1. Further, this calculating process or performs the A*B.sup.2 operation when Control=1. At this time, f'.sub.i =f.sub.m-1.multidot.f.sub.i +f.sub.i-1, 1<=i<=m-1 and f'.sub.0 =f.sub.m-1.multidot.f.sub.0. The outcome of this calculating processor is: ##EQU3##

<1>AB Operation

When Control=0, the input signal f'.sub.i =0, 0<=i<=m-1. As a result, the AND gates AND3 in each identity cell outputs a 0's, and the multiplexer MUK output t.sub.i.sup.(j) =q.sub.i.sup.(j-1). Accordingly, for the [i,j] identity cell,

p.sub.i.sup.(j) =p.sub.i.sup.(j-1) +q.sub.i.sup.(j-1).multidot.b.sub.j

and the output Q.sup.(j) of the m identity cells in the j.sup.th column is: ##EQU4##

For example, ##EQU5##

From above, the output Q.sup.(j) of the m identity cells in the j.sup.th column of the calculating processor can be simplified to: ##EQU6##

Similarly, the output P.sup.(j) of the m identity cells in the j.sup.th column of the calculating processor is: ##EQU7##

For example, ##EQU8##

(where the input signal p.sub.i.sup.(-1) of the m identity cells in the first row is 0, 0 i m-1) ##EQU9##

From above, the output P.sup.(j) of the m identity cells in the j.sup.th column of the calculating processor can be simplified to: ##EQU10##

According to this rule, the output of the last column (the output of the calculating processor) is: ##EQU11##

Thus, the calculating processor performs the A*B operation when Control=0.

<2>AB.sup.2 Operation

When Control=1, the multiplexer MUX of each identity cell output t.sub.i.sup.(j) =q.sub.i-1.sup.(j-1), Accordingly,

And for the [i,j] identity cell,

Then ##EQU12##

wherein ##EQU13##

Therefore, the output Q.sup.(j) of the m identity cells in the j.sup.th column of the calculating processor is: ##EQU14##

From above, the output Q.sup.(j) of the m identity cells in the j.sup.th column of the calculating processor can be simplified to: ##EQU15##

Similarly, the output P.sup.(j) of the m identity cells in the j.sup.th column of the calculating processor is: ##EQU16##

Then ##EQU17##

According to this rule, the output of the calculating processor is: ##EQU18##

Thus, the calculating processor performs AB.sup.2 when Control=1.

Example

Calculating Processor of a Finite Field GF(2.sup.4)

A calculating processor in the finite field GF(2.sup.4) is disclosed (see FIG. 3). This calculating processor is an array of 4.times.4 identity cells. The primitive polynomial F(x) of the finite field GF(2.sup.4) is F(x)=1+X+X.sup.4. That is, f.sub.0 =f.sub.1 =1, f.sub.2 =f.sub.3 =0 and ##EQU19##

The input signals are two elements A=(a.sub.0, a.sub.1, a.sub.2, a.sub.3), B=(b.sub.0, b.sub.1, b.sub.2, b.sub.3) and a control signal Control, and the output signal p.sub.0 -p.sub.3 is ##EQU20##

By this method, a calculating processor of any size can be designed.

General Calculating Processor

The calculating processor mentioned above can be modified to a general calculating processor of a finite field GF(2.sup.m) (see FIG. 4). The same with the above calculating processor, the general calculating processor is also an array of identity cells. Assume this general calculating processor is structured of M.times.M identity cells, then this general calculating processor can perform the A*B and A*B.sup.2 operation in all finite field GF(2.sup.m) if m<=M, where A and B are elements of the finite field GF(2.sup.m). Further, to adapt different-sized finite field GF(2.sup.m), each identity cell is further provided with two two-input multiplexers MUX1, MUX2 and a control signal m.sub.i. The control signal m.sub.i is determined by the size m of the finite field GF(2.sup.m), for controlling the multiplexers MUX1 and MUX2. The control signal m.sub.m-1 =1 only for the (m-1).sup.th row of identity cells, so that the multiplexer MUX1 can pass t.sub.m-1.sup.(j) to Carry1.sub.i.sup.(j) (i.ltoreq.m-1) in the same row, and the other multiplexer MUX2 can pass q.sub.m-1.sup.(j-1) to Carry2.sub.i.sup.(j) (i.ltoreq.m-1) in the same row. The other control signals m.sub.i =0 for i.noteq.m-1, so that the multiplexer MUX1 in all identity cells for i<m-1 can receive Carry1.sub.i+1.sup.(j) =t.sub.m-1.sup.(j-1) of the upper identity cell to its Carry1.sub.i.sup.(j), and the other multiplexer MUX2 in all identity cells for i<m-1 can receive Carry.sup.2.sub.i+1.sup.(j)=q.sub.m-1.sup.(j-1) of the upper identity cell to its Carry2.sub.i.sup.(j). Thus, the m.times.m identity cells at the right-down part of this general calculating processor perform the same arithmetic operations as the above mentioned m.times.m calculating processor. Further, the input signal b.sub.j =0 for m<=j<=M-1, ##EQU21##

Therefore the output of the general calculating processor is: ##EQU22##

Thus, a general calculating processor which can perform AB and AB.sup.2 in different-sized finite field GF(2.sup.m) can be designed.

The I/O ports of a general calculating processor includes two sets of input signals: two input elements A and B:

To reduce the number of the I/O ports, the primitive polynomial generator and the field-size controller can be designed with simple logic gates. By inputting several bits of control signals, parameters f.sub.i and f'.sub.i can be obtained by the primitive polynomial generator and parameter m.sub.i can be obtained by the field-size controller. Thus, the total number of the I/O ports can be reduced.

Example

General Calculating Processor for Finite Fields GF(2.sup.3).about.GF(2.sup.10)

As shown in FIG. 5, a general calculating processor for finite fields GF(2.sup.3).about.GF(2.sup.10) includes an array of 10.times.10 identity cells, a primitive polynomial generator and a field-size controller. The primitive polynomial generator and the field-size controller are controlled by three control signals M1.about.M3. Assume the primitive polynomial for the finite field GF(2.sup.m) is expressed as f(x)=x.sup.m +f.sub.m-1 x.sup.m-1 + . . . +f.sub.2 x.sup.2 +f.sub.1 x+f.sub.0, ##EQU24##

This patent has confirmed that f.sub.m-1 =0 for m=3.about.34, therefore f.sub.i =f.sub.i-1,1.ltoreq.i.ltoreq.m-1. Thus, the primitive polynomial generator can be simplified to reduce the circuit complexity, whose truth table is listed in Table I, as shown in FIG. 6. Also, the field-size controller of the finite field GF(2.sup.m) can be designed according to the truth table listed in Table II, as shown in FIG. 7.

Thus, a general calculating processor for a finite field GF(2.sup.m), m=3.about.10 can be implemented. The calculating processor includes an array of 10.times.10 identity cells, a primitive polynomial generator and a field-size controller. The input signals includes a.sub.0 -a.sub.9, b.sub.0 -b.sub.9, M1, M2, M3 and control; while the output signal is p.sub.0 -p.sub.9.

TABLE I M3 M2 M1 f.sub.0 f.sub.1 f.sub.2 f.sub.3 f.sub.4 f.sub.5 f.sub.6 f.sub.7 f.sub.8 f.sub.9 3 0 0 0 1 1 0 0 0 0 0 0 0 0 4 0 0 1 1 1 0 0 0 0 0 0 0 0 5 0 1 0 1 0 1 0 0 0 0 0 0 0 6 0 1 1 1 1 0 0 0 0 0 0 0 0 7 1 0 0 1 0 0 1 0 0 0 0 0 0 8 1 0 1 1 0 1 1 1 0 0 0 0 0 9 1 1 0 1 0 0 0 1 0 0 0 0 0 10 1 1 1 1 0 0 1 0 0 0 0 0 0

TABLE II m M3 M2 M1 m.sub.0 m.sub.1 m.sub.2 m.sub.3 m.sub.4 m.sub.5 m.sub.6 m.sub.7 m.sub.8 m.sub.9 3 0 0 0 0 0 1 0 0 0 0 0 0 0 4 0 0 1 0 0 0 1 0 0 0 0 0 0 5 0 1 0 0 0 0 0 1 0 0 0 0 0 6 0 1 1 0 0 0 0 0 1 0 0 0 0 7 1 0 0 0 0 0 0 0 0 1 0 0 0 8 1 0 1 0 0 0 0 0 0 0 1 0 0 9 1 1 0 0 0 0 0 0 0 0 0 1 0 10 1 1 1 0 0 0 0 0 0 0 0 0 1

Arithmetic Processor (AP)

S Arithmetic processor is structured on the calculating processor, for performing all arithmetic operations except addition. These arithmetic operations can be combined by four basic operations. That is: loading, multiplication, exponentiation and inverse multiplication. For example, division is implemented by combining multiplication and inverse multiplication. The detailed structure diagram of the arithmetic processor is shown in FIG. 8, which includes a calculating processor and additional control circuits and storage memories. For a finite field GF(2.sup.m), these control circuits and storage memories includes five m-bit multiplexers, two groups of m-bit D-type flip flops, an m-bit switch and some logic gates generating control signals for nultiplexers. The input of the arithmetic processor includes: Input=(I.sub.m-1, I.sub.m-2, I.sub.m-3, . . . , I.sub.0), control signal M=(M1, M2, . . . ) determined by the size of the finite field GF(2.sup.m), Signal1, Signal2, Control1, Control2, N.sub.m-1, N', Switch1, Switch2 and G_Clock, while the output of the arithmetic processor includes: Output=(O.sub.m-1, O.sub.m-2, O.sub.m-3, . . . , O.sub.0).

Hereafter, basic arithmetic operations (loading, multiplication, exponentiation and inverse multiplication) which are controlled by two control signals Control1, Control2, are respectively described.

<1>Loading

When the control signals (Control1, Control2)=(0, 0), the arithmetic processor performs the loading operation. This is to have the input Input=(I.sub.m-1, I.sub.m-2, I.sub.m-3, . . . , I.sub.0 ) stored in the register Register1 of the arithmetic processor to serve as an initial value for the next instruction. At this time, the control signals for the multiplexers MUX1.about.MUX4 are respectively 0, 1, 1, 1. If the input Input=(I.sub.m-1, I.sub.m-2, I.sub.m-3, . . . , I.sub.0)=.beta., then two input elements input to the calculating processor are respectively .beta. and .alpha..sup.0. Because the control signal control is 0, the calculating processor performs the A*B operation and the outcome .beta..multidot..alpha..sup.0 =.beta. is then loaded to the register Register1, as shown in FIG. 9.

<2>Multiplication

When the control signals (Control1, Control2)=(0, 1), the arithmetic processor performs multiplication, multiplying the input Input=(I.sub.m-1, I.sub.m-2, I.sub.m-3, . . . , I.sub.0) or the data stored in the register Register2 (determined by the multiplexer MUX5 controlled by the switch signal Switch2) by the data stored in the register Register1. When Switch2=1, the arithmetic processor multiplies the input Input=(I.sub.m-1, I.sub.m-2, I.sub.m-3, . . . , I.sub.0) by the data stored in the register Register1. When Switch2=0, the arithmetic processor multiplies the data stored in the register Register2 by the data stored in the register Register1. When executing this instruction, the calculating processor performs the A*B operation because Control1=0, and the control signals of the multiplexers MUX2.about.MUX4 are respectively 0, 1, 1. The outcome is then stored back in the register Register1, as shown in FIG. 10.

<3>Exponentiation

When the control signals (Control1, Control2)=(1, 1), the arithmetic processor performs exponentiation, especially .beta..sup.N, where .beta..epsilon.GF(2.sup.m) (0.ltoreq.N.ltoreq.2.sup.m -2). .beta. is an element in the finite field GF(2.sup.m), which is input from the input Input=(I.sub.m-1, I.sub.m-2, I.sub.m-3, . . . , I.sub.0) where N is between 0 and 2.sup.m -2 and can be divided as N=N.sub.0 +N.sub.1 2+N.sub.2 2.sup.2 + . . . +N.sub.m-1 2.sup.m-1, then .beta..sup.N can be expressed as: ##EQU25##

The deriving procedure is:

##EQU26##

Apparently, exponentiation .beta..sup.N can be implemented by m-1 AB.sup.2 operations of the calculating processor. Therefore the control signal Control1=1 for (m-1) cycles so that the calculating processor performs the A*B.sup.2 operations for (m-1) times. The outcome P.sub.i of the i.sup.th cycle is stored in the register Register1 so as to feedback to the calculating processor for the next operation. ##EQU27##

Further, the outcome of the exponentiation .beta..sup.Ni is selected from .alpha..sub.0 or .beta. according to N.sub.i. The control signal of the multiplexer MUX5 is Switch2=1 for (m-1) cycles, the control signal of the multiplexer MUX1 is N.sub.m-1 for the first cycle, the control signal of the multiplexer MUX2 is Signal1=(1, 0, 0, . . . , 0) for (m-1) cycles, the control signal of the multiplexer MUX3 is 0 for (m-1) cycles, the control signal of the multiplexer MUX4 is N'=(N.sub.m-2, N.sub.m-3, . . . , N.sub.0). Thus, the outcome of the exponentiation operation can be obtained in (m-1) cycles and stored in the register Register1. Further, when the exponentiation operation is executing, the outcome P.sub.i for each cycle is stored in the register Register1, therefore the data of the previous instruction stored in the register Register1 has to be transferred to the register Register2 (controlled by the signal Signal1) for later use. The procedure of the arithmetic processor can be seen in FIG. 11.

<4>Inverse Multiplication

When the control signal (Control1, Control2)=(1, 0), the arithmetic processor performs inverse multiplication .beta..sup.-1, where .beta..epsilon.GF(2.sup.m). In fact, for the finite field GF(2.sup.m), .beta..sup.-1 =.beta..sup.-2. Therefore, to perform .beta..sup.-1 is to perform exponentiation of N=0+1.multidot.2+1.multidot.2.sup.2 + . . . +1.multidot.2.sup.m-1, where N.sub.0 =0, N.sub.1 =N.sub.2 = . . . =N.sub.m-1 =1). The detailed procedure is: ##EQU28##

Apparently, inverse multiplication .beta..sup.-1, exponentiation .beta..sup.N, is implemented by (m-1) AB.sup.2 operations of the calculating processor. Therefore the control signal Control1=1 for (m-1) cycles so that the calculating processor performs AB.sup.2 operation for (m-1) times. The outcome P.sub.i of the i.sup.th cycle is stored in the register Register1 so as to feedback to the calculating processor for the next AB.sup.2 operation. The control signal of the multiplexer MUX5 is Switch2=1 for (m-1) cycles, the control signal of the multiplexer MUX1 is N.sub.m-1 for the first cycle, the control signal of the multiplexer MUX2 is Signal1=(1, 0, 0, . . . , 0) for (m-1) cycles, the control signal of the multiplexer MUX3 is 1 for (m-1) cycles, the control signal of the multiplexer MUX4 is Signal2=(1, 1, 1, . . . , 0). Thus, the outcome of the inverse multiplication operation can be obtained in (m-1) cycles and stored in the register Register1. Further, when the inverse multiplication operation is executing, the outcome P.sub.i for each cycle is stored in the register Register1, therefore the data of the previous instruction stored in the register Register1 has to be transferred to the register Register2 (controlled by the signal Signal1) for later use. The procedure of the arithmetic processor can be seen in FIG. 12.

As it is able to perform loading, multiplication, exponentiation and inverse multiplication, the arithmetic processor can perform all arithmetic operations in the finite field GF(2.sup.m) except addition (accumulation), which can be implemented by the arithmetic logic unit.

Arithmetic Logic Unit (ALU)

Addition in the finite field GF(2.sup.m) can be simply implemented by m XOR gates, and another register is provided to store the previous data when performing accumulation. When the accumulation is completed, the register is also refreshed. The whole arithmetic logic unit can be seen in FIG. 13. This circuit is designed to perform one accumulation in each cycle, which adds the data from the arithmetic processor and the data stored in the register and outputs back to the register. Whether or not the arithmetic processor performs accumulation is determined by the control signal Switch1. When Switch1=1, the arithmetic logic unit receives the output of the arithmetic processor and performs accumulation. When Switch1=0, a zero element (0) in the finite field GF(2.sup.m) is sent to the arithmetic logic unit, then the output of the arithmetic logic unit remains the same.

Arithmetic Unit (AU)

Combining the arithmetic processor, the arithmetic logic unit and the control circuit, the overall arithmetic circuit for the finite field GF(2.sup.m) can be obtained. The input of the arithmetic circuit includes: Input=(I.sub.m-1, I.sub.m-2, I.sub.m-3, . . . , I.sub.0), control signal M=(M1, M2, . . . ) which is determined by the size of the finite field GF(2.sup.m), Signal1, Signal2, Control1, Control2, N.sub.m-1, N', Switch1, Switch2, Switch3, Clear and G_Clock. The output of the arithmetic circuit includes: Output=(O.sub.m-1, O.sub.m-2, O.sub.m-3, . . . , O.sub.0). The description for these I/O signals is:

Control1, Control2 Description 0, 0 Loading 0, 1 Multiplication 1, 1 Exponentiation 1, 0 Inverse Signal1 Exponentiation/inverse multiplication: Signal1 = (100 . . . 0) in (m - 1) cycles Loading/multiplication: Signal1 = 0 Signal2 Exponentiation/inverse multiplication: Signal2 = (111 . . . 10) in (m - 1) cycles Loading/multiplication: Signal2 = 1 N.sub.m-1, N' Exponentiation .beta..sup.N, where N = N.sub.0 + N.sub.1 2 + N.sub.2 2.sup.2 + . . . + N.sub.m-1 2.sup.m-1, and Nm - 1 = N.sub.m-1 (N' = N.sub.m-2, N.sub.m-3, . . ., N.sub.0) Clear Clear data stored in the registers G_Clock Cycle signal of the arithmetic circuit Switch1 Addition: Switch = 1, else Switch1 = 0 Switch2 Data input externally (I.sub.m-1, I.sub.m-2, . . ., I.sub.0): Switch2 = 1; data input from internal register Register2: Switch2 = 0 Switch3 Data output: Switch3 = 1, else Switch3 = 0 (I.sub.m-1, I.sub.m-2, . . ., I.sub.0) Input signal (O.sub.m-1, O.sub.m-2, . . ., O.sub.0) Output signal M = (M1, M2, . . .) Control signals for primitive polynomial generator and field-size controller

Priority of the Arithmetic Circuit

1. Operations in the Bracket: ( ), [ ] and { }

Arithmetic operations in the bracket have the highest priority.

2. Exponentiation and Inverse Multiplication

Exponentiation and inverse multiplication have higher priority than multiplication and addition. When performing exponentiation and inverse multiplication, the former result is first stored in the register Register2. For example, when performing A/B which is implemented by combining multiplication and inverse multiplication, the element A is first loaded to the register Register2, then the element B is loaded to the register Register1 and used to obtain B.sup.-1. After B.sup.-1 is obtained in (m-1) cycles, the element A stored in the register Register1 and the element B stored in the element B are multiplied to obtain the final result.

3. Multiplication

When the data used to perform multiplication includes an exponential number or inverse multiplicative number, the multiplication number is postponed until exponentiation or inverse multiplication is completed. From above, one can understand that multiplication has higher priority than addition. For example, when performing A+BC, the element A is first loaded, then the signal Switch1 is set to 1 so that the element A is sent to the arithmetic logic unit, followed with multiplication BC. In this case, the multiplication BC is first performed and the result is then sent to the arithmetic logic unit for later addition.

4. Addition

Addition has the lowest priority in all arithmetic operations and is the only operation performed outside the arithmetic processor. When performing addition, the result of the arithmetic processor is sent to the arithmetic logic unit to perform accumulation. One can easily see this because the accumulation performed by the arithmetic logic unit is not started until all operations performed by the arithmetic processor are completed.

Summing up, the present invention provides an arithmetic circuit, which can perform all basic arithmetic operations in a finite field GF(2.sup.m), including addition, multiplication, division, exponentiation and inverse multiplication. The arithmetic circuit of the present invention is structured with a low circuit complexity, so that an error-correction decoder applying this arithmetic circuit can be greatly simplified.

While the invention has been particularly shown and described with the reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Claims

What is claimed is:

1. An arithmetic processor capable of executing arithmetic operations of multiplication A*B, exponential B.sup.N and inverse multiplication operation B.sup.-1, where N is a positive integer, for loading elements A and B in a finite field GF(2.sup.m) and performing all arithmetic operations but an addition operation A+B in the finite field GF(2.sup.m), comprising: a calculating processor capable of performing arithmetic operations AB and AB.sup.2, for loading elements A and B in the finite field GF(2.sup.m) and outputting AB or AB.sup.2 according to a control signal; registers storing the outcome of the calculating processor; and control circuits selectively transmitting the elements A and B in the finite field GF(2.sup.m) from the input terminal of the arithmetic processor or the registers to the input terminals of the calculation processor according to the control signal so that the calculating processor can correctly output AB, AB.sup.2 ; wherein, a first and a second control signals are applied to the arithmetic processor: when the first and second control signals are logic low, the arithmetic processor performs a loading operation and an input D=[d.sub.m-1, d.sub.m-2, . . . , d.sub.0 ] is stored in a first register from the registers, when the first control signal is 0 and the second control signal is 1, the arithmetic processor performs multiplication, multiplying the input D=[d.sub.m-1, d.sub.m-2, . . . , d.sub.0 ] or a data C stored in a second register from the registers by the data stored in the first register and loading the outcome to the first register, when the first and second control signals are logic high, the arithmetic processor performs exponentiation by replacing exponential operation with the (m-1) times C*D.sup.2, where m is a positive integer, represents the degree of GF(2.sup.m), when the first control signal is 1 and the second control signal is 0, the arithmetic processor performs inverse multiplication D.sup.-1,where D.epsilon.GF(2.sup.m) and D.sup.-1 =D.sup.2.sup..sup.m .sup.-2.

2. The arithmetic processor as claimed in claim 1, further comprising a switch for outputting the outcome of the calculating processor in the register according to a control signal.

3. The arithmetic processor as claimed in claim 1, wherein the control signal comprises a set of timing control signals for controlling timing sequence and data transmission of the control circuits and the registers.

4. The arithmetic processor as claimed in claim 1, wherein the finite field GF(2.sup.m) corresponds to a primitive polynomial F represented by [f.sub.m-1, f.sub.m-2, . . . , f.sub.0 ] and an induced parameter F'=[f'.sub.m-1, f'.sub.m-2, . . . , f'.sub.0 ] on standard basis, the elements C and D are respectively represented by [c.sub.m-1, c.sub.m-2, . . . , c.sub.0 ] and [d.sub.m-1, d.sub.m-2, . . . , d.sub.0 ] on standard basis, the arithmetic operation CD is performed when f'.sub.i =0, the arithmetic operation CD.sup.2 is performed when f'.sub.i =f.sub.m-1 *f.sub.i +f.sub.i-1 (1<=i<=m-1) and f'.sub.0 =f.sub.m-1 *f.sub.0 where m is a positive integer, and the calculating processor comprises: an array of m.times.m identity cells, each having an input terminal D, an input terminal F, an input terminal F', an input terminal Carry1, an input terminal Carry2, an output terminal Carry1, an output terminal Carry2, an input terminal t, an output terminal t, a row control signal q, an input terminal p, an input terminal q, an output terminal p, an output terminal q and a control signal terminal, wherein the [i,j] identity cell has its input terminal D connected to the signal d, its input terminal F connected to the signal f.sub.i its input terminal F' connected to the signal f'.sub.i, its input terminal Carry1 connected to the output terminal Carry1 of the [i+1,j] identity cell, its input terminal Carry2 connected to the output terminal Carry2 of the [i+1,j] identity cell, its input terminal t connected to the output terminal t of the [i-1,j] identity cell, its input terminal p connected to the output terminal p of the [i,j-1] identity cell, its input terminal q connected to the output terminal q of the [i,j-1] identity cell, its row control terminal q connected to the output terminal q of the [i-1,j-1] identity cell, its output terminals p and q outputting q[i, j-1]*d.sub.j +p [i, j-1] and q[m-1,j -1]*f.sub.i +q[i-1,j -1] when its control signal is connected to a logic 0 and outputting q[i,j-1]*d.sub.j +p[i,j-1] and q[m-2,j-1]*f.sub.i +q[m-1,j-1]*f'.sub.i +q[i-2,j-1] when its control signal is connected to a logic 1, the [i,0] identity cell has its input terminal q connected to the signal c.sub.i, the [i,0] identity cell has its input terminal p connected to the logic 0, the [0,j] identity cell has its row control terminal q and its input terminal t connected to the logic 0, and the [m-1,0] identity cell has its output terminal t connected to the input terminal Carry1 and its input terminal q connected to the input terminal Carry2, thereby forming two feedback loops.

5. The arithmetic processor as claimed in claim 4, wherein each identity cell is a combinational circuit of logic gates.

6. The arithmetic processor as claimed in claim 4, wherein each identity cell comprises: a multiplexer having a control terminal connected to the control signal of the identity cell, two input terminals respectively connected to the input terminal q of the identity cell and the row control terminal q of the identity cell, and an output terminal connected to the output terminal t of the identity cell; a first AND gate having two inputs respectively connected to the input terminals q and D of the identity cell; a second AND gate having two inputs respectively connected to the input terminal F and the input terminal carry1 of the identity cell; a third AND gate having two inputs respectively connected to the input terminal F' and the input terminal carry2 of the identity cell; a first XOR gate having two inputs respectively connected to the input terminal p of the identity cell and the output of the first AND gate, and an output connected to the output terminal p of the identity cell; and a second XOR gate having three inputs respectively connected to the input terminal t of the identity cell, the outputs of the second and the third AND gates, and an output connected to the output terminal q of the identity cell.

7. The arithmetic processor as claimed in claim 1, wherein the finite field GF(2.sup.m) corresponds to a primitive polynomial F represented by [f.sub.m-1, f.sub.m-2, . . . , f.sub.0 ] and an induced parameter F'=[f'.sub.m-1, f'.sub.m-2, . . . , f'.sub.0 ] on standard basis, the elements C and D are respectively represented by [c.sub.m-1, c.sub.m-2, . . . , c.sub.0 ] and [d.sub.m-1, d.sub.m-2, . . . , d.sub.0 ] on standard basis, the arithmetic operation CD is performed when f'.sub.i =0, the arithmetic operation CD.sup.2 is performed when f'.sub.i =f.sub.m-1,*f.sub.i +f.sub.i-1 (1<i<m-1) and f'.sub.0 =f.sub.m-1 *f.sub.0 where m is a positive integer, represents the degree of GF(2.sup.m), and the calculator can be extended to a general calculating processor for all finite field m<M, where M is positive integer, which comprises: an array of M.times.M identity cells, each having an input terminal D, an input terminal F, an input terminal F', a row control signal q, an input terminal Carry1, an input terminal Carry2, an output terminal Carry1, an output terminal Carry2, an input terminal t, an output terminal t, an input terminal m, an input terminal p, an input terminal q, an output terminal p, an output terminal q and a control signal terminal, wherein the [i,k] identity cell has its input terminal D connected to the signal d.sub.k, its input terminal F connected to the signal f.sub.i, its input terminal F' connected to the signal f'.sub.i, its input terminal p connected to the output terminal p of the [i,k-1] identity cell, its input terminal q connected to the output terminal q of the [i,k-1] identity cell, its input terminal Carry1 connected to the output terminal Carry1 of the [i+1,k] identity cell, its input terminal Carry2 connected to the output terminal Carry2 of the [i+1,k] identity cell, its input terminal m connected to a size-control signal indicating the size of the finite field, its input terminal t connected to the output terminal t of the [i-1,k] identity cell, its row control terminal q connected to the output terminal q of the [i-1,k-1] identity cell, its output terminals p and q outputting q[i,k-1]*d.sub.k +p[i,k-1] and q[m-1,k-1]*f.sub.i +q[i-1,k-1] when its control signal is connected to a logic 0 and outputting q[i,k-1]*d.sub.k +p[i,k-1] and q[m-1,k-1]*f.sub.i +q[m-2,k-1]*f.sub.i +q[i-2,k-1] when its control signal is connected to a logic 1, the [i,0] identity cell has its input terminal q connected to the signal c.sub.i, the [i, 0] identity cell has its input terminal p connected to the logic 0, the [0,k] identity cell has its row control terminal q and its input terminal t connected to the logic 0, the [M-1,0] identity cell has its output terminal t connected to the input terminal Carry1 and its input terminal q connected to the input terminal Carry2, thereby forming two feedback loops.

8. The arithmetic processor as claimed in claim 7, further comprising a size controller and a polynomial generator, for determining the size of the finite field and the coefficients of the primitive polynomial.

9. The arithmetic processor as claimed in claim 7, wherein each identity cell is a combinational circuit of logic gates.

10. The arithmetic processor as claimed in claim 9, wherein each identity cell comprises: a multiplexer having a control terminal connected to the control signal of the identity cell, two input terminals respectively connected to the input terminal q of the identity cell and the row control terminal q of the identity cell, and an output connected to the output terminal t of the identity cell; a first multiplexer having a control terminal connected to a size-control signal indicating the size of the finite field, two input terminals respectively connected to the output of the multiplexer of the identity cell and the input terminal Carry1 of the identity cell, and an output terminal connected to the output terminal Carry1 of the identity cell; a second multiplexer having a control terminal connected to the size signal, two input terminals respectively connected to the input terminals q and Carry2 of the identity cell, and an output terminal connected to the output terminal Carry2 of the identity cell; a first AND gate having two inputs respectively connected to the input terminals q and D of the identity cell; a second AND gate having two inputs respectively connected to the input terminal F and the output terminal of the first multiplexer; a third AND gate having two inputs respectively connected to the input terminal F and the output terminal of the second multiplexer; a first XOR gate having two inputs respectively connected to the input terminal p of the identity cell and the output of the first AND gate, and an output connected to the output terminal p of the identity cell; and a second XOR gate having three inputs respectively connected to the input terminal t of the identity cell and outputs of the second and the third AND gates, and an output connected to the output terminal q of the identity cell.