U.S. patent number 6,528,979 [Application Number 10/071,022] was granted by the patent office on 2003-03-04 for reference current circuit and reference voltage circuit.
This patent grant is currently assigned to NEC Corporation. Invention is credited to Katsuji Kimura.
United States Patent |
6,528,979 |
Kimura |
March 4, 2003 |
Reference current circuit and reference voltage circuit
Abstract
There is disclosed a reference current circuit capable of
preventing an appearance of the effect of the Early voltage,
operated from a low power supply voltage, and adapted to output a
current having a positive or optional temperature characteristic.
In this reference current circuit, by a self-biased method, a
current of a current mirror circuit is set to be proportional or
substantially inversely proportional to a temperature by first and
second transistors constituting a non-linear current mirror
circuit. A third transistor is provided. A current of the third
transistor proportional to a third voltage between a control
terminal and a current input terminal is set to be substantially
inversely proportional to the temperature, and the currents of the
current mirror circuit and the third transistor are weighted and
added. Thus, an output current having a fixed temperature current
is obtained.
Inventors: |
Kimura; Katsuji (Tokyo,
JP) |
Assignee: |
NEC Corporation
(JP)
|
Family
ID: |
18899459 |
Appl.
No.: |
10/071,022 |
Filed: |
February 8, 2002 |
Foreign Application Priority Data
|
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|
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Feb 13, 2001 [JP] |
|
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2001-036139 |
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Current U.S.
Class: |
323/313; 323/314;
323/907 |
Current CPC
Class: |
G05F
3/267 (20130101); G05F 3/30 (20130101); G05F
3/262 (20130101); G05F 3/265 (20130101); Y10S
323/907 (20130101) |
Current International
Class: |
G05F
3/30 (20060101); G05F 3/08 (20060101); G05F
3/26 (20060101); G05F 003/16 (); G05F 003/20 () |
Field of
Search: |
;323/315,314,907,313 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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0 411 657 |
|
Mar 1990 |
|
EP |
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59-191629 |
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Oct 1984 |
|
JP |
|
07200086 |
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Apr 1995 |
|
JP |
|
7-200086 |
|
Aug 1995 |
|
JP |
|
Other References
Neuteboom, Harry and Ben M.J. Kup and Mark Janssens, "A DSP-Based
Hearing Instrument IC". IEEE Journal of Solid-State Circuits, vol.
32, No. 11, Nov. 1997, pp. 1790-1806..
|
Primary Examiner: Vu; Bao Q.
Attorney, Agent or Firm: Hayes Soloway P.C.
Claims
What is claimed is:
1. A reference current circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between between the power supply line and the ground line, wherein
the current mirror circuit includes a first resistor having one end
connected to a first node, and the other end connected to a second
node, a first transistor connected between the second node and the
ground line, and having a control terminal connected to the first
node, and a second transistor connected between a third node and
the ground line, and having a control terminal connected to the
second node, and the third transistor has a control terminal
connected to the third node, drives the current mirror circuit for
setting a current source for driving the first and second
transistors as a mirror current, and constitutes a negative
feedback current loop.
2. A reference current circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line, wherein the
current mirror circuit includes a first resistor having one end
connected to a second node, and the other end connected to the
ground line, a first transistor connected between the first and
second nodes, and having a control terminal connected to the first
node, and a third node, and a second transistor connected between a
fourth node and the ground line, and having a control terminal
connected to the third node, and the third transistor has a control
terminal connected to the third node, drives the current mirror
circuit for setting a current source for driving the first and
second transistors as a mirror current, and constitutes a negative
feedback current loop.
3. A reference current circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line, wherein the
current mirror circuit includes a first resistor having one end
connected to a fourth node, and the other end connected to the
ground line, a first transistor connected between a first node and
the ground line, and having a control terminal connected to each of
the first node and a second node, and a second transistor connected
between a third node and the fourth node, and having a control
terminal connected to the second node, and the third transistor has
a control terminal connected to the third node, drives the current
mirror circuit for setting a current source for driving the first
and second transistors as a mirror current, and constitutes a
negative feedback current loop.
4. A reference current circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line; and second and
third resistors, wherein the current mirror circuit includes a
first resistor having one end connected to a second node, and the
other end connected to the ground line, a first transistor
connected between the first and second nodes, and having a control
terminal connected to the first node and a third node, and a second
transistor connected between a fourth node and the ground line, and
having a control terminal connected to the third node, the second
resistor has one end connected to the first node, and the other end
connected to the ground line, the third resistor has one end
connected to the fourth node, and the other end connected to the
ground line, and the third transistor has a control terminal
connected to the fourth node, drives the current mirror circuit for
setting a current source for driving the first and second
transistors as a mirror current, and constitutes a negative
feedback current loop.
5. A reference current circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line; and second and
third resistors, wherein the current mirror circuit includes a
first resistor having one end connected to a first node, and the
other end connected to a second node, a first transistor connected
between the second node and the ground line, and having a control
terminal connected to the first node and a third node, and a second
transistor connected between the third node and the ground line,
and having a control terminal connected to the second node, the
second resistor has one end connected to the first node, and the
other end connected to the ground line, the third resistor has one
end connected to the third node, and the other end connected to the
ground line, and the third transistor has a control terminal
connected to the third node, drives the current mirror circuit for
setting a current source for driving the first and second
transistors as a mirror current, and constitutes a negative
feedback current loop.
6. A reference current circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; a third transistor connected
between the power supply line and the ground line; and second and
third resistors, wherein the current mirror circuit includes a
first resistor having one end connected to a fourth node, and the
other end connected to a second node, a first transistor connected
between a first node and the ground line, and having a control
terminal connected to the first and second nodes, and a second
transistor connected between a third node and the fourth node, and
having a control terminal connected to the second node, the second
resistor has one end connected to the first node, and the other end
connected to the ground line, the third resistor has one end
connected to the third node, and the other end connected to the
ground line, and the third transistor has a control terminal
connected to the third node, drives the current mirror circuit for
setting a current source for driving the first and second
transistors as a mirror current, and constitutes a negative
feedback current loop.
7. A reference current circuit according to any one of claims 1 to
6, wherein a current outputted from the reference current circuit
is supplied into a fifth resistor.
8. A reference current circuit according to claim 7, wherein the
fifth resistor includes a plurality of resistors connected in
series.
9. A reference current circuit according to any one of claims 1 to
8, wherein a current of the third transistor is set to be
substantially inversely proportional to a temperature, a current
mirror circuit current flowing to the transistor of the current
mirror circuit and the current of the third transistor are weighted
and added, and an output current having a fixed temperature
characteristic is obtained.
10. A reference voltage circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line, wherein the
current mirror circuit includes a first resistor having one end
connected to a second node, and the other end connected to the
ground line, a first transistor connected between a first node and
the second node, and having a control terminal connected to the
first node and a third node, and a second transistor connected
between a fourth node and the ground line, and having a control
terminal connected to the third node, the reference voltage circuit
being self-biased to constitute a reference current circuit, and
including a second resistor having one end connected to a fourth
node, and the other end connected to a fifth node, the third
transistor connected between the fifth node and the ground line,
and having a control terminal connected to the fifth node, and a
third resistor having one end connected to the fourth node, and the
other end connected to the ground line, and an output voltage being
obtained by supplying an output current of the reference current
circuit to paths of the third transistor and the third resistor
through the second resistor.
11. A reference voltage circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line, wherein the
current mirror circuit includes a first resistor having one end
connected to a first node, and the other end connected to a second
node, a first transistor connected between the second node and the
ground line, and having a control terminal connected to the first
node, and a second transistor connected between a third node and
the ground line, and having a control terminal connected to the
second node, the reference voltage circuit being self-biased to
constitute a reference current circuit, and including a second
resistor having one end connected to a fourth node, and the other
end connected to a fifth node, the third transistor connected
between the fifth node and the ground line, and having a control
terminal connected to the fifth node, and a third resistor having
one end connected to the fourth node, and the other end connected
to the ground line, and an output voltage being obtained by
supplying an output current of the reference current circuit to
paths of the third transistor and the third resistor through the
second resistor.
12. A reference voltage circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line, wherein the
current mirror circuit includes a first resistor having one end
connected to a fourth node, and the other end connected to the
ground line, a first transistor connected between a first node and
the second node, and having a control terminal connected to the
first node and a second node, and a second transistor connected
between a third node and the fourth node, and having a control
terminal connected to the second node, the reference voltage
circuit being self-biased to constitute a reference current
circuit, and including a second resistor having one end connected
to the fourth node, and the other end connected to a fifth node,
the third transistor connected between the fifth node and the
ground line, and having a control terminal connected to the fifth
node, and a third resistor having one end connected to the fourth
node, and the other end connected to the ground line, and an output
voltage being obtained by supplying an output current of the
reference current circuit to paths of the third transistor and the
third resistor through the second resistor.
13. A reference voltage circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line, wherein the
current mirror circuit includes a first resistor having one end
connected to a second node, and the other end connected to the
ground line, a first transistor connected between a first node and
the second node, and having a control terminal connected to the
first node and a third node, and a second transistor connected
between a fourth node and the ground line, and having a control
terminal connected to the third node, the third transistor
connected between a fifth node and the ground line drives a
reference transistor of the current mirror circuit for setting a
current source for driving the first and second transistors as a
mirror current, and constitutes a negative feedback current loop,
and the reference voltage circuit including a second resistor
having one end connected to the fourth node, and the other end
connected to the fifth node, the third transistor connected between
the fifth node and the ground line, and having a control terminal
connected to the fifth node, and a third resistor having one end
connected to the fourth node, and the other end connected to the
ground line, and an output voltage being obtained by supplying an
output current proportional to a current of the current source for
driving the first and second transistors to paths of the third
transistor and the third resistor through the second resistor.
14. A reference voltage circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line, wherein the
current mirror circuit includes a first resistor having one end
connected to a first node, and the other end connected to a second
node, a first transistor connected between the second node and the
ground line, and having a control terminal connected to the first
node, and a second transistor connected between a third node and
the ground line, and having a control terminal connected to the
second node, and the third transistor connected between a fifth
node and the ground line wire drives a reference transistor of the
current mirror circuit for setting a current source for driving the
first and second transistors as a mirror current, and constitutes a
negative feedback current loop, the reference voltage circuit
including a second resistor having one end connected to a fourth
node, and the other end connected to the fifth node, the third
transistor connected between the fifth node and the ground line,
and having a control terminal connected to the fifth node, and a
third resistor having one end connected to the fourth node, and the
other end connected to the ground line, and an output voltage being
obtained by supplying an output current proportional to a current
of the current source for driving the first and second transistors
to paths of the third transistor and the third resistor through the
second resistor.
15. A reference voltage circuit comprising: a power supply line; a
ground line; a current mirror circuit installed between the power
supply line and the ground line; and a third transistor connected
between the power supply line and the ground line, wherein the
current mirror circuit includes a first resistor having one end
connected to a fourth node, and the other end connected to the
ground line, a first transistor connected between a first node and
the ground line, and having a control terminal connected to the
first node and a second node, and a second transistor connected
between a third node and the fourth node, and having a control
terminal connected to the second node, and the third transistor
connected between a fifth node and the ground line drives a
reference transistor of the current mirror circuit for setting a
current source for driving the first and second transistors as a
mirror current, and constitutes a negative feedback current loop,
the reference voltage circuit including a second resistor having
one end connected to the fourth node, and the other end connected
to the fifth node, the third transistor connected between the fifth
node and the ground line, and having a control terminal connected
to the fifth node, and a third resistor having one end connected to
the fourth node, and the other end connected to the ground line,
and an output voltage being obtained by supplying an output current
proportional to a current of the current source for driving the
first and second transistors to paths of the third transistor and
the third resistor through the second resistor.
16. A reference voltage circuit according to any one of claims 11
to 15, wherein an output circuit composed of a fourth transistor
having a control terminal connected through the second resistor to
a current input terminal, and a current output terminal connected
to the ground line, and the third resistor having one terminal
connected to the ground line, and the current mirror circuit for
driving the output circuit are series-connected by n stages, and n
output voltages are outputted.
17. A reference voltage circuit according to any one of claims 11
to 15, wherein an output circuit composed of a fourth transistor
having a control terminal connected through the second resistor to
a current input terminal, and a current output terminal connected
to the ground line, and the third resistor having one terminal
connected to the ground line is series-connected by n stages, and n
output voltages are outputted by sharing a circuit current.
18. A reference current circuit according to any one of claims 1 to
9, wherein the first to third transistors are bipolar
transistors.
19. A reference current circuit according to any one of claims 1 to
9, the first to third transistors are field-effect transistors.
20. A reference voltage circuit according to any one of claims 10
to 17, wherein the first to third transistors are bipolar
transistors.
21. A reference voltage circuit according to any one of claims 10
to 17, wherein the first to third transistors are field-effect
transistors.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reference current circuit and a
reference voltage circuit. More particularly, the present invention
relates to a bipolar or CMOS reference current circuit formed on a
semiconductor integrated circuit, adapted to prevent an appearance
of an effect of an early voltage, and operated from a low voltage
to output a reference current having a positive temperature
characteristic, alternatively to a bipolar or CMOS reference
current circuit for outputting a reference current having an
optional temperature characteristic. Furthermore, the present
invention relates to a bipolar or CMOS reference voltage circuit
operated from a low voltage to output a low reference voltage
having no temperature characteristics.
2. Description of the Prior Art
First, description will be made of a conventional art regarding a
reference current circuit. A reference current circuit has
conventionally been available, which is adapted to prevent an
appearance of an effect of such an early voltage, and output a
reference current having a fixed temperature characteristic.
Examples are a bipolar reference current circuit described in
Japanese Patent Application Laid-Open No. 191629/1984, and a
bipolar reference current circuit and a CMOS reference voltage
circuit described in Japanese Patent Application Laid-Open No.
200086/1995.
Now, an operation of the conventional bipolar reference current
circuit will be described.
FIG. 1 shows the bipolar reference current circuit described in
Japanese Patent Application Laid-Open No. 191629/1984, which is
generally called a proportional to absolute temperature (PTAT)
current source circuit because it outputs a current proportional to
a temperature. However, the PTAT current source circuit shown in
FIG. 1 is adapted to prevent an appearance of an effect of an early
voltage. It is because collectors of respective transistors Q5 and
Q6 are connected to bases of respective transistors Q3 and Q4 and,
by setting currents flowing to the transistors Q3 and Q4 equal to
each other, base baias voltages of the transistors Q3 and Q4 can be
set equal to each other, and thus collector voltages of the
transistors Q5 and Q6 are set equal to each other.
In FIG. 1, the transistors Q2 and Q3 are set as unit transistors,
and an emitter area ratio of a transistor Q1 is set to be K.sub.1
times (K.sub.1 >1) as large as that of the unit transistor.
Here, if base width modulation is ignored, a relation between a
collector current I.sub.C of the transistor and a voltage V.sub.BE
between the base and an emitter is represented by the following
equation (1):
In this case, I.sub.S denotes a saturation current of the unit
transistor; and V.sub.T a thermal voltage, which is represented by
V.sub.T =kT/q. Here, q denotes a unit electron charge; k Boltzmann
constant; T absolute temperature; and K an emitter area ratio with
respect to the unit transistor.
Assuming that a DC current amplification factor of the transistor
is sufficiently near 1, by ignoring a base current, in the bipolar
inverse Widlar current mirror circuit, from the equation (1),
relations thus established are represented by the following
equations:
Now, by solving the equation (4) from the equation (1), a relation
of an input/output current of the bipolar inverse Widlar current
mirror circuit is obtained by the following equation (5):
FIG. 2 shows an input/output characteristic of the bipolar inverse
Widlar current mirror.
In this case, the transistor Q3 drives the transistor Q4. The
transistor Q4 constitutes a current mirror circuit having a current
mirror ratio of 1:1 with the transistors Q5 and Q6. Since the
transistors Q1 and Q2 are respectively driven by the transistors Q5
and Q6, the bipolar self-biased inverse Widlar reference current
circuit is provided, and a relation is represented by the following
equation (6):
In the bipolar inverse Widlar current mirror circuit, a mirror
current I.sub.C2 is exponentially increased with respect to an
increase of a reference current I.sub.C1. Thus, if an operation
point is (I.sub.p =(V.sub.T /R.sub.1)ln K.sub.1 =I.sub.C1
=I.sub.C2), then I.sub.C1 >I.sub.C2 is established with I.sub.p
>I.sub.C1, and I.sub.C1 <I.sub.C2 is established with I.sub.p
<I.sub.C1. Accordingly, when Ip+.DELTA.I (.DELTA.I>0) is
supplied to the transistors Q4 to Q6, I.sub.C4 =I.sub.C6 =I.sub.C1
=Ip+.DELTA.I is established. However, since I.sub.C2 >I.sub.C5
=Ip+.DELTA.I is established to cause a shortage of current supplied
from the transistor Q5, the base current of the transistor Q3 is
pulled, and the transistor Q3 turns off. Thus, a current flowing to
the transistor Q3 is reduced, and currents of the transistors Q4 to
Q6 are also reduced to return to IP. Conversely, when I.sub.p
-.DELTA.I (.DELTA.I>0) is supplied to the transistors Q4 to Q6,
I.sub.C4 =I.sub.C6 =I.sub.C1 =I.sub.p -.DELTA.I is established.
However, since I.sub.C2 <I.sub.C5 =Ip-.DELTA.I is established to
cause a current supplied from the transistor Q5 to be excessive, a
current is pushed into the base of the transistor Q3, and the
transistor Q3 turns on. Accordingly, a current flowing to the
transistor Q3 is increased, and currents of the transistors Q4 to
Q6 are also increased to return to I.sub.p. That is, a negative
feedback current loop is constituted, an operation point is
uniquely decided with I.sub.C1 >0, realizing a stable
operation.
In addition, since the following equation (7) is established,
##EQU1##
an equation (8) is obtained:
Here, K.sub.1 denotes a constant having no temperature
characteristics and, as described above, the thermal voltage
V.sub.T is represented by V.sub.T =kT/q, exhibiting a temperature
characteristic of 3333 ppm/.degree. C. Accordingly, if a
temperature characteristic of a resistor R1 is smaller than that of
the thermal voltage V.sub.T, exhibiting a primary characteristic
with respect to a temperature, an output current I.sub.0 of the
reference current circuit outputted through the current mirror
circuit is proportional to the temperature, realizing a PTAT
current source circuit. In this case, since currents flowing to the
transistors Q1 to A3 are all equal to one another, base bias
voltages of the transistors Q2 and Q3 are also equal to each other.
Thus, since collector voltages of the transistors Q5 and Q6 are
fixed with these base bias voltages of the transistors Q2 and Q3,
and equally set, no effects of Early voltages of the transistors Q1
and Q2 appear. Since no changes occur in a desired current mirror
ratio even if the collector voltages of the transistors Q5 and Q6
are changed to cause an appearance of effects of Early voltages, a
highly accurate current output having only small changes with
respect to fluctuation in a power supply voltage is obtained.
Next, a conventional art regarding a reference voltage circuit will
be described. A reference voltage circuit having no temperature
characteristics because of cancellation, and adapted to output a
reference voltage of 1.2 V or lower has conventionally been
available. An example is described in IEEE Journal of Solid-State
Circuits, Vol. 32, No. 11, pp.1790 to 1806, November 1997.
First, an operation of this exemplary reference voltage circuit
will be described. FIG. 3 shows the reference voltage circuit
described in IEEE Journal of Solid-State Circuits, Vol. 32, No. 11,
pp. 1790 to 1806, November 1997. A current proportional to a
temperature is generally outputted. Thus, an output current of a
reference current circuit called a proportional to absolute
temperature (PTAT) current source circuit is supplied into an
output circuit, where it is converted into a voltage and set as a
reference voltage.
In FIG. 3, transistors Q1 and Q2 are set as unit transistors, and
an emitter area ratio of the transistor Q2 is set to be K.sub.1
times (K.sub.1 >1) as large as that of the unit transistor. If
the base width modulation is ignored, then a relation between a
collector current I.sub.C of the transistor, and a voltage V.sub.BE
between the base and an emitter is represented by the following
equation (9):
In this case, I.sub.S denotes a saturation current of the unit
transistor; and V.sub.T the thermal voltage, which is represented
by V.sub.T =kT/q. Here, q denotes a unit electron charge; k
Boltzmann constant; T absolute temperature; and K an emitter area
ratio with respect to the unit transistor.
Assuming that a DC current amplification factor of the transistor
is sufficiently near 1, if a base current is ignored, relations
thus established are represented by the following equations (10) to
(12):
A solution of the equation (12) from the equation (10) is
represented by the following equation (13):
In this case, since a common gate voltage of transistors M4 and M5
are controlled through an operation amplifier to establish the
equation (12), the transistors Q1 and Q2 are self-biased, which is
represented by the following equation (14).
Accordingly, the equation (13) is obtained by the following
equation (15):
In addition, a transistor M6 constitutes a current mirror circuit
with the transistors M4 and M5, the following equation (16) is
established:
A drain current I.sub.D6 of the transistor M6 is converted into a
voltage by the output circuit, and set as a reference voltage
V.sub.REF. Assuming that a current flowing to a resistor R2 is
.gamma.I.sub.D6 (0<.gamma.<1), the reference voltage is
represented by the following equation (17):
A solution .gamma. of the equation (17) is represented by the
following equation (18):
Accordingly, the reference voltage V.sub.REF is obtained by the
following equation (19): ##EQU2##
In this case, a coefficient term R.sub.3 /(R.sub.2 +R.sub.3) of the
equation (19) is 0<R.sub.3 /(R.sub.2 +R.sub.3)<1. Regarding a
second term of {V.sub.BE3 +(R.sub.2 /R.sub.1)V.sub.T ln(K1)},
V.sub.BE3 has a negative temperature characteristic of about -1.9
mV/.degree. C., and the thermal voltage V.sub.T has a positive
temperature characteristic of 0.0853 mV/.degree. C. Accordingly, in
order to prevent a reference voltage V.sub.REF to be outputted from
having no temperature characteristics, temperature characteristics
are cancelled each other between a voltage having a positive
temperature characteristic and a voltage having a negative
temperature characteristic. That is, in this case, a value of
(R.sub.2 /R.sub.1)ln(K1) is 22.3, and a voltage value of (R.sub.2
/R.sub.1)V.sub.T ln(K1) is 0.57 V. Now, if V.sub.BE3 is 0.7 V, then
{V.sub.BE3 +(R.sub.2 /R.sub.1)V.sub.T ln(K1)}=1.27 V is obtained.
Thus, since R.sub.3 /(R.sub.2 +R.sub.3)<1 is established, the
reference voltage V.sub.REF can be set to a value equal to 1.27 V
or lower, e.g., 1.0 V.
However, the following problems are inherent in the conventional
reference current circuit.
Conventionally, in the reference current circuit for outputting a
reference current having a positive temperature characteristic
similar to the above, a non-linear current mirror circuit was used
for the PTAT current source circuit, and prevention of an
appearance of an effect of an early voltage was achieved only by
using the foregoing Widlar current mirror circuit or the Widlar
current mirror circuit described in the other embodiment of
Japanese Patent Application Laid-Open No. 191629/1984 as the
non-linear current mirror circuit.
In addition, it is difficult to provide a reference current circuit
having an optional temperature characteristic, adapted to prevent
an appearance of an effect of an early voltage, by a currently
available technology.
Reference current circuits are usually used for bias currents in
circuits of an LSI including an analog LSI, a digital LSI such as a
memory, and many other kinds of an LSI. Especially, the reference
current circuit for outputting a current proportional to a
temperature is generally called a PTAT current source circuit.
However, higher integration of an LSI has made a process more
detailed, lowering a power supply voltage. At present, therefore,
other than the reference current circuit having a positive
temperature characteristic, a reference current circuit having an
optional temperature characteristic is requested. For example, a
reference voltage circuit can be easily realized by converting an
output current of a reference current circuit having no temperature
characteristics into a voltage through a resistor, and an output
voltage of an optional value can be obtained. The reference voltage
circuit having no temperature characteristics is generally called a
band gap reference voltage circuit, and its output voltage is near
a band gap voltage 1.205 V of silicon (Si) at absolute zero. Thus,
a normal operation is no longer possible by a nominal output
voltage 1.2 V of a nickel-hydrogen battery or a nickel-cadmium
battery as a currently most general secondary battery.
Next, problems inherent in the conventional reference voltage
circuit will be described. Conventionally, in the reference voltage
circuit for outputting a reference voltage having no temperature
characteristics, since an operation amplifier was used for a
feedback circuit of the PTAT current source circuit, operation was
difficult by a low power supply voltage. That is, reference voltage
circuits are usually used for bias currents in circuits of an LSI
including an analog LSI, a digital LSI such as memory devices, and
many other kinds of an LSI. Especially, the reference voltage
circuit for outputting a voltage having no temperature
characteristics is generally called a band gap reference voltage
circuit. Its output voltage is near a band gap voltage 1.205 V of
silicon (Si) at absolute zero.
However, higher integration of an LSI has made a process more
detailed, lowering a power supply voltage. At present, therefore, a
normal operation is no longer possible by a low nominal output
voltage of about 1.2 V of a nickel-hydrogen battery or a
nickel-cadmium battery as a current most general battery.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a reference
current circuit operated from a low power supply voltage of about 1
V, and adapted to output a current having a positive or optional
temperature characteristic. Specifically, the object of the present
invention is to provide a PTAT current source circuit using the
Nagata current mirror circuit, and adapted to prevent an appearance
of an effect of an early voltage, and a reference current circuit
having an optional temperature characteristic by using the PTAT
current source circuit thus obtained.
Another object of the present invention is to provide a reference
voltage circuit operated from a low power supply voltage of about
0.9 V, and adapted to output a voltage having no temperature
characteristics by simple and small circuitry.
In accordance with a first aspect of the present invention, there
is provided a reference current circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between between the power supply line and the ground
line. In this case, the current mirror circuit includes a first
resistor having one end connected to a first node, and the other
end connected to a second node, a first transistor connected
between the second node and the ground line, and having a control
terminal connected to the first node, and a second transistor
connected between a third node and the ground line, and having a
control terminal connected to the second node, and the third
transistor has a control terminal connected to the third node,
drives the current mirror circuit for setting a current source for
driving the first and second transistors as a mirror current, and
constitutes a negative feedback current loop.
In accordance with a second aspect of the present invention, there
is provided a reference current circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between the power supply line and the ground line. In
this case, the current mirror circuit includes a first resistor
having one end connected to a second node, and the other end
connected to the ground line, a first transistor connected between
the first and second nodes, and having a control terminal connected
to the first node, and a third node, and a second transistor
connected between a fourth node and the ground line, and having a
control terminal connected to the third node, and the third
transistor has a control terminal connected to the third node,
drives the current mirror circuit for setting a current source for
driving the first and second transistors as a mirror current, and
constitutes a negative feedback current loop.
In accordance with a third aspect of the present invention, there
is provided a reference current circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between the power supply line and the ground line. In
this case, the current mirror circuit includes a first resistor
having one end connected to a fourth node, and the other end
connected to the ground line, a first transistor connected between
a first node and the ground line, and having a control terminal
connected to each of the first node and a second node, and a second
transistor connected between a third node and the fourth node, and
having a control terminal connected to the second node, and the
third transistor has a control terminal connected to the third
node, drives the current mirror circuit for setting a current
source for driving the first and second transistors as a mirror
current, and constitutes a negative feedback current loop.
In accordance with a fourth aspect of the present invention, there
is provided a reference current circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between the power supply line and the ground line; and
second and third resistors. In this case, the current mirror
circuit includes a first resistor having one end connected to a
second node, and the other end connected to the ground line, a
first transistor connected between the first and second nodes, and
having a control terminal connected to the first node and a third
node, and a second transistor connected between a fourth node and
the ground line, and having a control terminal connected to the
third node, the second resistor has one end connected to the first
node, and the other end connected to the ground line, the third
resistor has one end connected to the fourth node, and the other
end connected to the ground line, and the third transistor has a
control terminal connected to the fourth node, drives the current
mirror circuit for setting a current source for driving the first
and second transistors as a mirror current, and constitutes a
negative feedback current loop.
In accordance with a fifth aspect of the present invention, there
is provided a reference current circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between the power supply line and the ground line; and
second and third resistors. In this case, the current mirror
circuit includes a first resistor having one end connected to a
first node, and the other end connected to a second node, a first
transistor connected between the second node and the ground line,
and having a control terminal connected to the first node and a
third node, and a second transistor connected between the third
node and the ground line, and having a control terminal connected
to the second node, the second resistor has one end connected to
the first node, and the other end connected to the ground line, the
third resistor has one end connected to the third node, and the
other end connected to the ground line, and the third transistor
has a control terminal connected to the third node, drives the
current mirror circuit for setting a current source for driving the
first and second transistors as a mirror current, and constitutes a
negative feedback current loop.
In accordance with a sixth aspect of the present invention, there
is provided a reference current circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; a third transistor connected
between the power supply line and the ground line; and second and
third resistors. In this case, the current mirror circuit includes
a first resistor having one end connected to a fourth node, and the
other end connected to a second node, a first transistor connected
between a first node and the ground line, and having a control
terminal connected to the first and second nodes, and a second
transistor connected between a third node and the fourth node, and
having a control terminal connected to the second node, the second
resistor has one end connected to the first node, and the other end
connected to the ground line, the third resistor has one end
connected to the third node, and the other end connected to the
ground line, and the third transistor has a control terminal
connected to the third node, drives the current mirror circuit for
setting a current source for driving the first and second
transistors as a mirror current, and constitutes a negative
feedback current loop.
Furthermore, the reference current circuit of the present invention
may employ various suitable application forms described below.
A current outputted from the reference current circuit is supplied
into a fifth resistor. The fifth resistor includes a plurality of
resistors connected in series.
In addition, according to the reference current circuit of the
present invention, a current of the third transistor is set to be
substantially inversely proportional to a temperature, a current
mirror circuit current flowing to the transistor of the current
mirror circuit and the current of the third transistor are weighted
and added, and an output current having a fixed temperature
characteristic is obtained.
In accordance with a seventh aspect of the present invention, there
is provided a reference voltage circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between the power supply line and the ground line. In
this case, the current mirror circuit includes a first resistor
having one end connected to a second node, and the other end
connected to the ground line, a first transistor connected between
a first node and the second node, and having a control terminal
connected to the first node and a third node, and a second
transistor connected between a fourth node and the ground line, and
having a control terminal connected to the third node, the
reference voltage circuit being self-biased to constitute a
reference current circuit, and including a second resistor having
one end connected to a fourth node, and the other end connected to
a fifth node, the third transistor connected between the fifth node
and the ground line, and having a control terminal connected to the
fifth node, and a third resistor having one end connected to the
fourth node, and the other end connected to the ground line, and an
output voltage being obtained by supplying an output current of the
reference current circuit to paths of the third transistor and the
third resistor through the second resistor.
In accordance with an eighth aspect of the present invention, there
is provided a reference voltage circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between the power supply line and the ground line. In
this case, the current mirror circuit includes a first resistor
having one end connected to a first node, and the other end
connected to a second node, a first transistor connected between
the second node and the ground line, and having a control terminal
connected to the first node, and a second transistor connected
between a third node and the ground line, and having a control
terminal connected to the second node, the reference voltage
circuit being self-biased to constitute a reference current
circuit, and including a second resistor having one end connected
to a fourth node, and the other end connected to a fifth node, the
third transistor connected between the fifth node and the ground
line, and having a control terminal connected to the fifth node,
and a third resistor having one end connected to the fourth node,
and the other end connected to the ground line, and an output
voltage being obtained by supplying an output current of the
reference current circuit to paths of the third transistor and the
third resistor through the second resistor.
In accordance with a ninth aspect of the present invention, there
is provided a reference voltage circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between the power supply line and the ground line. In
this case, the current mirror circuit includes a first resistor
having one end connected to a fourth node, and the other end
connected to the ground line, a first transistor connected between
a first node and the second node, and having a control terminal
connected to the first node and a second node, and a second
transistor connected between a third node and the fourth node, and
having a control terminal connected to the second node, the
reference voltage circuit being self-biased to constitute a
reference current circuit, and including a second resistor having
one end connected to the fourth node, and the other end connected
to a fifth node, the third transistor connected between the fifth
node and the ground line, and having a control terminal connected
to the fifth node, and a third resistor having one end connected to
the fourth node, and the other end connected to the ground line,
and an output voltage being obtained by supplying an output current
of the reference current circuit to paths of the third transistor
and the third resistor through the second resistor.
In accordance with a tenth aspect of the present invention, there
is provided a reference voltage circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between the power supply line and the ground line. In
this case, the current mirror circuit includes a first resistor
having one end connected to a second node, and the other end
connected to the ground line, a first transistor connected between
a first node and the second node, and having a control terminal
connected to the first node and a third node, and a second
transistor connected between a fourth node and the ground line, and
having a control terminal connected to the third node, the third
transistor connected between a fifth node and the ground line
drives a reference transistor of the current mirror circuit for
setting a current source for driving the first and second
transistors as a mirror current, and constitutes a negative
feedback current loop, and the reference voltage circuit including
a second resistor having one end connected to the fourth node, and
the other end connected to the fifth node, the third transistor
connected between the fifth node and the ground line, and having a
control terminal connected to the fifth node, and a third resistor
having one end connected to the fourth node, and the other end
connected to the ground line, and an output voltage being obtained
by supplying an output current proportional to a current of the
current source for driving the first and second transistors to
paths of the third transistor and the third resistor through the
second resistor.
In accordance with an eleventh aspect of the present invention,
there is provided a reference voltage circuit, comprising: a power
supply line; a ground line; a current mirror circuit installed
between the power supply line and the ground line; and a third
transistor connected between the power supply line and the ground
line. In this case, the current mirror circuit includes a first
resistor having one end connected to a first node, and the other
end connected to a second node, a first transistor connected
between the second node and the ground line, and having a control
terminal connected to the first node, and a second transistor
connected between a third node and the ground line, and having a
control terminal connected to the second node, and the third
transistor connected between a fifth node and the ground line wire
drives a reference transistor of the current mirror circuit for
setting a current source for driving the first and second
transistors as a mirror current, and constitutes a negative
feedback current loop, the reference voltage circuit including a
second resistor having one end connected to a fourth node, and the
other end connected to the fifth node, the third transistor
connected between the fifth node and the ground line, and having a
control terminal connected to the fifth node, and a third resistor
having one end connected to the fourth node, and the other end
connected to the ground line, and an output voltage being obtained
by supplying an output current proportional to a current of the
current source for driving the first and second transistors to
paths of the third transistor and the third resistor through the
second resistor.
In accordance with a twelfth aspect of the present invention, there
is provided a reference voltage circuit, comprising: a power supply
line; a ground line; a current mirror circuit installed between the
power supply line and the ground line; and a third transistor
connected between the power supply line and the ground line. In
this case, the current mirror circuit includes a first resistor
having one end connected to a fourth node, and the other end
connected to the ground line, a first transistor connected between
a first node and the ground line, and having a control terminal
connected to the first node and a second node, and a second
transistor connected between a third node and the fourth node, and
having a control terminal connected to the second node, and the
third transistor connected between a fifth node and the ground line
drives a reference transistor of the current mirror circuit for
setting a current source for driving the first and second
transistors as a mirror current, and constitutes a negative
feedback current loop, the reference voltage circuit including a
second resistor having one end connected to the fourth node, and
the other end connected to the fifth node, the third transistor
connected between the fifth node and the ground line, and having a
control terminal connected to the fifth node, and a third resistor
having one end connected to the fourth node, and the other end
connected to the ground line, and an output voltage being obtained
by supplying an output current proportional to a current of the
current source for driving the first and second transistors to
paths of the third transistor and the third resistor through the
second resistor.
The reference voltage circuit of the present invention may employ
various suitable application forms described below.
That is, an output circuit composed of a fourth transistor having a
control terminal connected through the second resistor to a current
input terminal, and a current output terminal connected to the
ground line, and the third resistor having one terminal connected
to the ground line, and the current mirror circuit for driving the
output circuit are series-connected by n stages, and n output
voltages are outputted.
According to the reference voltage circuit of the present
invention, an output circuit composed of a fourth transistor having
a control terminal connected through the second resistor to a
current input terminal, and a current output terminal connected to
the ground line, and the third resistor having one terminal
connected to the ground line is series-connected by n stages, and n
output voltages are outputted by sharing a circuit current.
According to the reference current circuit of the present
invention, the first to third transistors are bipolar
transistors.
According to the reference current circuit of the present
invention, the first to third transistors are field-effect
transistors.
According to the reference voltage circuit of the present
invention, the first to third transistors are bipolar
transistors.
Furthermore, according to the reference voltage circuit of the
present invention, the first to third transistors are field-effect
transistors.
According to the reference current circuit of the present
invention, in the non-linear current mirror circuit composed of the
two transistors having different voltages between bases and
emitters (or between gates and sources), self-biasing sets a
collector (or drain) current of each to be a current I.sub.PTAT
proportional, or substantially proportional to a temperature. On
the other hand, the voltage between the base and the emitter (or
between the gate and the source) has a negative temperature
characteristic. Thus, a current proportional to the voltage between
the base and the emitter (or between the gate and the source) is
set to be a current I.sub.IPTAT substantially inversely
proportional to the temperature.
Therefore, by weighting and adding the current I.sub.PTAT flowing
to the transistor of the non-linear current mirror circuit, and the
current I.sub.IPTAT proportional to the current between the base
and the emitter (or between the gate and the source), an output
current I.sub.REF (=I.sub.PTAT +I.sub.IPTAT) having a fixed
temperature characteristic is obtained. Moreover, by converting the
output current IREF into a voltage, a reference voltage circuit for
outputting an optional voltage value having a fixed temperature
characteristic can be provided.
However, in the conventional reference voltage circuit, by
weighting and adding a voltage V.sub.PTAT proportional to an
absolute temperature, and a voltage V.sub.IPTAT inversely
proportional to the absolute temperature, a reference voltage
circuit having a fixed temperature characteristic is provided.
Thus, in the conventional reference voltage circuit, an operation
power supply voltage exceeding V.sub.PTAT +V.sub.IPTAT (=1.2 V),
e.g., 1.4 V or higher, was necessary. According to the present
invention, however, a stable operation is provided even by a lower
power supply voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a view showing an example of a conventional highly
accurate bipolar PTAT reference current circuit, using a highly
accurate bipolar self-biased inverse Widlar reference current
circuit.
FIG. 2 is a view showing an input/output characteristic of the
conventional bipolar inverse Widlar current mirror circuit.
FIG. 3 is a view showing a conventional reference voltage circuit
using an operation amplifier.
FIG. 4 is a view showing an example of a reference current circuit
according to a first embodiment of the present invention, using a
highly accurate bipolar self-biased Nagata reference current
circuit.
FIG. 5 is a view showing an input/output characteristic of the
bipolar Nagata current mirror circuit.
FIG. 6 is a view showing an example of the reference current
circuit of the first embodiment of the present invention, using a
highly accurate CMOS self-biased Nagata reference current
circuit.
FIG. 7 is a view showing an input/output characteristic of the MOS
Nagata current mirror circuit.
FIG. 8 is a view showing a temperature characteristic of an inverse
number 1/.beta. of a transconductance parameter.
FIG. 9 is a view showing an example of a reference current circuit
according to a second embodiment of the present invention, using a
highly accurate CMOS self-biased inverse Widlar reference current
circuit.
FIG. 10 is a view showing an input/output characteristic of the MOS
inverse Widlar current mirror circuit.
FIG. 11 is a view showing an example of a reference current circuit
according to a third embodiment of the present invention, using a
highly accurate bipolar self-biased Widlar reference current
circuit.
FIG. 12 is a view showing an input/output characteristic of the
bipolar Widlar current mirror circuit.
FIG. 13 is a view showing an example of the reference current
circuit of the third embodiment of the present invention, using a
highly accurate CMOS self-biased Widlar reference current
circuit.
FIG. 14 is a view showing an input/output characteristic of the MOS
Widlar current mirror circuit.
FIG. 15 is a view showing an example of a reference current circuit
according to a fourth embodiment of the present invention, using a
bipolar inverse Widlar reference current circuit.
FIG. 16 is a view showing an example of the reference current
circuit of the fourth embodiment of the present invention, using a
CMOS inverse Widlar reference current circuit.
FIG. 17 is a view showing an example of a reference current circuit
according to a fifth embodiment of the present invention, using a
bipolar Nagata reference current circuit.
FIG. 18 is a view showing an example of the reference current
circuit of the fifth embodiment of the present invention, using a
CMOS Nagata reference current circuit.
FIG. 19 is a view showing an example of a reference current circuit
according to a sixth embodiment of the present invention, using a
bipolar Widlar reference current circuit.
FIG. 20 is a view showing an example of the reference current
circuit of the sixth embodiment of the present invention, using a
CMOS Widlar reference current circuit.
FIG. 21 is a view showing an example of a reference voltage circuit
according to a seventh embodiment of the present invention, using a
bipolar self-biased inverse Widlar reference current circuit.
FIG. 22 is a view showing an example of the reference voltage
circuit of the seventh embodiment of the present invention, using a
CMOS self-biased inverse Widlar reference current circuit.
FIG. 23 is a view showing an example of a reference voltage circuit
according to an eighth embodiment of the present invention, using a
bipolar self-biased Nagata Widlar reference current circuit.
FIG. 24 is a view showing an example of the reference voltage
circuit of the eight embodiment of the present invention, using a
CMOS self-biased Nagata Widlar reference current circuit.
FIG. 25 is a view showing an example of a reference voltage circuit
according to a ninth embodiment of the present invention, using a
bipolar self-biased Widlar reference current circuit.
FIG. 26 is a view showing an example of the reference voltage
circuit of the ninth embodiment of the present invention, using a
CMOS self-biased Widlar reference current circuit.
FIG. 27 is a view showing an example of a reference voltage circuit
according to a tenth embodiment of the present invention, using a
bipolar self-biased inverse Widlar reference current circuit.
FIG. 28 is a view showing an example of the reference voltage
circuit of the tenth embodiment of the present invention, using a
CMOS self-biased inverse Widlar reference current circuit.
FIG. 29 is a view showing an example of a reference voltage circuit
according to an eleventh embodiment of the present invention, using
a bipolar self-biased Nagata Widlar reference current circuit.
FIG. 30 is a view showing an example of the reference voltage
circuit of the eleventh embodiment of the present invention, using
a CMOS self-biased Nagata Widlar reference current circuit.
FIG. 31 is a view showing an example of a reference voltage circuit
according to a twelfth embodiment of the present invention, using a
bipolar self-biased Widlar reference current circuit.
FIG. 32 is a view showing an example of the reference voltage
circuit of the twelfth embodiment of the present invention, using a
CMOS self-biased Widlar reference current circuit.
FIG. 33 is a view showing an example of a circuit, where any one of
the reference voltage circuits of the seventh to twelfth
embodiments of the present invention is series-connected.
FIG. 34 is a view showing an example of a circuit, where any one of
the reference voltage circuits of the seventh to twelfth
embodiments of the present invention is series-connected.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Next, description will be made of the preferred embodiments of the
present invention, specifically those of reference current and
voltage circuits in a divided manner. First, the embodiments of the
reference current circuits of the present invention will be
described with reference to the accompanying drawings.
FIG. 4 is a view showing an example of a reference current circuit
according to a first embodiment of the present invention,
specifically an embodiment of a bipolar reference current
circuit.
Referring to FIG. 4, the reference current circuit of the first
embodiment of the present invention is shown to be constructed in a
manner that transistors Q1 and Q2, and a resistor R1 constitute the
bipolar Nagata current mirror circuit, and transistors Q4, Q5,
(Q6), and a resistor R4 constitute the bipolar Nagata current
mirror circuit. In this case, by the transistors Q5 and Q6, the
transistors Q1 and Q2, and the resistor R1 constitute the bipolar
self-biased Nagata reference current circuit.
In the bipolar Nagata current mirror circuit constituted of the
transistors Q4, Q5, (Q6) and the resistor R4, a circuit constant is
set such that when a current of the transistor Q3 to be driven is
increased, currents flowing to the transistors Q5 and Q6 can be
reduced. Thus, in the bipolar self-biased Nagata reference current
circuit, a negative feedback current loop is formed in the circuit,
enabling the circuit to be stably operated.
In the case of the bipolar self-biased Nagata reference current
circuit described in Japanese Patent Application Laid-Open No.
200086/1995, since a positive feedback current loop is formed in
the circuit, the circuit is not operated.
FIG. 5 shows an input/output characteristic of the bipolar Nagata
current mirror circuit (FIG. 4) constituted of the transistors Q1
and Q2 and the resistor R1. In the drawing, an abscissa indicates
an input current I.sub.C1, and an ordinate indicates an output
current I.sub.C2. A feature of the bipolar Nagata current mirror
circuit is that there are a region where the output current (mirror
current) I.sub.C2 is monotonously increased with respect to the
input current (reference current) I.sub.C1, a peak point, and a
region where the output current (mirror current) I.sub.C2 is
monotonously reduced with respect to the input current (reference
current) I.sub.C1. At the peak point, when the input current
(reference current) is I.sub.C1 =V.sub.T /R.sub.1, the output
current (mirror current) is I.sub.C2 =K.sub.1 V.sub.T /eR.sub.1.
Assuming that a DC current amplification factor of the transistor
is sufficiently near 1, by ignoring a base current, in the bipolar
Nagata current mirror circuit, from the equation (1), relations are
represented by the following equations (20) to (22):
Here, by solving the equations (20) to (22), a relation between the
input and output currents in the bipolar Nagata current mirror
circuit is represented by the following equation (23):
At the peak point, with R.sub.1 I.sub.C1 =V.sub.T, I.sub.C2
=K.sub.1 I.sub.C1 /e is established, where e is 2.7183.
Accordingly, with K.sub.1 =e, I.sub.C2 =I.sub.C1 is established. In
this case, the transistor Q3 drives the transistor Q4. The
transistor Q4 constitutes the bipolar Nagata current mirror circuit
with the transistor Q5 and Q6 and the resistor R4, which is
operated in the region where the output current (mirror current) is
monotonously reduced with respect to the input current (reference
current). The transistors Q1 and Q2 are respectively driven by the
transistors Q6 and Q5. Thus, the bipolar self-biased Nagata
reference current circuit is provided, and if an emitter area ratio
of the transistors Q5 and Q6 is 1:K.sub.2, then a relation is
represented by the following equation (24):
However, if the transistor Q4 is a unit transistor, an emitter area
ratio of the transistor Q5 is K.sub.3 times as large as that of the
unit transistor; and an emitter area ratio of the transistor Q6
K.sub.2 K.sub.3 times as large as that of the unit transistor. In
addition, to keep the bipolar Nagata current mirror circuit
operable in the region of a monotonous reduction, K.sub.3 >e
(=2.7183) must be set.
Therefore, since the following equation (25) is established,
##EQU3##
the equation (26) is obtained:
Here, K.sub.1 and K.sub.2 denote constants having no temperature
characteristics and, as described above, the thermal voltage
V.sub.T is represented by V.sub.T =kT/q, exhibiting a temperature
characteristic of 3333 ppm/.degree. C. Accordingly, if a
temperature characteristic of the resistor R1 is smaller than the
temperature characteristic of the thermal voltage V.sub.T, being a
primary characteristic with respect to a temperature, an output
current I.sub.0 (=I.sub.C1) of the reference current circuit
outputted through the current mirror circuit is proportional to the
temperature, realizing a PTAT current source circuit.
To make currents flowing to the transistors Q1 and Q3 equal to each
other, the emitter area ratios K1, K2 and K3, and values of the
resistors R1 and R4 are set. Thus, base bias voltages of the
transistors Q1 and Q3 are substantially equal to each other, fixing
and setting collector voltages of the transistors Q1 and Q3 to be
equal to each other. As a result, no effects of Early voltages of
the transistors Q1 and Q2 appear, and no changes occur in a desired
current mirror ratio even if the collector voltages of the
transistors Q5 and Q6 are changed to cause an appearance of effects
of Early voltages, making it possible to obtain a highly accurate
current output having only a small change with respect to
fluctuation in a power supply voltage. Moreover, even when the
currents flowing to the transistors Q1 and Q3 are not equal to each
other, the collector voltages of the transistors Q1 and Q2 are
fixed by at least the base bias voltages of the transistors Q1 and
Q3, and a fluctuation extent is limited, and thus almost no effects
of Early voltages (base width modulation) of the transistors Q1 and
Q2 appear.
FIG. 6 shows the reference current circuit of the first embodiment
of the present invention, specifically a CMOS reference current
circuit of another embodiment. In the reference current circuit of
the first embodiment of the present invention, transistors M1 and
M2 and a resistor R1 constitute the Nagata current mirror circuit
and, similarly, transistors M4, and M5 (M6), and a resistor R4
constitute the Nagata current mirror circuit. In this case, by the
transistors M5 and M6 constituting a current source, the
transistors M1 and M2 and the resistor R1 constitute the
self-biased Nagata reference current circuit. In addition, the MOS
Nagata reference current circuit constituted of the transistors M4
and M5 (M6), and the resistor R4 has a circuit constant set such
that when a current of a transistor M3 to be driven is increased,
currents flowing to the transistors M5 and M6 can be reduced. Thus,
in the CMOS self-biased Nagata reference current circuit, a
negative feedback current loop is formed, and the circuit is stably
operated. In the case of the CMOS self-biased Nagata reference
current circuit described in Japanese Patent Application Laid-Open
No. 200086/1995, a positive feedback current loop is formed in the
circuit, and thus the circuit is not operated.
In FIG. 6, the transistor M1 is a unit transistor, and a ratio
(W/L) of a gate width W between a gate length L of the transistor
M2 is K.sub.1 times (K.sub.1 >1) as large as that of the unit
transistor. In the MOS Nagata current mirror circuit shown in FIG.
6, if element consistency is high, the channel length modulation
and a body effect are ignored, and a relation between a drain
current and a voltage between the gate and the source of the MOS
transistor is set according to a square law, then the drain current
of the MOS transistor is represented by the following equation
(27):
Here, .beta. denotes a transconductance parameter, which is
represented by .beta.=.mu. (C.sub.OX /2) (W/L). In this case, .mu.
denotes an effective mobility of a carrier; C.sub.OX a gate oxide
capacitance per unit area; and W and L respectively a gate width
and a gate length.
A drain current of the MOS transistor M2 is represented by the
following equation (2):
Furthermore, a relation represented by the following equation (29)
is established:
Here, by solving the equations (27) to (29), a relation between
input and output currents of the MOS Nagata current mirror circuit
represented by the following equation (30) is established:
##EQU4##
FIG. 7 shows an input/output characteristic of the MOS Nagata
current mirror circuit constituted of the transistors M1 and M2 and
the resistor R1. In the drawing, an abscissa indicates an input
current I.sub.D1, and an ordinate indicates an output current
I.sub.D2. A feature of the MOS Nagata current mirror circuit is
that as in the case of the bipolar Nagata current mirror circuit,
there are a region where the output current (mirror current)
I.sub.D2 is monotonously increased with respect to the input
current (reference current) I.sub.D1, a peak point, and a region
where the output current (mirror current) I.sub.D2 is monotonously
reduced with respect to the input current (reference current)
I.sub.D1. At the peak point, with the input current (reference
current) I.sub.D1 =1/(4R.sub.1.sup.2.beta.), the output current
(mirror current) is I.sub.D2 =K.sub.1 /16R.sub.1.sup.2.beta..
Normally, I.sub.D2 =K.sub.1 I.sub.D1 /4 is set with I.sub.D1
=1/(4R.sub.1.sup.2.beta.). Accordingly, I.sub.D2 =I.sub.D1 is set
with K.sub.1 =4.
In this case, the transistor M3 drives the transistor M4. The
transistor M4 constitutes the MOS Nagata current mirror circuit
with the transistors M5 and M6 and the resistor R4, which is
operated in the region where the output current (mirror current) is
monotonously reduced with respect to the input current (reference
current). The transistors M1 and M2 are respectively driven by the
transistors M6 and M5. Thus, the MOS self-biased Nagata current
circuit is provided. If a ratio (W/L) of a gate width W between a
gate length L of the transistor M5 and a ratio (W/L) of a gate
width W between a gate length L of the transistor M6 is 1:K.sub.2,
then a relation is represented by the following equation (31):
If the transistor M4 is a unit transistor, a ratio (W/L) of a gate
width W between a gate length L of the transistor M5 is K.sub.3
times as large as that of the unit transistor; and a ratio (W/L) of
a gate width W between a gate length L of the transistor M6 K.sub.2
K.sub.3 times as large as that of the unit transistor. In addition,
to keep the MOS Nagata current mirror circuit operable in the
region of a monotonous reduction, K.sub.3 >4 must be set.
Therefore, a relation represented by the following equation (32) is
established:
By solving the equations (29) to (32), then a relation represented
by the following equation (33) is obtained: ##EQU5##
Here, K.sub.1 and K.sub.2 denote constants having no temperature
characteristics. On the other hand, since the mobility .mu. has a
temperature characteristic in the MOS transistor, temperature
dependence of the transconductance parameter .beta. is represented
by the following equation (34): ##EQU6##
Here, .beta.0 denotes a value of .beta. at a normal temperature
(300 K). Thus, a relation represented by the following equation
(35) is obtained. ##EQU7##
FIG. 8 shows a calculated value of a temperature characteristic of
1/.beta. (inverse number of the transconductance parameter) in the
circuit of FIG. 6. The temperature characteristic of 1/.beta. is
5000 ppm/.degree. C. at a normal temperature. This is 1.5 times as
large as that of a temperature characteristic 3333 ppm/.degree. C.
of the thermal voltage V.sub.T of the bipolar transistor. In other
words, an output current I.sub.REF of the CMOS reference current
circuit is represented by the following equation (36): ##EQU8##
Here, K.sub.1 and K.sub.2 denote constants having no temperature
characteristics. As described above, the temperature characteristic
of 1/.beta. is substantially proportional to a temperature, being
5000 ppm/.degree. C. at the normal temperature. This is 1.5 times
as large as that of the temperature characteristic 3333
ppm/.degree. C. of the thermal voltage V.sub.T of the bipolar
transistor. Thus, if a temperature characteristic of the resistor
R2 is equal to or lower than 5000 ppm/.degree. C., being a primary
characteristic with respect to the temperature, a drain current
I.sub.D1 has a positive temperature characteristic, and an output
current I.sub.0 of the reference current circuit outputted through
the current mirror circuit is proportional to the temperature,
realizing a PTAT current source circuit.
To make currents flowing to the transistors M1 and M3 equal to each
other, transistor size ratios (ratio (W/L) of gate width W between
gate length L (W/L)) K1, K2 and K3 are set, and values of the
resistors R1 and R4 are set. Thus, gate voltages of the transistors
M1 and M3 can be set substantially equal to each other, fixing and
setting drain voltages of the transistors M1 and M3 to be equal to
each other. As a result, no effects of the channel length
modulation of the transistors M1 and M2 appear, and no changes
occur in a desired current mirror ratio even if the drain voltages
of the transistors M5 and M6 are changed to cause an appearance of
effects of the channel length modulation, making it possible to
obtain a highly accurate current output having only a small change
with respect to fluctuation in a power supply voltage. Moreover,
even when the currents flowing to the transistors M1 and M3 are not
equal to each other, the drain voltages of the transistors M1 and
M2 are fixed by at least the. gate voltages of the transistors M1
and M3, and a fluctuation extent is limited, and thus almost no
effects of the channel length modulation of the transistors M1 and
M2 appear.
FIG. 9 shows a reference current circuit according to a second
embodiment of the present invention, specifically an embodiment of
a CMOS reference current circuit. In the reference current circuit
of the second embodiment of the present invention, transistors M1
and M2, and a resistor R1 constitute the MOS inverse Widlar current
mirror circuit. As described above with reference to the prior art,
a negative feedback current loop is formed, and the circuit is
stable operated at a set operation point. Thus, the MOS inverse
Widlar current mirror circuit is self-biased to realize a CMOS
reference current circuit. In FIG. 9, if the transistor M2 is a
unit transistor, and a ratio (W/L) of a gate width W between a gate
length L of the transistor M1 is K.sub.1 times (K.sub.1 >1) as
large as that of the unit transistor, then drain currents of the
MOS transistors M1 and M2 are respectively represented by the
following equations (37) and (38):
Furthermore, a relation represented by the following equation (39)
is established:
Here, by solving the equations (37) to (39), a relation is
represented by the following equation (40): ##EQU9##
FIG. 10 shows an input/output characteristic of the MOS inverse
Widlar current mirror circuit. In the drawing, an abscissa
indicates an input current I.sub.D1, and an ordinate indicates an
output current I.sub.D2, a characteristic with K.sub.1 =1 and
K.sub.1 =4 set as parameters being shown.
In this case, the transistor M3 drives the transistor M4, and the
transistor M4 constitutes a current mirror circuit with the
transistors M5 and M6. The transistors M1 and M2 are respectively
driven by the transistors M6 and M5. Thus, the MOS self-biased
inverse Widlar reference current circuit is provided, and if a
ratio (W/L) of a ratio (W/L) of a gate width W btween a gate length
L of the transistor M6 and M5 6 (W/L) 5 is 1:K.sub.2, then a
relation is represented by the following equation (41):
Furthermore, a relation represented by the following equation (42)
is established:
By solving the equations (37) to (42), then a relation is
represented by the following equation (43). ##EQU10##
Here, K.sub.1 and K.sub.2 denote constants having no temperature
characteristics. On the other hand, since mobility .mu. has a
temperature characteristic in the MOS transistor, temperature
dependence of a transconductance parameter .beta. is represented
byte the equation (31), and an output current I.sub.REF of the CMOS
reference current circuit is obtained by the following equation
(44): ##EQU11##
Here, K1 and K2 denote constants having no temperature
characteristics and, as described above, a temperature
characteristic of 1/.beta. is substantially proportional to a
temperature, being 5000 ppm/.degree. C. at a normal
temperature.
Accordingly, if a temperature characteristic of the resistor R2 is
equal toor lower than 5000 ppm/.degree. C., being a primary
characteristic with respect to the temperature, an output current
I.sub.0 of the reference current circuit outputted through the
current mirror circuit is proportional to the temperature,
realizing a PTAT current source circuit. Here, by setting K.sub.2
=1, and the transistors M2 to M6 as unit transistors, gate voltages
of the transistors M1 and M3 can be set equal to each other, and
drain voltages of the transistors M5 and M6 are fixed and set equal
to each other. As a result, no effects of the channel length
modulation of the transistors M1 and M2 appear, and no changes
occur in a desired current mirror ratio even if the drain voltages
of the transistors M5 and M6 are changed to cause an appearance of
effects of the channel length modulation, making it possible to
obtain a highly accurate current output having only a small change
with respect to fluctuation in a power supply voltage. Moreover,
even with K.sub.2.noteq.1, the drain voltages of the transistors M1
and M3 are fixed by at least the gate voltages of the transistors
M1 and M2, and a fluctuation extent is limited, and thus almost no
effects of the channel length modulation of the transistors M1 and
M2 appear.
FIG. 11 shows a reference current circuit according to a third
embodiment of the present invention, specifically an embodiment of
a bipolar reference current circuit. In the reference current
circuit of the third embodiment of the present invention,
transistors Q1 and Q2 and a resistor R1 constitute the bipolar
Widlar current mirror circuit and, similarly, transistors Q4, Q5,
(Q6), and a resistor R4 constitute the bipolar Nagata current
mirror circuit. In this case, by the transistors Q5 and Q6
constituting a current source, the transistors Q1 and Q2, and the
resistor R1 constitute the bipolar self-biased Widlar reference
current circuit. In addition, in the bipolar Nagata current mirror
circuit constituted of the transistors Q4, Q5, (Q6) and the
resistor R4, a circuit constant is set such that when a current of
the transistor Q3 to be driven is increased, currents flowing to
the transistors Q5 and Q6 can be reduced. Thus, in the bipolar
self-biased Nagata reference current circuit, a negative feedback
current loop is formed, enabling the circuit to be stably operated.
In the case of the bipolar self-biased Widlar reference current
circuit described in Japanese Patent Application Laid-Open No.
200086/1995, a positive feedback current loop is formed in the
circuit, and thus the circuit is not operated.
Assuming that a DC current amplification factor of the transistor
is sufficiently near 1, by ignoring a base current, in the bipolar
Widlar current mirror circuit, from the equation (1), relations are
represented by the following equations (45) to (47):
Here, by solving the equations (45) to (47), a relation between
input and output currents in the bipolar Widlar current mirror
circuit is represented by the following equation (48):
I.sub.C1 =(I.sub.C2 /K.sub.1)exp(R.sub.1 I.sub.C2 /V.sub.T)
(48)
A relation between input and output currents of the bipolar Widlar
current mirror is just a inverse of input and output currents of
the bipolar inverse Widlar current mirror circuit. FIG. 12 shows an
input/output characteristic of the bipolar Widlar current mirror
circuit constituted of the transistors Q1 and Q2 and the resistor
R1.
In this case, the transistor Q3 drives the transistor Q4. The
transistor Q4 constitutes the bipolar Nagata current mirror circuit
with the transistor Q5 and Q6 and the resistor R4, which is
operated in a region where the output current (mirror current) is
monotonously reduced with respect to the input current (reference
current). The transistors Q1 and Q2 are respectively driven by the
transistors Q6 and Q5. Thus, the bipolar self-biased Widlar
reference current circuit is provided, and if an emitter area ratio
of the transistors Q5 and Q6 is 1:K.sub.2, then a relation is
represented by the following equation (49):
However, if the transistor Q4 is a unit transistor, an emitter area
ratio of the transistor Q5 is K.sub.3 times as large as that of the
unit transistor; and an emitter area ratio of the transistor Q6 is
K.sub.2 K.sub.3 times as large as that of the unit transistor. In
addition, to keep the bipolar Nagata current mirror circuit
operable in the region of a monotonous reduction, K.sub.3 >e
(=2.7183) must be set.
In addition, since the following equation (50) is established,
##EQU12##
the equation (51) is obtained:
Here, K.sub.1 and K.sub.2 denote the constants having no
temperature characteristics and, as described above, the thermal
voltage V.sub.T is represented by V.sub.T =kT/q, exhibiting a
temperature characteristic of 3333 ppm/.degree. C. Accordingly, if
a temperature characteristic of the resistor R1 is smaller than the
temperature characteristic of the thermal voltage V.sub.T, being a
primary characteristic with respect to a temperature, an output
current I.sub.0 (=I.sub.C1) of the reference current circuit
outputted through the current mirror circuit is proportional to the
temperature, realizing a PTAT current source circuit.
To make currents flowing to the transistors Q1 and Q3 equal to each
other, the emitter area ratios K1, K2 and K3, and values of the
resistors R1 and R4 are set. Thus, base bias voltages of the
transistors Q1 and Q3 are substantially equal to each other, fixing
and setting collector voltages of the transistors Q1 and Q3 to be
equal to each other. As a result, no effects of Early voltages of
the transistors Q1 and Q2 appear, and no changes occur in a desired
current mirror ratio even if the collector voltages of the
transistors Q5 and Q6 are changed to cause an appearance of effects
of Early voltages, making it possible to obtain a highly accurate
current output having only a small change with respect to
fluctuation in a power supply voltage. Moreover, even when the
currents flowing to the transistors Q1 and Q3 are not equal to each
other, the collector voltages of the transistors Q1 and Q2 are
fixed by at least the base bias voltages of the transistors Q1 and
Q3, and a fluctuation extent is limited, and thus almost no effects
of Early voltages of the transistors Q1 and Q2 appear.
FIG. 13 shows the reference current circuit of the third embodiment
of the present invention, specifically a CMOS reference current
circuit of another embodiment. In the reference current circuit of
the third embodiment of the present invention, transistors M1 and
M2 and a resistor R1 constitute the MOS Widlar current mirror
circuit and, similarly, transistors M4, and MS (M6), and a resistor
R4 constitute the MOS Nagata current mirror circuit. In this case,
by the transistors MS and M6 constituting a current source, the
transistors M1 and M2 and the resistor R1 constitute the CMOS
self-biased Widlar reference current circuit. In addition, the MOS
Nagata reference current circuit constituted of the transistors M4
and M5 (M6), and the resistor R4 has a circuit constant set such
that when a current of a transistor M3 to be driven is increased,
currents flowing to the transistors MS and M6 can be reduced. Thus,
in the CMOS self-biased Widlar reference current circuit, a
negative feedback current loop is formed, and the circuit is stably
operated. In the case of the CMOS self-biased Widlar reference
current circuit described in Japanese Patent Application Laid-Open
No. 200086/1995, a positive feedback current loop is formed in the
circuit, and thus the circuit is not operated. FIG. 14 shows an
input/output characteristic of the MOS Widlar current mirror
circuit constituted of the transistors M1 and M2 and the resistor
R1.
In FIG. 13, the transistor M1 is a unit transistor, and a ratio
(W/L) of a gate width W between a gate length L of the transistor
M2 is K.sub.1 times (K.sub.1 >1) as large as that of the unit
transistor. In the MOS Widlar current mirror circuit shown in FIG.
13, if the consistency of the circuit element is high, the channel
length modulation and a body effect are ignored, and a relation
between a drain current and a voltage between the gate and the
source of the MOS transistor is set according to a square law, then
the drain currents of the MOS transistors M1 and M2 are represented
by the following equations (52) and (53):
Furthermore, a relation represented by the following equation (54)
is established:
Here, by solving the equations (52) to (54), a relation between
input and output currents of the MOS Widlar current mirror circuit
is represented by the following equation (55): ##EQU13##
This relation between the input and output currents of the MOS
Widlar current mirror circuit is a inverse of a relation between
input and output currents of the MOS inverse Widlar current mirror
circuit. FIG. 14 shows an input/output characteristic of the MOS
Widlar current mirror circuit constituted of the transistors M1 and
M2 and the resistor R1.
In this case, the transistor M3 drives the transistor M4. The
transistor M4 constitutes the MOS Nagata current mirror circuit
with the transistors M5 and M6 and the resistor R4, which is
operated in a region where the output current (mirror current) is
monotonously reduced with respect to the input current (reference
current). The transistors M1 and M2 are respectively driven by the
transistors M6 and M5. Thus, the MOS self-biased Widlar current
circuit is provided.
If a ratio (W/L) of a gate width W between a gate length L of the
transistor M5 and a ratio (W/L) of a gate width W between a gate
length L of the transistor M6 is 1:K.sub.2, then a relation is
represented by the following equation (56):
Furthermore, a relation is represented by the following equation
(57):
By solving the equations (52) to (57), then a relation represented
by the following equation (58) is obtained: ##EQU14##
Here, K.sub.1 and K.sub.2 denote constants having no temperature
characteristics. On the other hand, since the mobility .mu. has a
temperature characteristic in the MOS transistor, the temperature
dependence of the transconductance parameter .beta. is represented
by the equation (31), and an output current I.sub.REF of the CMOS
reference current circuit is represented by the following equation
(59): ##EQU15##
Here, K.sub.1 and K.sub.2 denote constants having no temperature
characteristics. As described above, the temperature characteristic
of 1/.beta. is substantially proportional to a temperature, being
5000 ppm/.degree. C. at the normal temperature. If a temperature
characteristic of the resistor R2 is equal to or lower than 5000
ppm/.degree. C., being a primary characteristic with respect to the
temperature, a drain current I.sub.D1 has a positive temperature
characteristic, and an output current I.sub.0 of the reference
current circuit outputted through the current mirror circuit is
proportional to the temperature, realizing a PTAT current source
circuit. To make currents flowing to the transistors M1 and M3
equal to each other, transistor size ratios (ratio (W/L) of gate
width W between gate length L) K.sub.1, K.sub.2 and K.sub.3 are
set, and values of the resistors R1 and R4 are set. Thus, gate
voltages of the transistors M1 and M3 can be set substantially
equal to each other, fixing and setting drain voltages of the
transistors M1 and M2 to be equal to each other.
As a result, no effects of the channel length modulation of the
transistors M1 and M2 appear, and no changes occur in a desired
current mirror ratio even if the drain voltages of the transistors
M5 and M6 are changed to cause an appearance of effects of the
channel length modulation, making it possible to obtain a highly
accurate current output having only a small change with respect to
fluctuation in a power supply voltage. Moreover, even when the
currents flowing to the transistors M1 and M3 are not equal to each
other, the drain voltages of the transistors M1 and M2 are fixed by
at least the gate voltages of the transistors M1 and M3, and a
fluctuation extent is limited, and thus almost no effects of the
channel length modulation of the transistors M1 and M2 appear.
The reference current circuits (PTGAT current sources) for
outputting currents having positive temperature characteristics
have been described. Each of the foregoing circuits is constructed
such that the collector (drain) voltages of the two output
transistors constituting the current mirror circuit can be equal,
or substantially equal to each other. The temperature
characteristics of the collector (or drain) voltages of at least
the two output transistors constituting the current mirror circuit
are negative. By using such a temperature characteristic of the
drain voltage, a current I.sub.IPTAT having a negative temperature
characteristic is obtained, and this current I.sub.IPTAT and a
current I.sub.PTAT having a positive temperature characteristic
obtained from the PTAT current mirror source are weighted and
added. Thus, it is possible to realize a reference current circuit
for outputting a current having an optional temperature
characteristic.
FIG. 15 shows a reference current circuit according to a fourth
embodiment of the present invention, specifically an embodiment of
a bipolar reference current circuit, which outputs a current having
an optional temperature characteristic. Referring to FIG. 15, the
reference current circuit of the fourth embodiment of the present
invention is shown to be constructed in a manner that transistors
Q1 and Q2, and a resistor R1 constitute the bipolar inverse Widlar
current mirror circuit, and transistors Q4, Q5, (Q6), and a
resistor R4 constitute the bipolar inverse Widlar current mirror
circuit. In this case, if a ratio of currents flowing to the
resistors R2 and R3 is equal to that of currents of the current
mirror circuit constituted of the transistors Q5 and Q6, the
transistors Q1, Q2 (Q3), Q5 and Q6, and the resistor R1 constitute
the bipolar self-biased inverse Widlar reference current circuit.
Accordingly, a terminal voltage V.sub.1 (=V.sub.BE2) of the
resistor R2 and a terminal voltage V.sub.2 (=V.sub.BE3) of the
resistor R3 may be set equal to each other, and a ratio of
resistance values of the resistors R2 and R3 may be set inverse to
a current ratio of the current mirror circuit.
Assuming that a DC current amplification factor of the transistor
is sufficiently near 1, by ignoring a base current, from the
equation (1), relations are represented by the following equations
(60) to (62):
Then, if the transistor Q1 and the resistor R2, and the transistor
Q2 and the resistor R3 are driven by a current mirror circuit
having a mirror ratio of 1:1, a relation represented by the
following equation (63) is established:
Here, the transistors Q4, Q5, (Q6) and the resistor R4 constitute
the bipolar inverse Widlar current mirror circuit, and the
transistors Q5 and Q6 are unit transistors. An emitter area ratio
of the transistor Q4 is K.sub.3 times as large as that of the unit
transistor. By setting a resistor R4 to establish I.sub.C3
=I.sub.C4 =I.sub.C2, V.sub.1 =V.sub.2 (.thrfore.V.sub.BE2
=V.sub.BE3) is set, and with R.sub.3 =R.sub.2, the following
equation (64) is established:
Thus, the following equation (65) is obtained: ##EQU16##
Here, K.sub.1 and K.sub.2 denote constants having no temperature
characteristics and, as described above, the thermal voltage
V.sub.T is represented by V.sub.T =kT/q, exhibiting a temperature
characteristic of 3333 ppm/.degree. C. Thus, .DELTA.V.sub.BE is
proportional to a temperature.
An output current I.sub.REF of the bipolar reference current
circuit is obtained by the following equation (66): ##EQU17##
That is, the output current I.sub.REF of the bipolar reference
current circuit is represented by an equation of weighting and
adding a base-emitter bias voltage V.sub.BE having a negative
temperature characteristic and .DELTA.V.sub.BE having a positive
temperature characteristic. Accordingly, by changing weight
factors, temperature characteristics of two reference voltages can
be optionally set as described above. Specifically, an emitter area
ratio or a current mirror ratio and each resistance ratio may be
set. For example, by converting the output current I.sub.REF of the
bipolar reference current circuit into a voltage by the resistor
R5, an output voltage V.sub.REF obtained is represented by the
following equation (67): ##EQU18##
In this case, the thermal voltage V.sub.T has a positive
temperature characteristic of 3333 ppm/.degree. C., and the
base-emitter bias voltages V.sub.BE2 and V.sub.BE3 of the
transistors Q2 and Q3 have negative temperature characteristics of
about -1.9 mV/.degree. C. The resistance ratios (R.sub.5 /R.sub.1)
and (R.sub.5 /R.sub.3) are zero because of cancellation of
temperature characteristics, and ln(K.sub.1 K.sub.2) has no
temperature characteristics. Thus, the output voltage V.sub.REF
obtained by converting the output current of the bipolar reference
current circuit into a voltage through the resistor is decided by
the positive temperature characteristic, 3333 ppm/.degree. C., of
the thermal voltage V.sub.T, and the negative temperature
characteristic, about -1.9 mV/.degree. C., of the base-emitter bias
voltage V.sub.BE2 of the transistor Q2. For example, in order to
set zero a temperature characteristic of V.sub.REF obtained by
voltage conversion of the output current of the bipolar reference
current circuit through the resistor, if a base-emitter bias
voltage V.sub.B output voltage E.sub.2 (=V.sub.BE3) of the
transistor Q2 is 630 mV at a normal temperature, since the thermal
voltage V.sub.T is 25.6 mV at the normal temperature, (R.sub.3
/R.sub.1)ln(K.sub.1 K.sub.2)=22.3 is obtained. Accordingly,
{V.sub.BE (R.sub.3 /R.sub.1)V.sub.T ln(K.sub.1 K.sub.2)}=1.2 V is
obtained. The output voltage V.sub.REF having the temperature
characteristic of zero thus obtained can be set to an optional
voltage value by optionally setting a ratio (R.sub.5 /R.sub.3) of
the resistors R.sub.5 and R.sub.3.
In the setting of (R.sub.5 /R.sub.3)<1, for example a case of
setting 0.7 V is considered, an operation is possible from about
0.9 V. Alternatively, if a power supply voltage has an allowance to
increase a voltage, by setting (R.sub.5 /R.sub.3)>1, a reference
voltage having a temperature characteristic of zero at V.sub.REF
>1.2 V is obtained. Specifically, V.sub.REF =1.5 V is obtained
by setting (R.sub.5 /R.sub.3)=1.25; and V.sub.REF =2.0 V by setting
(R.sub.5 /R.sub.3)=5/3. As apparent from the foregoing, by setting
the resistor R.sub.5 to be R.sub.5 >R.sub.3, and optionally
providing the number (n-1) of taps in the resistor R.sub.5 to set
it as an output terminal, it is possible to obtain n reference
voltages of optional different voltage values having no temperature
characteristics.
FIG. 16 shows the reference current circuit of the fourth
embodiment of the present invention, specifically a CMOS reference
current circuit of another embodiment, which outputs a current
having an optional temperature characteristic. Referring to FIG.
16, the reference current circuit of the fourth embodiment of the
present invention is shown to be constructed in a manner that
transistors M1 and M2 and a resistor R1 constitute the MOS inverse
Widlar current mirror circuit, and transistors M4, and M5 (M6), and
a resistor R4 constitute the MOS inverse Widlar current mirror
circuit. In this case, if a ratio of currents flowing to the
resistors R2 and R3 is equal to that of currents flowing to the
current mirror circuit constituted of the transistors M5 and M6,
the transistors M1, and M2 (M3), M5 and M6, and the resistor R1
constitute the MOS self-biased inverse Widlar reference current
circuit. Accordingly, a terminal voltage V.sub.2 (=V.sub.GS2) of
the resistor R2, and a terminal voltage V.sub.2 (=V.sub.GS3) of the
resistor R3 may be set equal to each other, and a ratio of
resistance values of the resistors R2 and R3 may be set inverse to
a current ratio of the current mirror circuit. In FIG. 16, the
transistor M2 is a unit transistor, and a ratio (W/L) of a gate
width W/a gate length L of the transistor M1 is K.sub.1 times
(K.sub.1 >1) as large as that of the unit transistor.
If the consistency of the circuit element is high, drain currents
of the MOS transistors M1 and M2 are represented by the following
equations (68) and (69):
Furthermore, a relation is represented by the following equation
(70):
Then, if the transistor M1 and the resistor R2, and the transistor
M2 and the transistor R3 are driven by a current mirror having a
mirror ratio of 1:1, the following equation (71) is obtained:
In this case, the transistors M4 and M5 (M6), and the resistor R4
constitute the MOS inverse Widlar current mirror circuit, the
transistors M5 and M6 are unit transistors, and a ratio (W/L) of a
gate width W between a gate length L of the transistor M4 is
K.sub.3 times as large as that of the unit transistor. By setting
the R4, I.sub.D3 =I.sub.D4 =I.sub.D2 is established, realizing
V.sub.1 =V.sub.2 (.thrfore.V.sub.GS2 =V.sub.GS3). With R3=R2, a
relation represented by the following equation (72) is
established:
Thus, by solving the equations (68) to (72), a relation represented
by the following equation (73) is obtained: ##EQU19##
Here, K.sub.1 denotes a constant having no temperature
characteristics. On the other hand, since mobility .mu. has a
temperature characteristic in the MOS transistor, temperature
dependence of the transconductance parameter .beta. is represented
by the equation (21) and, as shown in FIG. 5, a temperature
characteristic of 1/.beta. is substantially proportional to a
temperature. The temperature characteristic of 1/.beta. is 5000
ppm/.degree. C. at a normal temperature. Therefore, it can be
understood that if a temperature characteristic of the resistor R1
is equal to or lower than 5000 ppm/.degree. C., a drain current
I.sub.D1 has a positive temperature characteristic.
That is, an output current I.sub.REF of the MOS reference voltage
current is obtained by the following equation (74):
On the other hand, from the equation (69), the following
represented by an equation (75) is established: ##EQU20##
Then, the equation (74) is rewritten into the following equation
(76): ##EQU21##
In this case, a temperature characteristic of a threshold voltage
V.sub.TH is represented by the following equation (77):
Here, .alpha. is about 2.3 mV/.degree. C. in a CMOS fabrication
process of the MOS transistor having a low threshold voltage.
Accordingly, the output current I.sub.REF of the MOS reference
voltage circuit is represented by weighting and adding a term of
the threshold voltage V.sub.TH having a negative temperature
characteristic and a term of 1/.beta. having a positive temperature
characteristic. As a result, by changing weight factors, it is
possible to optionally set a temperature characteristic of the
reference current. For example, by converting the output current
I.sub.REF of the MOS reference current circuit into a voltage
through the resistor R5, an output voltage V.sub.REF is represented
by the following equation (78): ##EQU22##
A right side of the equation (78) is represented by weighting and
adding of voltage values caused by inverse numbers of the threshold
voltage V.sub.TH having the negative temperature characteristic and
the transconductance parameter (mobility) having the positive
temperature characteristic. Accordingly, by changing weight
factors, it is possible to optionally set a temperature
characteristic of the output voltage V.sub.REF of the MOS reference
voltage circuit as described above. Specifically, (W/L)/(W/L)
ratio, or a current mirror ratio and resistance values, and each
resistance ratio may be set. In this case, a temperature
characteristic of 1/.beta. as an inverse number of the
transconductance parameter .beta. is substantially proportional to
a temperature, which is 5000 ppm/.degree. C. at a normal
temperature. A threshold voltage V.sub.TH of the transistor M2 has
a negative temperature characteristic of about -2.3 mV/.degree. C.
The temperature characteristics of the resistance ratios (R.sub.5
/R.sub.1) and (R.sub.5 /R.sub.3) are zero because of cancellation,
and K.sub.1 has no temperature characteristics. Thus, the output
voltage V.sub.REF of the MOS reference voltage circuit is decided
by the positive temperature characteristic of 5000 ppm/.degree. C.,
the negative temperature characteristic of the threshold voltage
V.sub.TH of the transistor M2, and about -2.3 mV/.degree. C. For
example, if V.sub.TH0 =0.7 V is set, the following represented by
an equation (79) is obtained: ##EQU23##
Then, the output value is represented by the following equation
(80)
V.sub.REF =(R.sub.5 /R.sub.3) (0.46+0.7)=1.16(R.sub.5 /R.sub.3)V
(80)
Here, the voltage 1.16 V has no temperature characteristics. Thus,
since the temperature characteristic of the (R.sub.5 /R.sub.3) is
zero because of cancellation, a reference voltage V.sub.REF to be
outputted has no temperature characteristics.
In this case, a ratio (R.sub.5 /R.sub.3) of the resistors R5 and R3
can be optionally set. For example, if (R.sub.5 /R.sub.3)<1 is
set, an operation is possible by a low voltage. Specifically, with
R.sub.5 /R.sub.3 =0.69, V.sub.REF =0.8 V is set, and an operation
is possible from a power supply voltage of about 1.0 V.
Furthermore, (R.sub.5 /R.sub.3)>1 can be set. For example, with
R.sub.5 /R.sub.3 =1.72, V.sub.REF =2.0 V is set, and an operation
is possible from a power supply voltage of about 2.2 V. Moreover,
by providing three taps in the resistor R5, and dividing a
resistance value into four parts, four reference voltages all
having no temperature characteristics, i.e., V.sub.REF1 =0.5V,
V.sub.REF2 =1.0V, V.sub.REF3 =1.5 V, and V.sub.REF4 =2.0 V, are
obtained.
FIG. 17 shows a reference current circuit according to a fifth
embodiment of the present invention, specifically an embodiment of
a bipolar reference current circuit, which outputs a current having
an optional temperature characteristic. Referring to FIG. 17, the
reference current circuit of the fifth embodiment of the present
invention is shown to be constructed in a manner that transistors
Q1 and Q2, and a resistor R1 constitute the bipolar Nagata Widlar
current mirror circuit, and the bipolar Nagata current mirror
circuit constituted of transistors Q4, Q5, (Q6), and a resistor R4
has a circuit constant such that when a current of a transistor Q3
to be driven is increased, currents flowing to the transistors Q5
and Q6 can be reduced. Thus, a negative feedback current loop is
provided in the circuit, enabling the circuit to be stably
operated. In this case, if a ratio of currents flowing to the
resistors R2 and R3 is equal to that of currents of the current
mirror circuit constituted of the transistors Q5 and Q6, the
transistors Q1, Q2 (Q3), Q5 and Q6, and the resistor R1 constitute
the bipolar self-biased Nagata reference current circuit.
Accordingly, K.sub.1, K.sub.2 and K.sub.3, and the resistors R1 and
R4 are set such that the terminal voltage V.sub.1 (=V.sub.BE2) of
the resistor R2 and the terminal voltage V.sub.2 (=V.sub.BE3) of
the resistor R3 can be set equal to each other, and a ratio of
resistance values of the resistors R2 and R3 may be set inverse to
a current ratio of the current mirror circuit.
Assuming that a DC current amplification factor of the transistor
is sufficiently near 1, by ignoring a base current, from the
equation (1), relations are represented by the following equations
(81) to (83):
Then, if the transistor Q1 and the resistor R2, and the transistor
Q2 and the resistor R3 are driven by a current mirror having a
mirror ratio of K.sub.2 :1, a relation represented by the following
equation (84) is established:
Here, the transistors Q4, Q5, (Q6) and the resistor R4 constitute
the bipolar Nagata current mirror circuit, and the transistors Q5
and Q6 are unit transistors. An emitter area ratio of the
transistor Q4 is K.sub.3 times as large as that of the unit
transistor. By setting a resistor R4 to establish I.sub.C1
=I.sub.C3, V.sub.1 =V.sub.2 (.thrfore.V.sub.BE2 =V.sub.BE3) is set,
and with R.sub.3 /R.sub.2 =K.sub.2, the following equation (85) is
established:
Thus, the following equation (86) is obtained: ##EQU24##
Here, K.sub.1 and K.sub.2 denote constants having no temperature
characteristics and, as described above, a thermal voltage V.sub.T
is represented by V.sub.T =kT/q, exhibiting a temperature
characteristic of 3333 ppm/.degree. C. Thus, .DELTA.V.sub.BE is
proportional to a temperature.
An output current I.sub.REF of the bipolar reference voltage
circuit is obtained by the following equation (87): ##EQU25##
That is, the output current I.sub.REF of the bipolar reference
current circuit is represented by an equation of weighting and
adding a base-emitter bias voltage V.sub.BE having a negative
temperature characteristic and .DELTA.V.sub.BE having a positive
temperature characteristic. Accordingly, by changing weight
factors, temperature characteristics of two reference voltages can
be optionally set as described above. Specifically, an emitter area
ratio or a current mirror ratio and each resistance ratio may be
set. For example, by converting the output current I.sub.REF of the
bipolar reference current circuit into a voltage by the resistor
R5, an output voltage V.sub.REF obtained is represented by the
following equation (88): ##EQU26##
In this case, the thermal voltage V.sub.T has a positive
temperature characteristic of 3333 ppm/.degree. C., and the
base-emitter bias voltages V.sub.BE2 and V.sub.BE3 of the
transistors Q2 and Q3 have negative temperature characteristics of
about -1.9 mV/.degree. C. The resistance ratios (R.sub.5 /R.sub.1)
and (R.sub.5 /R.sub.3) are zero because of cancellation of the
temperature characteristics, and K.sub.2 and ln(K.sub.1 K.sub.2)
have no temperature characteristics. Thus, the output voltage
V.sub.REF obtained by converting the output current of the bipolar
reference current circuit into a voltage through the resistor is
decided by the positive temperature characteristic, 3333
ppm/.degree. C., of the thermal voltage V.sub.T, and the negative
temperature characteristic, about -1.9 mV/.degree. C., of the
base-emitter bias voltage V.sub.BE2 of the transistor Q1. For
example, in order to set zero a temperature characteristic of the
output voltage V.sub.REF obtained by voltage conversion of the
output current of the bipolar reference current circuit through the
resistor, if a base-emitter bias voltage V.sub.BE1 (=V.sub.BE3) of
the transistor Q1 is 630 mV at a normal temperature, since the
thermal voltage V.sub.T is 25.6 mV at the normal temperature,
(R.sub.3 /K.sub.2 R.sub.1)ln(K.sub.1 K.sub.2)=22.3 is obtained.
Accordingly, {R.sub.3 /(K.sub.2 R.sub.1)}V.sub.T ln(K.sub.1
K.sub.2)+V.sub.BE1 }=1.2 V is obtained.
The output voltage V.sub.REF having the temperature characteristic
of zero thus obtained can be set to an optional voltage value by
optionally setting a ratio (R.sub.5 /R.sub.3) of the resistors
R.sub.5 and R.sub.3. In the setting of (R.sub.5 /R.sub.3)<1, for
example a case of setting 0.7 V is considered, an operation is
possible from about 0.9 V. Alternatively, if a power supply voltage
has an allowance to increase a voltage, by setting (R.sub.5
/R.sub.3)>1, a reference voltage having a temperature
characteristic of zero at V.sub.REF >1.2 V is obtained.
Specifically, V.sub.REF =1.5 V is obtained by setting (R.sub.5
/R.sub.3)=1.25; and V.sub.REF =2.0 V by setting (R.sub.5
/R.sub.3)=5/3. As apparent from the foregoing, by setting the
resistor R.sub.5 to be R.sub.5 >R.sub.3, and optionally
providing the number (n-1) of taps in the resistor R.sub.5 to set
it as an output terminal, it is possible to obtain n reference
voltages of optional different voltage values having no temperature
characteristics.
FIG. 18 shows the reference current circuit of the fifth embodiment
of the present invention, specifically a CMOS reference current
circuit of another embodiment, which outputs a current having an
optional temperature characteristic. Referring to FIG. 18, the
reference current circuit of the fifth embodiment of the present
invention is shown to be constructed in a manner that transistors
M1 and M2 and a resistor R1 constitute the MOS Nagata current
mirror circuit, and the MOS Nagata current mirror circuit
constituted of transistors M4, and M5 (M6), and a resistor R4 has a
circuit constant set such that when a current of a transistor M3 to
be driven is increased, currents flowing to the transistors M5 and
M6 can be reduced. In this case, if a ratio of currents flowing to
the resistors R2 and R3 is equal to that of currents flowing to the
current mirror circuit constituted of the transistors M5 and M6,
the transistors M1, and M2 (M3), M5 and M6, and the resistor R1
constitute the MOS self-biased Nagata reference current circuit.
Accordingly, K.sub.1, K.sub.2 and K.sub.3, and the resistors R1 and
R2 are set such that the terminal voltage V.sub.1 (=V.sub.GS2) of
the resistor R2, and the terminal voltage V.sub.2 (=V.sub.GS3) of
the resistor R3 may be set equal to each other, and a ratio of
resistance values of the resistors R2 and R3 may be set inverse to
a current ratio of the current mirror circuit. In FIG. 18, the
transistor M2 is a unit transistor, and a ratio of a gate width W
between a gate length L (W/L) of the transistor M1 is K.sub.1 times
(K.sub.1 >1) as large as that of the unit transistor.
If the consistency of the circuit element is high, drain currents
of the MOS transistors M1 and M2 are represented by the following
equations (89) and (90):
Furthermore, a relation is represented by the following equation
(91):
Then, if the transistor M1 and the resistor R2, and the transistor
M2 and the transistor R3 are driven by a current mirror having a
mirror ratio of K.sub.2 :1, the following equation (92) is
obtained:
In this case, the transistors M4 and M5 (M6), and the resistor R4
constitute the MOS Nagata current mirror circuit, the transistors
M5 and M6 are unit transistors, and a ratio (W/L) of a gate width W
between a gate length L of the transistor M4 is K.sub.3 times as
large as that of the unit transistor. By setting the R4, I.sub.D1
=I.sub.D3 is established, realizing V.sub.1 =V.sub.2
(.thrfore.V.sub.GS2 =V.sub.GS3). With R.sub.3 /R.sub.2 =K.sub.2, a
relation represented by the following equation (93) is
established:
Thus, by solving the equations (89) to (92), a relation represented
by the following equation (94) is obtained: ##EQU27##
Here, K.sub.1 and K.sub.2 denote the constants having no
temperature characteristics. On the other hand, since the mobility
.mu. has a temperature characteristic in the MOS transistor, the
temperature dependence of the transconductance parameter .beta. is
represented by the equation (34) and, as shown in FIG. 5, the
temperature characteristic of 1/.beta. is substantially
proportional to the temperature. The temperature characteristic of
1/.beta. is 5000 pm/.degree. C. at the normal temperature.
Therefore, it can be understood that if the temperature
characteristic of the resistor R1 is equal to or lower than 5000
ppm/.degree. C., a drain current I.sub.D1 has a positive
temperature characteristic. That is, an output current I.sub.REF of
the MOS reference voltage current is obtained by the following
equation (95):
On the other hand, from the equation (89), the following
represented by an equation (96) is established: ##EQU28##
Then, the equation (95) is rewritten into the following equation
(97): ##EQU29##
In this case, the temperature characteristic of the threshold
voltage V.sub.TH is represented by the equation (77), where a is
about 2.3 mV/.degree. C. in a CMOS fabrication process of the MOS
transistor having a low threshold voltage.
Accordingly, the output current I.sub.REF of the MOS reference
voltage circuit is represented by weighting and adding a term of
the threshold voltage V.sub.TH having a negative temperature
characteristic and a term of 1/.beta. having a positive temperature
characteristic. As a result, by changing weight factors, it is
possible to optionally set the temperature characteristic of the
reference current. For example, by converting the output current
I.sub.REF of the MOS reference current circuit into a voltage
through the resistor R5, an output voltage V.sub.REF is represented
by the following equation (98): ##EQU30##
A right side of the equation (98) is represented by weighting and
adding of the voltage values caused by inverse numbers of the
threshold voltage V.sub.TH having the negative temperature
characteristic and the transconductance parameter (mobility) having
the positive temperature characteristic. Accordingly, by changing
weight factors, it is possible to optionally set a temperature
characteristic of the output voltage V.sub.REF of the MOS reference
voltage circuit. Specifically, a (W/L)/(W/L) ratio, or a current
mirror ratio and resistance values, and each resistance ratio may
be set. In this case, a temperature characteristic of 1/.beta. as
an inverse number of the transconductance parameter .beta. is
substantially proportional to the temperature, which is 5000
ppm/.degree. C. at a normal temperature. The threshold voltage
V.sub.TH of the transistor M2 has a negative temperature
characteristic of about -2.3 mV/.degree. C. The temperature
characteristics of the resistance ratios (R.sub.5 /R.sub.1) and
(R.sub.5 /R.sub.3) are zero because of cancellation, and K.sub.1
has no temperature characteristics. Thus, the output voltage
V.sub.REF of the MOS reference voltage circuit is decided by the
positive temperature characteristic of 5000 ppm/.degree. C., the
negative temperature characteristic of the threshold voltage
V.sub.TH of the transistor M2, and about -2.3 mV/.degree. C. For
example, if V.sub.TH0 =0.7 V is set, the following represented by
an equation (99) is obtained: ##EQU31##
Then, the output value is represented by the following equation
(100):
Here, the voltage 1.16 V has no temperature characteristics.
Thus, since the temperature characteristic of the (R.sub.5
/R.sub.3) is zero because of cancellation, a reference voltage
V.sub.REF to be outputted has no temperature characteristics. In
this case, a ratio (R.sub.5 /R.sub.3) of the resistors R5 and R3
can be optionally set. For example, if (R.sub.5 /R.sub.3)<1 is
set, an operation is possible by a low voltage. Specifically, with
R.sub.5 /R.sub.3 =0.69, V.sub.REF =0.8 V is set, and an operation
is possible from a power supply voltage of about 1.0 V.
Furthermore, (R.sub.5 /R.sub.3)>1 can be set. For example, with
R.sub.5 /R.sub.3 =1.72, V.sub.REF =2.0 V is set, and an operation
is possible from a power supply voltage of about 2.2 V. Moreover,
by providing three taps in the resistor R5, and dividing a
resistance value into four parts, four reference voltages all
having no temperature characteristics, i.e., V.sub.REF1 =0.5 V,
V.sub.REF2 =1.0 V, V.sub.REF3 =1.5 V, and V.sub.REF4 =2.0 V, are
obtained.
FIG. 19 shows a reference current circuit according to a sixth
embodiment of the present invention, specifically an embodiment of
a bipolar reference current circuit, which outputs a current having
an optional temperature characteristic. Referring to FIG. 19, the
reference current circuit of the sixth embodiment of the present
invention is shown to be constructed in a manner that transistors
Q1 and Q2, and a resistor R1 constitute the bipolar Widlar current
mirror circuit, and the bipolar Nagata current mirror circuit
constituted of transistors Q4, Q5, (Q6), and a resistor R4 has a
circuit constant set such that when a current of a transistor Q3 to
be driven is increased, currents flowing to the transistors Q5 and
Q6 can be reduced. Thus, a negative feedback current loop is
provided in the circuit, and the circuit is stably operated. In
this case, if a ratio of currents flowing to the resistors R2 and
R3 is equal to that of currents of the current mirror circuit
constituted of the transistors Q5 and Q6, the transistors Q1, Q2
(Q3), Q5 and Q6, and the resistor R1 constitute the bipolar
self-biased Nagata reference current circuit. Accordingly, K.sub.1,
K.sub.2 and K.sub.3, and the resistors R1 and R4 are set such that
the terminal voltage V.sub.1 (=V.sub.BE1) of the resistor R2 and
the terminal voltage V.sub.2 (=V.sub.BE3) of the resistor R3 may be
set equal to each other, and a ratio of resistance values of the
resistors R2 and R3 may be set inverse to a current ratio of the
current mirror circuit.
Assuming that a DC current amplification factor of the transistor
is sufficiently near 1, by ignoring a base current, from the
equation (1), relations are represented by the following equations
(101) to (103):
Then, if the transistor Q1 an the resistor R2, and the transistor
Q2 and the resistor R3 are driven by a current mirror having the
mirror ratio of K.sub.2 :1, a relation represented by the following
equation (104) is established:
Here, the transistors Q4, Q5, (Q6) and the resistor R4 constitute
the bipolar Nagata current mirror circuit, and the transistors Q5
and Q6 are unit transistors. An emitter area ratio of the
transistor Q4 is K.sub.3 times as large as that of the unit
transistor. By setting a resistor R4 to establish I.sub.C1
=I.sub.C3, V.sub.1 =V.sub.2 (.thrfore.V.sub.BE2 =V.sub.BE3) is set,
and with R.sub.3 /R.sub.2 =K.sub.2, the following equation (105) is
established:
Thus, the following equation (106) is obtained: ##EQU32##
Here, K.sub.1 and K.sub.2 denote the constants having no
temperature characteristics and, as described above, the thermal
voltage V.sub.T is represented by V.sub.T =kT/q, exhibiting a
temperature characteristic of 3333 ppm/.degree. C. Thus,
.DELTA.V.sub.BE is proportional to a temperature.
An output current I.sub.REF of the bipolar reference voltage
circuit is obtained by the following equation (107):
That is, the output current I.sub.REF of the bipolar reference
current circuit is represented by an equation of weighting and
adding the base-emitter bias voltage V.sub.BE having a negative
temperature characteristic and .DELTA.V.sub.BE having a positive
temperature characteristic. Accordingly, by changing weight
factors, the temperature characteristics of two reference voltages
can be optionally set as described above. Specifically, an emitter
area ratio or a current mirror ratio and each resistance ratio may
be set. For example, by converting the output current I.sub.REF of
the bipolar reference current circuit into a voltage by the
resistor R5, the output voltage V.sub.REF obtained is represented
by the following equation (108): ##EQU33##
In this case, the thermal voltage V.sub.T has a positive
temperature characteristic of 3333 ppm/.degree. C., and the
base-emitter bias voltages V.sub.BE2 and V.sub.BE3 of the
transistors Q2 and Q3 have negative temperature characteristics of
about -1.9 mV/.degree. C. The resistance ratios (R.sub.5 /R.sub.1)
and (R.sub.5 /R.sub.3) are zero because of cancellation of
temperature characteristics, and ln(K.sub.1 K.sub.2) has no
temperature characteristics. Thus, the output voltage V.sub.REF
obtained by converting the output current of the bipolar reference
current circuit into a voltage through the resistor is decided by
the positive temperature characteristic, 3333 ppm/.degree. C., of
the thermal voltage V.sub.T, and the negative temperature
characteristic, about -1.9 mV/.degree. C., of the base-emitter bias
voltage V.sub.BE1 of the transistor Q1. For example, in order to
set zero a temperature characteristic of the output voltage
V.sub.REF obtained by voltage conversion of the output current of
the bipolar reference current circuit through the resistor, if a
base-emitter bias voltage V.sub.BE1 (=V.sub.BE3) of the transistor
Q1 is 630 mV at the normal temperature, since the thermal voltage
V.sub.T is 25.6 mV at the normal temperature, (R.sub.3
/R.sub.1)ln(K.sub.1 K.sub.2)=22.3 is obtained.
Accordingly, {(R.sub.3 R.sub.1)V.sub.T ln(K.sub.1
K.sub.2)+V.sub.BE1 }=1.2 V is obtained. The output voltage
V.sub.REF having the temperature characteristic of zero thus
obtained can be set to an optional voltage value by optionally
setting a ratio (R.sub.5 /R.sub.3) of the resistors R.sub.5 and
R.sub.3. In the setting of (R.sub.5 /R.sub.3)<1, for example a
case of setting 0.7 V is considered, an operation is possible from
about 0.9 V. Alternatively, if a power supply voltage has an
allowance to increase a voltage, by setting (R.sub.5
/R.sub.3)>1, a reference voltage having a temperature
characteristic of zero at V.sub.REF >1.2 V is obtained.
Specifically, V.sub.REF =1.5 V is obtained by setting (R.sub.5
/R.sub.3)=1.25; and V.sub.REF =2.0 V by setting (R.sub.5
/R.sub.3)=5/3. As apparent from the foregoing, by setting the
resistor R.sub.5 to be R.sub.5 >R.sub.3, and optionally
providing the number (n-1) of taps in the resistor R.sub.5 to set
it as an output terminal, it is possible to obtain n reference
voltages of optional different voltage values having no temperature
characteristics.
FIG. 20 shows the reference current circuit of the sixth embodiment
of the present invention, specifically a CMOS reference current
circuit of another embodiment, which outputs a current having an
optional temperature characteristic. Referring to FIG. 20, the
reference current circuit of the sixth embodiment of the present
invention is shown to be constructed in a manner that transistors
M1 and M2 and a resistor R1 constitute the MOS Widlar current
mirror circuit, and the MOS Nagata current mirror circuit
constituted of transistors M4, and M5 (M6), and a resistor R4 has a
circuit constant set such that when a current of a transistor M3 to
be driven is increased, currents flowing to the transistors M5 and
M6 can be reduced. Accordingly, a negative feedback current loop is
provided in the circuit, and the circuit is stably operated. In
this case, if a ratio of currents flowing to the resistors R2 and
R3 is equal to that of currents flowing to the current mirror
circuit constituted of the transistors M5 and M6, the transistors
M1, and M2 (M3), M5 and M6, and the resistor R1 constitute the MOS
self-biased Nagata reference current circuit. Thus, K.sub.1,
K.sub.2 and K.sub.3, and the resistors R1 and R2 are set such that
the terminal voltage V.sub.1 (=V.sub.GS1) of the resistor R2, and
the terminal voltage V.sub.2 (=V.sub.GS3) of the resistor R3 can be
set equal to each other, and a ratio of resistance values of the
resistors R2 and R3 may be set inverse to a current ratio of the
current mirror circuit. In FIG. 20, the transistor M2 is a unit
transistor, and a ratio (W/L) of a gate width W between a gate
length L of the transistor M1 is K.sub.1 times (K.sub.1 >1) as
large as that of the unit transistor.
If the consistency of the circuit element is high, drain currents
of the MOS transistors M1 and M2 are represented by the following
equations (109) and (110):
Furthermore, a relation is represented by the following equation
(111):
Then, if the transistor M1 and the resistor R2, and the transistor
M2 and the transistor R3 are driven by a current mirror having a
mirror ratio of K.sub.2 :1, the following equation (112) is
obtained:
In this case, the transistors M4 and M5 (M6), and the resistor R4
constitute the MOS Nagata current mirror circuit, the transistor M4
is a unit transistor, and a ratio (W/L) of a gate width W between a
gate length L of the transistor M5 is K.sub.3 times as large as
that of the unit transistor. By setting the R4, I.sub.D1 =I.sub.D3
is established, realizing V.sub.1 =V.sub.2 (.thrfore.V.sub.GS1
=V.sub.GS3). With R.sub.3 /R.sub.2 =K.sub.2, a relation represented
by the following equation (113) is established:
Thus, by solving the equations (109) to (112), a relation
represented by the following equation (114) is obtained:
##EQU34##
Here, K.sub.1 and K.sub.2 denote constants having no temperature
characteristics. On the other hand, since mobility .mu. has a
temperature characteristic in the MOS transistor, temperature
dependence of the transconductance parameter .beta. is represented
by the equation (34) and, as shown in FIG. 8, a temperature
characteristic of 1/.beta. is substantially proportional to a
temperature. The temperature characteristic of 1/.beta. is 5000
ppm/.degree. C. at a normal temperature. Therefore, it can be
understood that if a temperature characteristic of the resistor R1
is equal to or lower than 5000 ppm/.degree. C., a drain current ID2
has a positive temperature characteristic.
That is, an output current I.sub.REF of the MOS reference voltage
current is obtained by the following equation (115):
I.sub.REF I.sub.D2 +V.sub.2 /R.sub.3 =I.sub.D2 +V.sub.GS1 /R.sub.3
(115)
On the other hand, from the equation (109), the following
represented by an equation (116) is established: ##EQU35##
Then, the equation (115) is rewritten into the following equation
(117): ##EQU36##
In this case, the temperature characteristic of the threshold
voltage V.sub.TH is represented by the (77), where .alpha. is about
2.3 mV/.degree. C. in a CMOS fabrication process of the MOS
transistor having a low threshold voltage. Accordingly, the output
current I.sub.REF of the MOS reference voltage circuit is
represented by weighting and adding a term of the threshold voltage
V.sub.TH having a negative temperature characteristic and a term of
1/.beta. having a positive temperature characteristic.
As a result, by changing weight factors, it is possible to
optionally set a temperature characteristic of the reference
current. For example, by converting the output current I.sub.REF of
the MOS reference current circuit into a voltage through the
resistor R5, an output voltage V.sub.REF is represented by the
following equation (118): ##EQU37##
A right side of the equation (118) is represented by weighting and
adding of voltage values caused by inverse numbers of the threshold
voltage V.sub.TH having the negative temperature characteristic and
the transconductance parameter (mobility) having the positive
temperature characteristic. Accordingly, by changing weight
factors, it is possible to optionally set a temperature
characteristic of the output voltage V.sub.REF of the MOS reference
voltage circuit as described above. Specifically, a (W/L)/(W/L)
ratio, or a current mirror ratio and resistance values, and each
resistance ratio may be set.
In this case, the temperature characteristic of 1/.beta. as an
inverse number of the transconductance parameter .beta. is
substantially proportional to a temperature, which is 5000
ppm/.degree. C. at the normal temperature. The threshold voltage
V.sub.TH of the transistor M2 has the negative temperature
characteristic of about -2.3 mV/.degree. C. The temperature
characteristics of the resistance ratios (R.sub.5 /R.sub.1) and
(R.sub.5 /R.sub.3) are zero because of cancellation, and K.sub.1
has no temperature characteristics. Thus, the output voltage
V.sub.REF of the MOS reference voltage circuit is decided by the
positive temperature characteristic of 5000 ppm/.degree. C., the
negative temperature characteristic of the threshold voltage
V.sub.TH of the MOS reference voltage circuit, and about -2.3
mV/.degree. C. For example, if V.sub.TH0 =0.7 V is set, the
following represented by an equation (119) is obtained:
##EQU38##
Then, the output value is represented by the following equation
(120):
Here, the voltage 1.16 V has no temperature characteristics. Thus,
since the temperature characteristic of the (R.sub.5 /R.sub.3) is
zero because of cancellation, the reference voltage V.sub.REF to be
outputted has no temperature characteristics.
In this case, a ratio (R.sub.5 /R.sub.3) of the resistors R5 and R3
can be optionally set. For example, if (R.sub.5 /R.sub.3)<1 is
set, an operation is possible by a low supply voltage.
Specifically, with R.sub.5 /R.sub.3 =0.69, V.sub.REF =0.8 V is set,
and an operation is possible from a power supply voltage of about
1.0 V. Furthermore, (R.sub.5 /R.sub.3)>1 can be set. For
example, with R.sub.5 /R.sub.3 =1.72, V.sub.REF =2.0 V is set, and
an operation is possible from a power supply voltage of about 2.2
V. Moreover, by providing three taps in the resistor R5, and
dividing a resistance value into four parts, four reference
voltages all having no temperature characteristics, i.e.,
V.sub.REF1 =0.5 V, V.sub.REF2 =1.0 V, V.sub.REF3 =1.5 V, and
V.sub.REF4 =2.0 V, are obtained.
Next, description will be made of the preferred embodiments of the
present invention, specifically those of reference voltage circuits
with reference to the accompanying drawings. FIG. 21 is a view
showing an example of a reference voltage circuit according to a
seventh embodiment of the present invention, specifically an
embodiment of a bipolar reference voltage circuit. Referring to
FIG. 21, the reference voltage circuit of the seventh embodiment of
the present invention is shown to be constructed in a manner that
transistors Q1 and Q2, and a resistor R1 constitute the bipolar
inverse Widlar current mirror circuit. Assuming that a DC current
amplification factor of the transistor is sufficiently near 1, by
ignoring a base current, in the bipolar inverse Widlar current
mirror circuit, from the equation (9), relations are represented by
the following equations (121) to (123):
Here, by solving the equations (121) to (123), a relation between
input and output currents in the bipolar inverse Widlar current
mirror circuit is represented by the following equation (124):
Thus, in the bipolar inverse Widlar current mirror circuit, a
mirror current I.sub.C2 is exponentially increased with respect to
a reference current I.sub.C2.
In this case, the transistor Q5 constitutes the current mirror
circuit with the transistor Q4 (and Q6), which has a current mirror
ratio of 1:1, and the transistors Q1 and Q2 are respectively driven
by the transistors Q4 and Q5. Thus, the bipolar self-biased inverse
Widlar reference current circuit is provided, and then a relation
is represented by the following equation (125):
Furthermore, since the following equation (126) is established,
##EQU39##
the equation (127) is obtained:
Here, K.sub.1 denotes a constant having no temperature
characteristics and, as described above, the thermal voltage
V.sub.T is represented by V.sub.T =kT/q, exhibiting a temperature
characteristic of 3333 ppm/.degree. C. Accordingly, if a
temperature characteristic of the resistor R1 is smaller than the
temperature characteristic of the thermal voltage V.sub.T, being a
primary characteristic with respect to a temperature, an output
current I.sub.REF (=I.sub.C1) of the reference current circuit
outputted through the current mirror circuit is proportional to the
temperature, realizing a PTAT current source. In addition, since
the transistor Q5 constitutes a current mirror circuit with the
transistors Q4 and Q6, a relation represented by the following
equation (128) is established:
I.sub.C4 =I.sub.C5 =I.sub.C6 =I.sub.C1 =I.sub.C2 =(V.sub.T
/R.sub.1)ln(K.sub.1) (128)
A collector current I.sub.C6 of the transistor Q6 is converted into
a voltage by the output circuit, becoming a reference voltage
V.sub.REF. If a current flowing to the resistor R2 is
.gamma.I.sub.C6 (0<.gamma.<1), then the reference voltage
V.sub.REF is represented by the following equation (129):
By solving the equation (120) for .gamma., .gamma. is represented
by the following equation (130):
Thus, the reference voltage V.sub.REF is obtained by the following
equation (131): ##EQU40##
In the equation (131), a coefficient term R.sub.3 /(R.sub.2
+R.sub.3) is 0<R.sub.3 /(R.sub.2 +R.sub.3)<1. In a second
term {V.sub.BE3 +(R.sub.2 /R.sub.1)V.sub.T ln(K.sub.1)}, V.sub.BE3
has a negative temperature characteristic of about -1.9 mV/.degree.
C., and the thermal voltage V.sub.T has a positive temperature
characteristic of 0.0853 mV/.degree. C. Accordingly, in order to
prevent the reference voltage V.sub.REF to be outputted from having
any temperature characteristics, a temperature characteristic is
canceled by a voltage having a positive temperature characteristic
and a voltage having a negative temperature characteristic. That
is, in this case, a value of (R.sub.2 /R.sub.1)ln(K.sub.1) is 22.3,
and a voltage value of (R.sub.2 /R.sub.1)V.sub.T ln(K.sub.1) is
0.57 V. Now, if V.sub.BE3 is 0.7 V, {V.sub.BE3 +(R.sub.2
/R.sub.1)V.sub.T ln(K.sub.1)}=1.27 V is obtained. Thus, sine
R.sub.3 /(R.sub.2 +R.sub.3)<1 is established, the reference
voltage V.sub.REF can be set equal to or lower than 1.27 V, e.g.,
1.0 V. In addition, as shown in FIG. 33, a current is outputted
through the current mirror circuit, and then the current is
converted into a voltage by an output circuit constituted of a
diode-connected transistor and two resistors, and outputted. Thus,
by series-connecting the current mirror circuit with n output
circuits having different resistance ratios (R.sub.3 /(R.sub.2
+R.sub.3), two resistors at each stage, it is possible to obtain n
reference voltages having no temperature characteristics.
For example, if a power supply voltage has an allowance to increase
a voltage, the output circuits each constituted of the
diode-connected transistor and the two resistors are
series-connected at n stages, a flowing current is shared, and the
two resistance values at each stage are made different from each
other. Accordingly, n different output voltages (V.sub.REF1,
V.sub.REF2, V.sub.REF3, . . . , V.sub.REFn) are obtained. Any of
these output voltages has no temperature characteristics.
Alternatively, as shown in FIG. 34, similar output circuits each
constituted of a diode-connected transistor and two resistors are
series-connected at n stages, and a flowing current is shared,
enabling output voltages to be nV.sub.REF. Needless to say, since a
voltage between stages can be outputted, voltages V.sub.REF,
2V.sub.REF, 3V.sub.REF, . . . nV.sub.REF are also obtained. In this
case, no changes occur in a circuit current.
FIG. 22 shows the reference voltage circuit of the seventh
embodiment of the present invention, specifically a CMOS reference
voltage circuit of another embodiment. Referring to FIG. 22, the
reference voltage circuit of the seventh embodiment of the present
invention is shown to be constructed in a manner that transistors
M1 and M2 and a resistor R1 constitute the MOS inverse Widlar
current mirror circuit, a negative feedback current loop is
provided, and the circuit is stably operated at a set operation
point. Thus, the CMOS reference current circuit is realized by
self-biased the MOS inverse Widlar current mirror circuit. In FIG.
22, the transistor M2 is a unit transistor, and a ratio (W/L) of a
gate width W between a gate length L of the transistor M1 is
K.sub.1 times (K.sub.1 >1) as large as that of the unit
transistor. Then, drain currents of the MOS transistors M1 and M2
are represented by the following equations (132) and (133):
Here, .beta. denotes a transconductance parameter, which is
represented by .beta.=.mu. (C.sub.OX /2) (W/L). In this case, .mu.
denotes effective mobility of a carrier; C.sub.OX a gate oxide film
capacity per unit area; W and L respectively a gate width and a
gate length; and V.sub.TH a threshold voltage.
Furthermore, a relation represented by the following equation (134)
is established:
Here, by solving the equations (132) to (134), a relation is
represented by the following equation (135): ##EQU41##
In this case, the transistor M5 constitutes the current mirror
circuit with the transistors M4 and M6, and the transistors M1 and
M2 are respectively driven by the transistors M4 and M5. Thus, the
MOS self-biased inverse Widlar current circuit is provided. If the
ratios (W/L) of gate widths W between gate lengths L of the
transistors M4, M5 and M6 are all equal, then a relation is
represented by the following equation (136):
Furthermore, a relation represented by the following equation (137)
is established:
By solving the equations (132) to (137), a relation represented by
the following equation (138) is obtained: ##EQU42##
Here, K.sub.1 denotes a constant having no temperature
characteristics.
On the other hand, since the mobility .mu. has a temperature
characteristic in the MOS transistor, the temperature dependence of
the transconductance parameter .beta. is represented by the
following equation (139): ##EQU43##
Here, .beta..sub.0 denotes a value of .beta. at a normal
temperature (300K). Thus, a relation represented by the following
equation (140) is obtained: ##EQU44##
A temperature characteristic of 1/.beta. is 5000 ppm/.degree. C. at
a normal temperature. This is 1.5 times as large as that of a
temperature characteristic 3333 ppm/.degree. C. of the thermal
voltage V.sub.T of the bipolar transistor.
The output current I.sub.REF of the CMOS reference current circuit
is represented by the following equation (141): ##EQU45##
Here, K.sub.1 denotes a constant having no temperature
characteristics. As described above, the temperature characteristic
of 1/.beta. is substantially proportional to a temperature, being
5000 ppm/.degree. C. at the normal temperature. Thus, if a
temperature characteristic of the resistor R2 is equal to or lower
than 5000 ppm/.degree. C., being a primary characteristic with
respect to the temperature, a drain current I.sub.D1 has a positive
temperature characteristic, and an output current I.sub.0 of the
reference current circuit outputted through the current mirror
circuit is proportional to the temperature, realizing a PTAT
current source circuit. In addition, since the transistor M6
constitutes the current mirror circuit with the transistors M4 and
M5, a relation is represented by the following equation (142):
A drain current I.sub.D6 of the transistor M6 is converted into a
voltage by the output circuit, becoming a reference voltage
V.sub.REF. If a current flowing to the resistor R2 is
.gamma.I.sub.D6 (0<.gamma.<1), then the reference voltage
V.sub.REF is represented by the following equation (143):
By solving the equation (143) for .gamma., .gamma. is represented
by the following equation (144):
Accordingly, the reference voltage V.sub.REF is obtained by the
following equation (145) ##EQU46##
On the other hand, V.sub.GS3 is represented by the following
equation (146):
##EQU47##
The equation (145) is rewritten into the following equation (147):
##EQU48##
In this case, a temperature characteristic of a threshold voltage
V.sub.TH is represented by the following equation (148):
V.sub.T =V.sub.TH0 -.alpha.(T-T.sub.0) (148)
Here, .alpha. is about 2.3 mV/.degree. C. in a CMOS fabrication
process of the. MOS transistor having a low threshold voltage.
Accordingly, the output current I.sub.REF of the MOS reference
voltage circuit is represented by weighting and adding a term of
the threshold voltage V.sub.TH having a negative temperature
characteristic and a term of 1/.beta. having a positive temperature
characteristic. As a result, by changing weight factors, it is
possible to optionally set a temperature characteristic of the
reference current. An output voltage V.sub.REF is represented by
the following equation (149): ##EQU49##
A right side of the equation (149) is represented by weighting and
adding of the voltage values caused by inverse numbers of the
threshold voltage V.sub.TH having the negative temperature
characteristic and the transconductance parameter (mobility) having
the positive temperature characteristic. Accordingly, by changing
weight factors, it is possible to optionally set the temperature
characteristic of the output voltage V.sub.REF of the MOS reference
voltage circuit as described above. Specifically, a (W/L)/(W/L)
ratio, or a current mirror ratio and resistance values, and each
resistance ratio may be set.
In this case, the temperature characteristic of 1/.beta. as an
inverse number of the transconductance parameter .beta. is
substantially proportional to the temperature, which is 5000
ppm/.degree. C. at the normal temperature. The threshold voltage
V.sub.TH of the transistor M2 has a negative temperature
characteristic of about -2.3 mV/.degree. C. The temperature
characteristics of the resistance ratios (R.sub.2 /R.sub.1) and
R.sub.2 /(R.sub.2 +R.sub.3) are zero because of cancellation, and
K.sub.1 has no temperature characteristics. Thus, the output
voltage V.sub.REF of the MOS reference voltage circuit is decided
by the positive temperature characteristic of 5000 ppm/.degree. C.,
the negative temperature characteristic of the threshold voltage
V.sub.TH of the transistor M2, and about -2.3 mV/.degree. C.
In order to prevent the output voltage V.sub.REF of the MOS
reference voltage circuit from having any temperature
characteristics in the equation (149), the following equation (150)
is established: ##EQU50##
Accordingly, if V.sub.TH0 =0.7 V is set, the output voltage
V.sub.REF is obtained by the following equation (151):
##EQU51##
In this case, sine R.sub.3 /(R.sub.2 +R.sub.3)<1 is established,
if R.sub.3 /(R.sub.2 +R.sub.3)=0.7 is set, V.sub.REF =0.77 V is
established. In addition, as shown in FIG. 33, a current is
outputted through the current mirror circuit, and then the current
is converted into a voltage by an output circuit constituted of a
diode-connected transistor and two resistors, and outputted. Thus,
by series-connecting the current mirror circuit with n output
circuits having the different resistance ratios (R.sub.3 /(R.sub.2
+R.sub.3), two resistors at each stage, it is possible to obtain n
reference voltages having no temperature characteristics.
For example, if a power supply voltage has an allowance to increase
a voltage, the output circuits each if constituted of the
diode-connected transistor and the two resistors are
series-connected at n stages, a flowing current is shared, and the
two resistance values at each stage are made different from each
other. Accordingly, n different output voltages (V.sub.REF1,
V.sub.REF2, V.sub.REF3, . . . , V.sub.REFn) are obtained. Any of
these output voltages has no temperature characteristics.
Alternatively, as shown in FIG. 34, similar output circuits each
constituted of a diode-connected transistor and two resistors are
series-connected at n stages, and a flowing current is shared,
enabling output voltages to be nV.sub.REF. Needless to say, since a
voltage between stages can be outputted, voltages V.sub.REF,
2V.sub.REF, 3V.sub.REF, . . . , nV.sub.REF are also obtained. In
this case, no changes occur in a circuit current.
FIG. 23 shows a reference voltage circuit according to an eighth
embodiment of the present invention, specifically an embodiment of
a bipolar reference current circuit. Referring to FIG. 23, the
reference voltage circuit of the eighth embodiment of the present
invention is shown to be constructed in a manner that transistors
Q1 and Q2, and a resistor R1 constitute the bipolar Nagata current
mirror circuit. A feature of the bipolar Nagata current mirror
circuit is that there are a region where an output current (mirror
current) is monotonously increased with respect to an input current
(reference current), a peak point, and a region where the output
current (mirror current) is monotonously reduced with respect to
the input current (reference current). In this case, by transistors
Q4 and Q5 (Q6) constituting a current mirror circuit, the
transistors Q1 and Q2, and the resistor R1 constitute the bipolar
self-biased Nagata current mirror circuit.
Assuming that a DC current amplification factor of the transistor
is sufficiently near 1, by ignoring a base current, in the bipolar
Nagata current mirror circuit, from the equation (9), relations are
represented by the following equations (152) to (154):
Here, by solving the equations (152) to (154), a relation between
input and output currents in the bipolar Nagata current mirror
circuit is represented by the following equation (155):
At the peak point, with R.sub.1 I.sub.C1 =V.sub.T, I.sub.C2
=K.sub.1 I.sub.C1 /e is set: e=2.7183. Thus, with K.sub.1 =e,
I.sub.C2 =I.sub.C1 is set.
In this case, the transistors Q5 and Q4 constitute the current
mirror circuit, and the transistors Q1 and Q2 are respectively
driven by the transistors Q4 and Q5. Thus, the bipolar self-biased
Nagata reference current circuit is provided, and then a relation
is represented by the following equation (156):
Furthermore, since the following equation (157) is established,
##EQU52##
the equation (158) is obtained:
Here, K.sub.1 denotes a constant having no temperature
characteristics and, as described above, the thermal voltage
V.sub.T is represented by V.sub.T =kT/q, exhibiting the temperature
characteristic of 3333 ppm/.degree. C. Accordingly, if a
temperature characteristic of the resistor R1 is smaller than the
temperature characteristic of the thermal voltage V.sub.T, being a
primary characteristic with respect to a temperature, an output
reference current I.sub.REF (=I.sub.C1) of the reference current
circuit outputted through the current mirror circuit is
proportional to the temperature, realizing a PTAT current source.
In addition, since the transistor Q5 constitutes a current mirror
circuit with the transistors Q4 and Q6, a relation represented by
the following equation (159) is established:
A collector current I.sub.C6 of the transistor Q6 is converted into
a voltage by the output circuit, becoming a reference voltage
V.sub.REF. If a current flowing to the resistor R2 is
.gamma.I.sub.C6 (0<.gamma.<1), then the reference voltage
V.sub.REF is represented by the following equation (160):
By solving the equation (160) for .gamma., .gamma. is represented
by the following equation (161):
Thus, the reference voltage V.sub.REF is obtained by the following
equation (162): ##EQU53##
In the equation (162), a coefficient term R.sub.3 /(R.sub.2
+R.sub.3) is 0<R.sub.3 /(R.sub.2 +R.sub.3)<1. In a second
term {V.sub.BE3 +(R.sub.2 /R.sub.1)V.sub.T ln (K.sub.1)}, V.sub.BE3
has a negative temperature characteristic of about -1.9 mV/.degree.
C., and the thermal voltage V.sub.T has a positive temperature
characteristic of 0.0853 mV/.degree. C. Accordingly, in order to
prevent the reference voltage V.sub.REF to be outputted from having
any temperature characteristics, a temperature characteristic is
canceled by a voltage having a positive temperature characteristic
and a voltage having a negative temperature characteristic. That
is, in this case, a value of (R.sub.2 /R.sub.1)ln(K.sub.1) is 22.3,
and a voltage value of (R.sub.2 /R.sub.1)V.sub.T ln(K.sub.1) is
0.57V. Now, if V.sub.BE3 is 0.7 V, {V.sub.BE3 +(R.sub.2
/R.sub.1)V.sub.T ln(K.sub.1)}=1.27 V is obtained. Thus, sine
R.sub.3 /(R.sub.2 +R.sub.3)<1 is established, the reference
voltage V.sub.REF can be set equal to or lower than 1.27 V, e.g.,
1.0 V. In addition, as shown in FIG. 33, a current is outputted
through the current mirror circuit, and then the current is
converted into a voltage by an output circuit constituted of a
diode-connected transistor and two resistors, and outputted. Thus,
by series-connecting the current mirror circuit with n output
circuits having different resistance ratios (R.sub.3 /(R.sub.2
+R.sub.3), two resistors at each stage, it is possible to obtain n
reference voltages having no temperature characteristics.
For example, if a power supply voltage has an allowance to increase
a voltage, the output circuits each constituted of the
diode-connected transistor and the two resistors are
series-connected at n stages, a flowing current is shared, and the
two resistance values at each stage are made different from each
other. Accordingly, n different output voltages (V.sub.REF1,
V.sub.REF2, V.sub.REF3, . . . , V.sub.REFn) are obtained. Any of
these output voltages has no temperature characteristics.
Alternatively, as shown in FIG. 34, similar output circuits each
constituted of a diode-connected transistor and two resistors are
series-connected at n stages, and a flowing current is shared,
enabling output voltages to be nV.sub.REF. Needless to say, since a
voltage between stages can be outputted, voltages V.sub.REF,
2V.sub.REF, 3V.sub.REF, . . . , nV.sub.REF are also obtained. In
this case, no changes occur in a circuit current.
FIG. 24 shows the reference voltage circuit of the eighth
embodiment of the present invention, specifically a CMOS reference
current circuit of another embodiment. Referring to FIG. 24, the
reference voltage circuit of the eighth embodiment of the present
invention is shown to be constructed in a manner that transistors
M1 and M2 and a resistor R1 constitute the MOS Nagata current
mirror circuit. A feature of the MOS Nagata current mirror circuit
is that there are a region where an output current (mirror current)
is monotonously increased with respect to an input current
(reference current), a peak point, and a region where the output
current (mirror current) is monotonously reduced with respect to
the input current (reference current). In this case, by transistors
M4 and M5 (M6) constituting a current mirror circuit, the
transistors M1 and M2, and the resistor R1 constitute the CMOS
self-biased Nagata reference current circuit. In FIG. 24, the
transistor M1 is a unit transistor, and a ratio (W/L) of a gate
width W or a gate length L of the transistor M2 is K.sub.1 times
(K.sub.1 >1) as large as that of the unit transistor.
In the MOS Nagata current mirror circuit shown in FIG. 24, the
consistency of the circuit element is high, the channel length
modulation and a body effect are ignored, and a relation between a
drain voltage and a voltage between the gate and the source of the
MOS transistor is set according to a square law. Then, a drain
current of the MOS transistor M1 is represented by the following
equation (163):
I.sub.D1 =.beta.(V.sub.GS1 -V.sub.TH).sup.2 (163)
Furthermore, a drain current of the MOS transistor M2 is
represented by the following equation (164):
In addition, a relation represented by the following equation (165)
is established:
By solving the equations (163) to (165), a relation between the
input and output currents of the MOS Nagata current mirror circuit
is represented by the following equation (166): ##EQU54##
As in the case of the bipolar Nagata current mirror circuit, a
feature of the MOS Nagata current mirror circuit is that there are
a region where an output current (mirror current) is monotonously
increased with respect to an input current (reference current), a
peak point, and a region where the output current (mirror current)
is monotonously reduced with respect to the input current
(reference current). At the peak point, with I.sub.D1
=1/(4R.sub.1.sup.2.beta.), I.sub.D2 =K.sub.1 I.sub.D1 /4 is set.
Thus, with K.sub.1 =4, I.sub.D2 =I.sub.D1 is set. In this case, the
transistor M5 constitutes the current mirror circuit with the
transistor M4, and the transistors M1 and M2 are respectively
driven by the transistors M4 and M5. Therefore, the MOS self-biased
Nagata current circuit is provided. Then, a relation is represented
by the following equation (167):
I.sub.D1 =I.sub.D2 (167)
Furthermore, a relation represented by the following equation (168)
is established:
By solving the equations (166) to (168), then a relation
represented by the following equation (169) is obtained:
##EQU55##
Here, K.sub.1 denotes a constant having no temperature
characteristics. On the other hand, since mobility .mu. has a
temperature characteristic in the MOS transistor, temperature
dependence of the transconductance parameter .beta. is represented
by the equation (139). Here, .beta..sub.0 denotes a value of .beta.
at a normal temperature (300K). That is, an output current
I.sub.REF of the CMOS reference current circuit is represented by
the following equation (170): ##EQU56##
Here, K.sub.1 denotes a constant having no temperature
characteristics. As described above, the temperature characteristic
of 1/.beta. is substantially proportional to a temperature, being
5000 ppm/.degree. C. at the normal temperature. Thus, if a
temperature characteristic of the resistor R2 is equal to or lower
than 5000 ppm/.degree. C., being a primary characteristic with
respect to the temperature, a drain current I.sub.D1 has a positive
temperature characteristic, and an output current I.sub.REF of the
reference current circuit outputted through the current mirror
circuit is proportional to the temperature, realizing a PTAT
current source circuit.
In addition, since the transistor M6 constitutes the current mirror
circuit with the transistors M4 and M5, a relation is represented
by the following equation (171):
A drain current I.sub.D6 of the transistor M6 is converted into a
voltage by the output circuit, becoming a reference voltage
V.sub.REF. If a current flowing to the resistor R2 is
.gamma.I.sub.D6 (0<.gamma.<1), then the reference voltage
V.sub.REF is represented by the following equation (172):
By solving the equation (172) for .gamma., .gamma. is represented
by the following equation (173):
Accordingly, the reference voltage V.sub.REF is obtained by the
following equation (174) ##EQU57##
On the other hand, V.sub.GS3 is represented by the following
equation (175): ##EQU58##
The equation (175) is rewritten into the following equation (176):
##EQU59##
In this case, the temperature characteristic of the threshold
voltage V.sub.TH is represented by the following equation
(177):
Here, .alpha. is about 2.3 mV/.degree. C. in a CMOS fabrication
process of the MOS transistor having a low threshold voltage.
Accordingly, the output current I.sub.REF of the MOS reference
voltage circuit is represented by weighting and adding a term of
the threshold voltage V.sub.TH having a negative temperature
characteristic and a term of 1/.beta. having a positive temperature
characteristic. As a result, by changing weight factors, it is
possible to optionally set a temperature characteristic of the
reference current.
An output voltage V.sub.REF is represented by the following
equation (178): ##EQU60##
A right side of the equation (178) is represented by weighting and
adding of voltage values caused by inverse numbers of the threshold
voltage V.sub.TH having the negative temperature characteristic and
the transconductance parameter (mobility) having the positive
temperature characteristic. Accordingly, by changing weight
factors, it is possible to optionally set a temperature
characteristic of the output voltage V.sub.REF of the MOS reference
voltage circuit as described above. Specifically, a (W/L)/(W/L)
ratio, or a current mirror ratio and resistance values, and each
resistance ratio may be set.
In this case, the temperature characteristic of 1/.beta. as an
inverse number of the transconductance parameter .beta. is
substantially proportional to the temperature, which is 5000
ppm/.degree. C. at the normal temperature. The threshold voltage
V.sub.TH of the transistor M2 has a negative temperature
characteristic of about -2.3 mV/.degree. C. The temperature
characteristics of the resistance ratios (R.sub.2 /R.sub.1) and
R.sub.2 /(R.sub.2 +R.sub.3) are zero because of cancellation, and
K.sub.1 has no temperature characteristics. Thus, the output
voltage V.sub.REF of the MOS reference voltage circuit is decided
by the positive temperature characteristic of 5000 ppm/.degree. C.,
the negative temperature characteristic of the threshold voltage
V.sub.TH of the transistor M2, and about -2.3 mV/.degree. C.
In order to prevent the output voltage V.sub.REF of the MOS
reference voltage circuit from having any temperature
characteristics in the equation (149), the following equation (179)
is established: ##EQU61##
Accordingly, if V.sub.TH0 =0.7 V is set, the output voltage
V.sub.REF is obtained by the following equation (180):
##EQU62##
In this case, sine R.sub.3 /(R.sub.2 +R.sub.3)<1 is established,
if R.sub.3 /(R.sub.2 +R.sub.3)=0.7 is set, V.sub.REF =0.77 V is
established, and an operation is possible from a power supply
voltage of about 1.0 V. In addition, as shown in FIG. 33, a current
is outputted through the current mirror circuit, and then the
current is converted into a voltage by an output circuit
constituted of a diode-connected transistor and two resistors, and
outputted. Thus, by series-connecting the current mirror circuit
with n output circuits having different resistance ratios (R.sub.3
/(R.sub.2 +R.sub.3), two resistors at each stage, it is possible to
obtain n reference voltages having no temperature
characteristics.
For example, if a power supply voltage has an allowance to increase
a voltage, the output circuits each constituted of the
diode-connected transistor and the two resistors are
series-connected at n stages, a flowing current is shared, and the
two resistance values at each stage are made different from each
other. Accordingly, n different output voltages (V.sub.REF1,
V.sub.REF2, V.sub.REF3, . . . , V.sub.REFn) are obtained. Any of
these output voltages has no temperature characteristics.
Alternatively, as shown in FIG. 34, similar output circuits each
constituted of a diode-connected transistor and two resistors are
series-connected at n stages, and a flowing current is shared,
enabling output voltages to be nV.sub.REF. Needless to say, since a
voltage between stages can be outputted, voltages V.sub.REF,
2V.sub.REF, 3V.sub.REF, . . . , nV.sub.REF are also obtained. In
this case, no changes occur in a circuit current.
FIG. 25 shows a reference voltage circuit according to a ninth
embodiment of the present invention, specifically an embodiment of
a bipolar reference current circuit. Referring to FIG. 25, the
reference voltage circuit of the ninth embodiment of the present
invention is shown to be constructed in a manner that transistors
Q1 and Q2, and a resistor R1 constitute the bipolar Widlar current
mirror circuit. Assuming that a DC current amplification factor of
the transistor is sufficiently near 1, by ignoring a base current,
in the bipolar Widlar current mirror circuit, from the equation
(9), relations are represented by the following equations (181) to
(183):
Here, by solving the equations (181) to (183), a relation between
input and output currents in the bipolar Widlar current mirror
circuit is represented by the following equation (184):
Thus, the relation between the input and output currents of the
bipolar Widlar current mirror circuit is just a inverse of a
relation between input and output currents of the bipolar inverse
Widlar current mirror circuit, and an output current (mirror
current) is monotonously increased with respect to an input current
(reference current).
In this case, the transistor Q5 constitutes the current mirror
circuit with the transistor Q4, and the transistors Q1 and Q2 are
respectively driven by the transistors Q4 and Q5. Thus, the bipolar
self-biased Widlar reference current circuit is provided, and then
a relation is represented by the following equation (185):
Furthermore, since the following equation (186) is established,
##EQU63##
the equation (187) is obtained:
Here, K.sub.1 denotes a constant having no temperature
characteristics and, as described above, the thermal voltage
V.sub.T is represented by V.sub.T =kT/q, exhibiting a temperature
characteristic of 3333 ppm/.degree. C. Accordingly, if a
temperature characteristic of the resistor R1 is smaller than the
temperature characteristic of the thermal voltage V.sub.T, being a
primary characteristic with respect to a temperature, an output
current I.sub.REF (=I.sub.C1) of the reference current circuit
outputted through the current mirror circuit is proportional to the
temperature, realizing a PTAT current source circuit. In addition,
since the transistor Q5 constitutes a current mirror circuit with
the transistors Q4 and Q6, a relation represented by the following
equation (188) is established:
I.sub.C4 =I.sub.C5 =I.sub.C6 =I.sub.C1 =I.sub.C2 =(V.sub.T
/R.sub.1)ln(K.sub.1) (188)
A collector current I.sub.C6 of the transistor Q6 is converted into
a voltage by the output circuit, becoming a reference voltage
V.sub.REF. If a current flowing to the resistor R2 is
.gamma.I.sub.C6 (0<.gamma.<1), then the reference voltage
V.sub.REF is represented by the following equation (189):
By solving the equation (189) for .gamma., .gamma. is represented
by the following equation (190):
Thus, the reference voltage V.sub.REF is obtained by the following
equation (191): ##EQU64##
In the equation (191), a coefficient term R.sub.3 /(R.sub.2
+R.sub.3) is 0<R.sub.3 /(R.sub.2 +R.sub.3)<1. In a second
term {V.sub.BE3 +(R.sub.2 /R.sub.1)V.sub.T ln(K.sub.1)}, V.sub.BE3
has a negative temperature characteristic of about -1.9 mV/.degree.
C., and the thermal voltage V.sub.T has a positive temperature
characteristic of 0.0853 mV/.degree. C. Accordingly, in order to
prevent the reference voltage V.sub.REF to be outputted from having
any temperature characteristics, a temperature characteristic is
canceled by a voltage having a positive temperature characteristic
and a voltage having a negative temperature characteristic. That
is, in this case, a value of (R.sub.2 /R.sub.1)ln(K.sub.1) is 22.3,
and a voltage value of (R.sub.2 /R.sub.1)V.sub.T ln(K.sub.1) is
0.57 V. Now, if V.sub.BE3 is 0.7 V, {V.sub.BE3 +(R.sub.2
/R.sub.1)V.sub.T ln(K.sub.1)}=1.27 V is obtained. Thus, sine
R.sub.3 /(R.sub.2 +R.sub.3)<1 is established, the reference
voltage V.sub.REF can be set equal to or lower than 1.27 V, e.g.,
1.0 V. In addition, as shown in FIG. 33, a current is outputted
through the current mirror circuit, and then the current is
converted into a voltage by an output circuit constituted of a
diode-connected transistor and two resistors, and outputted. Thus,
by series-connecting the current mirror circuit with n output
circuits having different resistance ratios (R.sub.3 /(R.sub.2
+R.sub.3), two resistors at each stage, it is possible to obtain n
reference voltages having no temperature characteristics.
For example, if a power supply voltage has an allowance to increase
a voltage, the output circuits each constituted of the
diode-connected transistor and the two resistors are
series-connected at n stages, a flowing current is shared, and the
two resistance values at each stage are made different from each
other. Accordingly, n different output voltages (V.sub.REF1,
V.sub.REF2, V.sub.REF3, . . . , V.sub.REFn) are obtained. Any of
these output voltages has no temperature characteristics.
Alternatively, as shown in FIG. 34, similar output circuits each
constituted of a diode-connected transistor and two resistors are
series-connected at n stages, and a flowing current is shared,
enabling output voltages to be nV.sub.REF. Needless to say, since a
voltage between stages can be outputted, voltages V.sub.REF,
2V.sub.REF, 3V.sub.REF, . . . , nV.sub.REF are also obtained. In
this case, no changes occur in a circuit current.
FIG. 26 shows the reference voltage circuit of the ninth embodiment
of the present invention, specifically a CMOS reference current
circuit of another embodiment. referring to FIG. 26, the reference
voltage circuit of the ninth embodiment of the present invention is
shown to be constructed in a manner that transistors M1 and M2 and
a resistor R1 constitute the MOS Widlar current mirror circuit. As
in the case of the bipolar Widlar current mirror circuit, in the
MOS Widlar current mirror circuit, an output current (mirror
current) is monotonously increased with respect to an input current
(reference current). In this case, by transistors M5 and M6
constituting a current source, the transistors M1 and M2, and the
resistor R1 constitute the CMOS self-biased Widlar reference
current circuit.
In the MOS Widlar current mirror circuit shown in FIG. 26, the
transistor M1 is a unit transistor, and a ratio (W/L) of a gate
width W or a gate length L of the transistor M2 is K.sub.1 times
(K.sub.1 >1) as large as that of the unit transistor. The
consistency of the circuit element is high, the channel length
modulation and a body effect are ignored, and a relation between a
drain voltage and a voltage between the gate and the source of the
MOS transistor is set according to a square law. Then, the drain
currents of the MOS transistors M1 and M2 are represented by the
following equations (192) and (193):
Furthermore, a relation represented by the following equation (194)
is established:
Here, by solving the equations (192) to (194), a relation between
input and output currents of the MOS Widlar current mirror circuit
is represented by the following equation (195): ##EQU65##
The relation between the input and output currents of the MOS
Widlar current mirror circuit is just a inverse of a relation
between input and output currents of the MOS inverse Widlar current
mirror circuit. In this case, the transistors M1 and M2 are
respectively driven by the transistors M4 and M5. Thus, the MOS
self-biased Widlar current circuit is provided. A relation is
represented by the following equation (196):
Furthermore, a relation represented by the following equation (197)
is established:
By solving the equations (192) to (197), a relation represented by
the following equation (198) is obtained: ##EQU66##
Here, K.sub.1 denotes a constant having no temperature
characteristics. On the other hand, since the mobility .mu. has a
temperature characteristic in the MOS transistor, the temperature
dependence of the transconductance parameter .beta. is represented
by the equation (139), and the output current I.sub.REF of the CMOS
reference current circuit is obtained by the following equation
(199): ##EQU67##
Here, K.sub.1 denotes a constant having no temperature
characteristics. As described above, the temperature characteristic
of 1/.beta. is substantially proportional to a temperature, being
5000 ppm/.degree. C. at the normal temperature. Thus, if a
temperature characteristic of the resistor R2 is equal to or lower
than 5000 ppm/.degree. C., being a primary characteristic with
respect to the temperature, a drain current I.sub.D1 has a positive
temperature characteristic, and an output current I.sub.0 of the
reference current circuit outputted through the current mirror
circuit is proportional to the temperature, realizing a PTAT
current source circuit.
In addition, since the transistor M6 constitutes the current mirror
circuit with the transistors M4 and M5, a relation is represented
by the following equation (200):
A drain current I.sub.D6 of the transistor M6 is converted into a
voltage by the output circuit, becoming a reference voltage
V.sub.REF. If a current flowing to the resistor R2 is
.gamma.I.sub.D6 (0<.gamma.<1), then the reference voltage
V.sub.REF is represented by the following equation (201):
V.sub.REF =V.sub.BE3 +R.sub.2.gamma.I.sub.D6 =R.sub.3
(1-.gamma.)I.sub.D6 (201)
By solving the equation (201) for .gamma., .gamma. is represented
by the following equation (202):
Accordingly, the reference voltage V.sub.REF is obtained by the
following equation (203) ##EQU68##
On the other hand, V.sub.GS3 is represented by the following
equation (204): ##EQU69##
The equation (204) is rewritten into the following equation (205):
##EQU70##
In this case, a temperature characteristic of the threshold voltage
V.sub.TH is represented by the following equation (206):
Here, .alpha. is about 2.3 mV/.degree. C. in a CMOS fabrication
process of the MOS transistor having a low threshold voltage.
Accordingly, the output current I.sub.REF of the MOS reference
voltage circuit is represented by weighting and adding a term of
the threshold voltage V.sub.TH having a negative temperature
characteristic and a term of 1/.beta. having a positive temperature
characteristic. As a result, by changing weight factors, it is
possible to optionally set a temperature characteristic of the
reference current. An output voltage V.sub.REF is represented by
the following equation (207): ##EQU71##
A right side of the equation (207) is represented by weighting and
adding of voltage values caused by inverse numbers of the threshold
voltage V.sub.TH having the negative temperature characteristic and
the transconductance parameter (mobility) having the positive
temperature characteristic. Accordingly, by changing weight
factors, it is possible to optionally set a temperature
characteristic of the output voltage V.sub.REF of the MOS reference
voltage circuit as described above. Specifically, a (W/L)/(W/L)
ratio, or a current mirror ratio and resistance values, and each
resistance ratio may be set.
In this case, a temperature characteristic of 1/.beta. as an
inverse number of the transconductance parameter .beta. is
substantially proportional to a temperature, which is 5000
ppm/.degree. C. at a normal temperature. The threshold voltage
V.sub.TH of the transistor M2 has a negative temperature
characteristic of about -2.3 mV/.degree. C. The temperature
characteristics of the resistance ratios (R.sub.2 /R.sub.1) and
R.sub.2 /(R.sub.2 +R.sub.3) are zero because of cancellation, and
K.sub.1 has no temperature characteristics. Thus, the output
voltage V.sub.REF of the MOS reference voltage circuit is decided
by the positive temperature characteristic of 5000 ppm/.degree. C.,
the negative temperature characteristic of the threshold voltage
V.sub.TH of the transistor M2, and about -2.3 mV/.degree. C.
In order to prevent the output voltage V.sub.REF of the MOS
reference voltage circuit from having any temperature
characteristics in the equation (207), the following equation (208)
is established: ##EQU72##
Accordingly, if V.sub.TH0 =0.7 V is set, the output voltage
V.sub.REF is obtained by the following equation (209):
##EQU73##
In this case, sine R.sub.3 /(R.sub.2 +R.sub.3)<1 is established,
if R.sub.3 /(R.sub.2 +R.sub.3)=0.7 is set, V.sub.REF =0.77 V is
established, and an operation is possible from a power supply
voltage of about 1.0 V. In addition, as shown in FIG. 33, a current
is outputted through the current mirror circuit, and then the
current is converted into a voltage by an output circuit
constituted of a diode-connected transistor and two resistors, and
outputted. Thus, by series-connecting the current mirror circuit
with n output circuits having different resistance ratios (R.sub.3
/(R.sub.2 +R.sub.3), two resistors at each stage, it is possible to
obtain n reference voltages having no temperature
characteristics.
For example, if a power supply voltage has an allowance to increase
a voltage, the output circuits each constituted of the
diode-connected transistor and the two resistors are
series-connected at n stages, a flowing current is shared, and the
two resistance values at each stage are made different from each
other. Accordingly, n different output voltages (V.sub.REF1,
V.sub.REF2, V.sub.REF3, . . . , V.sub.REFn) are obtained. Any of
these output voltages has no temperature characteristics.
Alternatively, as shown in FIG. 34, similar output circuits each
constituted of a diode-connected transistor and two resistors are
series-connected at n stages, and a flowing current is shared,
enabling output voltages to be nV.sub.REF. Needless to say, since a
voltage between stages can be outputted, voltages V.sub.REF,
2V.sub.REF, 3V.sub.REF, . . . , nV.sub.REF are also obtained. In
this case, no changes occur in a circuit current.
Next, description will be made of a tenth embodiment of the present
invention. FIG. 27 shows a reference voltage circuit according to
the tenth embodiment of the present invention, specifically an
embodiment of a bipolar reference voltage circuit. Referring to
FIG. 27, the reference voltage circuit of the tenth embodiment of
the present invention is shown to be constructed in a manner that
transistors Q1 and Q2, and a resistor R1 constitute the bipolar
inverse Widlar current mirror circuit. In this case, a resistor
R.sub.C and a capacity C.sub.C are both for phase compensation.
This circuit is constructed in a manner that in the circuit of FIG.
21 showing the embodiment of the bipolar reference voltage circuit
of the seventh embodiment of the present invention, the
self-biasing method is changed, a transistor Q3 is added to set
collector voltages of the transistors Q1 and Q2 substantially equal
to each other, the transistor Q5 is driven by the transistor Q3,
and collector currents of the transistors Q6, Q7 and Q8
constituting the current mirror circuit with the transistor Q5 are
reduced without being affected by the base width modulation (Early
voltages). Thus, a reference voltage V.sub.REF to be obtained is
similarly represented by the equation (131), and a similar
advantage is provided.
FIG. 28 shows the reference voltage circuit of the tenth embodiment
of the present invention, specifically a MOS reference voltage
circuit of another embodiment. Referring to FIG. 28, the reference
voltage circuit of the tenth embodiment of the present invention is
shown to be constructed in a manner that transistors M1 and M2, and
a resistor R1 constitute the MOS inverse Widlar current mirror
circuit. In this case, a resistor R.sub.C and a capacity C.sub.C
care both for phase compensation. This circuit is constructed in a
manner that in the circuit of FIG. 22 showing the embodiment of the
MOS reference voltage circuit of the eighth embodiment of the
present invention, the self-biased method is changed, a transistor
M3 is added to set drain voltages of the transistors M1 and M2
substantially equal to each other, the transistor M5 is driven by
the transistor M3, and the drain currents of the transistors M6, M7
and M8 constituting the current mirror circuit with the transistor
M5 are reduced without being affected by the channel length width
modulation. Thus, a reference voltage V.sub.REF to be obtained is
similarly represented by the equation (149), and a similar
advantage is provided.
Likewise, FIG. 29 shows a reference voltage circuit according to an
eleventh embodiment of the present invention, specifically an
embodiment of a bipolar reference voltage circuit. Referring to
FIG. 29, the reference voltage circuit of the eleventh embodiment
of the present invention is shown to be constructed in a manner
that transistors Q1 and Q2, and a resistor R1 constitute the
bipolar Nagata current mirror circuit. In this case, a resistor
R.sub.C and a capacity C.sub.C are both for phase compensation.
This circuit is constructed in a manner that in the circuit of FIG.
23 showing the embodiment of the bipolar reference voltage circuit
of the eighth embodiment of the present invention, the self-biased
method is changed, a transistor Q3 is added to set the collector
bias voltages of the transistors Q1 and Q2 substantially equal to
each other, the transistor Q5 is driven by the transistor Q3, and
collector currents of the transistors Q6, Q7 and Q8 constituting
the current mirror circuit with the transistor Q5 are reduced
without being affected by the base width modulation (Early
voltages). Thus, a reference voltage V.sub.REF to be obtained is
similarly represented by the equation (162), and a similar
advantage is provided.
FIG. 30 shows the reference voltage circuit of the eleventh
embodiment of the present invention, specifically a MOS reference
voltage circuit of another embodiment. Referring to FIG. 30, the
reference voltage circuit of the eleventh embodiment of the present
invention is shown to be constructed in a manner that transistors
M1 and M2, and a resistor R1 constitute the MOS Nagata current
mirror circuit. In this case, a resistor R.sub.C and a capacity
C.sub.C are both for phase compensation. This circuit is
constructed in a manner that in the circuit of FIG. 24 showing the
embodiment of the MOS reference voltage circuit of the ninth
embodiment of the present invention, the self-biased method is
changed, a transistor M3 is added to set the drain voltages of the
transistors M1 and M2 substantially equal to each other, the
transistor M5 is driven by the transistor M3, and the drain
currents of the transistors M6, M7 and M8 constituting the current
mirror circuit with the transistor M5 are reduced without being
affected by the channel length width modulation. Thus, a reference
voltage V.sub.REF to be obtained is similarly represented by the
equation (178), and a similar advantage is provided.
FIG. 31 shows a reference voltage circuit according to a twelfth
embodiment of the present invention, specifically an embodiment of
a bipolar reference voltage circuit. Referring to FIG. 31, the
reference voltage circuit of the twelfth embodiment of the present
invention is shown to be constructed in a manner that transistors
Q1 and Q2, and a resistor R1 constitute the bipolar Widlar current
mirror circuit. In this case, a resistor R.sub.C and a capacity
C.sub.C are both for phase compensation. This circuit is
constructed in a manner that in the circuit of FIG. 25 showing the
embodiment of the bipolar reference voltage circuit of the ninth
embodiment of the present invention, the self-biased method is
changed, a transistor Q3 is added to set the collector bias
voltages of the transistors Q1 and Q2 substantially equal to each
other, the transistor Q5 is driven by the transistor Q3, and
collector currents of the transistors Q6, Q7 and Q8 constituting
the current mirror circuit with the transistor Q5 are reduced
without being affected by the base width modulation (Early
voltages). Thus, a reference voltage V.sub.REF to be obtained is
similarly represented by the equation (191), and a similar
advantage is provided.
FIG. 32 shows the reference voltage circuit of the twelfth
embodiment of the present invention, specifically a MOS reference
voltage circuit of another embodiment. Referring to FIG. 32, the
reference voltage circuit of the twelfth embodiment of the present
invention is shown to be constructed in a manner that transistors
M1 and M2, and a resistor R1 constitute the CMOS Widlar current
mirror circuit. In this case, a resistor R.sub.C and a capacity
C.sub.C are both for phase compensation. This circuit is
constructed in a manner that in the circuit of FIG. 26 showing the
embodiment of the MOS reference voltage circuit of the ninth
embodiment of the present invention, the self-biased method is
changed, a transistor M3 is added to set the drain voltages of the
transistors M1 and M2 substantially equal to each other, the
transistor M5 is driven by the transistor M3, and the drain
currents of the transistors M6, M7 and M8 constituting the current
mirror circuit with the transistor M5 are reduced without being
affected by the channel length width modulation. Thus, a reference
voltage V.sub.REF to be obtained is similarly represented by the
equation (207), and a similar advantage is provided.
In addition, the reference voltage circuits of the tenth to twelfth
embodiments of the present invention can be series-connected as
shown in FIG. 33 or FIG. 34.
Furthermore, a starting-up circuit is necessary for staring a
self-biased circuit, which has been omitted in the description of
the operation thus far for simplicity. For example, as a simple
starting-up circuit, one disclosed in Japanese Patent Application
Laid-Open No. 3114561/1996 by the inventors is known.
As apparent from the foregoing, according to the reference current
circuit of the present invention, it is possible to provide a
highly accurate reference current circuit for outputting a current
value proportional to a temperature without being affected by any
Early voltages. It is because the negative feedback current loop is
formed in the reference current circuit to realize the PTAT current
source to be stably operated, and the collector (or drain) voltages
of the two transistors constituting the non-linear current mirror
circuit are set to the fixed values. According to the reference
current circuit of the present invention, it is possible to realize
a reference current circuit for outputting an optional current
value having an optional temperature characteristic. It is because
the reference current output is obtained by adding the current
proportional to the temperature of the PTAT current source and the
current proportional to VEE (or VGS) of the transistor having a
negative temperature characteristic. In addition, according to the
reference current circuit of the present invention, an operation
voltage of the circuit can be set equal to or lower than 1 V. It is
because the reference current circuit is realized by the circuitry
for driving one transistor stage by the current mirror circuit,
thereby reducing the number of longitudinally loaded circuits.
According to the reference voltage circuit of the present
invention, the temperature characteristic is canceled by sharing
the output current proportional to the temperature by the
transistor diode-connected through the resistor (R2), and the
resistor (R3) connected in parallel therewith, and thus providing
the output voltage R3/(R2+R3) times (R3/(R2+R3)<1) as large as
that of the conventional reference voltage circuit. As a result, it
is possible to realize a reference voltage circuit for outputting a
voltage of 1.2 V or lower, having no temperature characteristics.
According to the reference voltage circuit of the present
invention, since the circuit is realized by the current mirror
circuit without using any operation amplifiers, it is possible to
provide a reference voltage circuit to be operated from a power
supply voltage of about 1 V. Moreover, according to the reference
voltage circuit of the present invention, the collector (or drain)
voltages of the two transistors constituting the non-linear current
mirror circuit are set to the fixed values. As a result, it is
possible to realize a highly accurate reference voltage circuit,
which is not affected by any base width modulation (Early voltages)
or any channel length modulation.
* * * * *