U.S. patent number 6,505,279 [Application Number 09/135,410] was granted by the patent office on 2003-01-07 for microcontroller system having security circuitry to selectively lock portions of a program memory address space.
This patent grant is currently assigned to Silicon Storage Technology, Inc.. Invention is credited to Eugene Feng, Gary Phillips.
United States Patent |
6,505,279 |
Phillips , et al. |
January 7, 2003 |
Microcontroller system having security circuitry to selectively
lock portions of a program memory address space
Abstract
A microcontroller system includes a security lock circuit to
regulate access requests to contents of locations of a program
memory. The regulation is selective, based on an operating mode of
the security lock circuit, and also based on the source of the
access request and the location of the program memory for which the
access request is intended. Among other advantages, one major
advantage provided by the security lock circuit is that concurrent
programming (i.e., programming of one area of memory using
instructions executing from another area of memory) can be
initiated under predetermined secure conditions.
Inventors: |
Phillips; Gary (San Jose,
CA), Feng; Eugene (San Jose, CA) |
Assignee: |
Silicon Storage Technology,
Inc. (Sunnyvale, CA)
|
Family
ID: |
22467985 |
Appl.
No.: |
09/135,410 |
Filed: |
August 14, 1998 |
Current U.S.
Class: |
711/163; 711/152;
712/43; 712/E9.007; 712/E9.055 |
Current CPC
Class: |
G06F
9/24 (20130101); G06F 9/3802 (20130101) |
Current International
Class: |
G06F
9/24 (20060101); G06F 9/38 (20060101); G06F
013/00 () |
Field of
Search: |
;711/103,163,164,154,152
;713/201,200 ;340/825.34 ;365/185.4,185.04 ;712/226,43 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
"P83CE558/P80CE558/P8CE558 Single-chip 8-bit microcontroller",
Preliminary Specification IC20 Data Handbook, Phillips
Semiconductors, Aug. 6, 1996..
|
Primary Examiner: Donaghue; Larry D.
Attorney, Agent or Firm: Gray Cary Ware & Freidenrich
LLP
Claims
What is claimed is:
1. A method of operating a microcontroller system in one of a
plurality of modes of operation, said system having a
microcontroller and a first programmable memory block storing a
first program, and a second programmable memory block storing a
second program said method of operating said one mode comprising:
reading said first program from of said first programmable memory
block by said microcontroller; reading said second program from
said second programmable memory block; and reprogramming said first
program solely by executing said second program.
2. The method of claim 1 wherein said microcontroller further
blocks writing into said first and second programmable memory
blocks by signals external to said microcontroller system while
reading said first program and reading and executing said second
program.
3. The method of claim 2 wherein said microcontroller system
further comprising a security lock circuit and wherein said
microcontroller system operates in response to said security lock
circuit.
4. The method of claim 1 wherein said first programmable memory
block and said second programmable memory block are portions of a
flash memory.
5. A unitary integrated microcontroller system operable in one of a
plurality of modes comprising: a microcontroller; a first
programmable memory block for storing a first program; a second
programmable memory block for storing a second program; a storage
for storing a security value; and a security circuit responsive to
said security value for operating in said one mode, causing said
microcontroller to read said first program from said first
programmable memory block, read said second program from said
second programmable memory block, and reprogramming said first
program solely by executing said second program.
6. The system of claim 5 wherein said security circuit responsive
to said security value further causes said first and second
programmable memory blocks from being written by signals external
to said microcontroller system.
7. The system of claim 6 wherein said first programmable memory
block and said second programmable memory block are portions of a
flash memory.
Description
TECHNICAL FIELD
The present invention relates to microcontroller systems having
flash memory in a program memory address space and, in particular,
to a microcontroller having security circuitry such that a program
executing from one portion of the flash memory of the
microcontroller can securely program or reprogram another portion
of the flash memory.
BACKGROUND
Microcontroller systems-including memory are known in the art. With
a conventional microcontroller system, blocks of the memory may be
locked such that a locked block cannot be interrogated. This
locking thus secures program code contained in the locked blocks
from unauthorized access by firmware piraters and from accidental
erasing and programming.
However, conventionally, neither can the locked blocks be
conveniently reprogrammed or accessed by -an authorized user. It is
desirable for a microcontroller system to be configurable such that
blocks of memory can be locked from unauthorized interrogation or
code corruption, but can also be reprogrammed and/or accessed under
a predetermined secure environment.
SUMMARY
In accordance with the present invention, a microcontroller system
includes a security lock circuit to regulate access requests to
contents of locations of a program memory. The regulation is
selective, based on an operating mode of the security-lock circuit,
and also based on the source of the access request and the location
of the program memory for which the access request is intended.
Among other advantages, one major advantage provided by the
security lock circuit is that concurrent programming (i.e.,
programming of one area of memory using instructions executing from
another area of memory) can be initiated under predetermined secure
conditions.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block functional illustration of an embodiment of a
microcontroller system.
FIG. 2 is a block functional illustration of an embodiment of a
flash operation controller of the FIG. 1 microcontroller
system.
FIGS. 3A to 3C illustrate various states of program memory
organization of the FIG. 1 microcontroller system.
DETAILED DESCRIPTION
FIG. 1 illustrates, in block functional form, a microcontroller
system 100 in accordance with an embodiment of the present
invention, unitarily formed in an integrated circuit. The system
100 includes a microcontroller unit (MCU) core 103, designated by
part number T8052 in FIG. 1. In the described (preferred)
embodiment, the microcontroller system 100 is compatible with
standard 8xC58 microcontroller devices.
Embedded program memory 102 includes two independent program memory
blocks 102a and 102b. The program memory blocks 102a and 102b are
erasable and reprogrammable, and are preferably flash EEPROM of the
type disclosed, for example, in U.S. Pat. No. 5,572,054, issued
Nov. 5, 1996 and assigned to Silicon Storage Technology, Inc. of
Sunnyvale, Calif., the assignee of the present patent application.
Program memory block 102a (designated, for convenience of
reference, as the "lower program block") is addressable at the
standard 87C58 32 Kbytes of internal ROM area, and program memory
block 102b (designated for convenience of reference as the "upper
program memory block") is, addressable at the high address end of
the 8xC5x architecture. In addition, the microcontroller system 100
is configurable to address up to 64 Kbytes of program memory (not
shown) external to the system 100. The system 100 also includes
on-chip RAM (not shown) and is configurable to address external
data RAM (not shown).
A flash operation controller 104 (shown in more detail in FIG. 2,
discussed later) includes circuitry for controlling access to and
from the program flash memory 102. A command/address decoder 106
interfaces the MCU core 103 to the addressable memory (whether
program memory 102 or other addressable memory, internal or
external), I/O ports, and configuration registers. Some of the
configuration registers, particularly those within the flash
operation controller, are discussed in greater detail later. When
the system 100 is operating with the MCU core 103 (as opposed to an
external processor, discussed below), this is known as "normal
mode".
I/O pads interface. 108 includes circuitry for interfacing the
various components of the system 100 to external devices (not
shown), for example, external memory or an external host. Finally,
test mode controller 110 assists in controlling the system 100 when
it is operating in "external host mode", wherein an external "host"
processor (not shown) is operating in place of the MCU core 103. An
example of an external host is a PCB tester automated test
equipment, a PC-controlled development board, or an OTP (one-time
programmable) MCU programmer. During external host mode, in
response to hardware commands decoded from control signal input
pins, the system 100 performs test, erase and/or programming
functions.
Security functions of the microcontroller system 100 are now
discussed with reference to FIG. 2, which is a more detailed
functional diagram of the flash operation controller 104. In the
context of the present invention, a primary function of the flash
operation controller 104 is to control read and/or write access to
the blocks 102a and 102b of the program memory 102, in accordance
with the value stored in a "security byte". Specifically, the flash
control unit 201 controls such access responsive to the value of
the security byte, as indicated by a field of the SuperFlash.RTM.
Configuration register (SFCF) 202 which contains a decoding of the
security byte. The security byte is located at the highest address
location, FFFFh, of the microcontroller system 100 memory space.
That is, the security byte is located at the highest location in
upper program memory block 102b.
Depending on the value of the security byte, either the entire
program memory 102 may be locked; just the upper program memory
block 102b may be locked; or both the lower program memory block
102a and the upper program memory block 102b may be unlocked.
(Again, the term "value of the security byte" is a shorthand
notation herein for the value of the field in the SFCF register 202
that is a decoding of the security byte.) Precisely what it means
for a block of memory to be "locked" or "unlocked" is discussed
later. Table 1 shown below provides a summary of the effect that a
particular value of the security byte has on the security functions
of the system 100.
TABLE 1 Sec SFCF Blk Block Sector Write Burst Verify Byte (6:5) EA#
Sel Erase Erase Byte Write Byte Description FF 00 X X Y Y Y Y Y No
lock 55 11 X X N N N N N Both locked F5 01 X 0 Y Y Y Y Y Only block
1 (4KB) is X 1 N N N N N locked 05 10 X 1 N N N N N Both locked but
block 0 is 0 0 N N N N N programmable by software 1 0 Y Y Y Y Y
code resided in block 1 Note: SecByte = Value of Security Byte at
location FFFFh; SFCF(6:5) = Bit 5 and 6 of SFCF register; EA# =
Ext. Access enable input pin: 1 - running code from internal
memory, 0 - running code from external enable; blkSel = Block
Select signal (internal): 1 - block 1 (4Kx8), 0 - block 0 (32Kx8);
X = don't care; Y = command allowed; N = command not allowed.
When the security byte has a value FFh, both the program memory
block 102a and program memory block 102b are unlocked. When the
system 100 is delivered from the factory, or after a CHIP ERASE
function whereby the contents of the program memory 102 are erased
and there is no need for security, the default value of the
security byte is FFh.
Referring also to Table 2 shown below, if the security byte value
is other than FFh (i.e., has an "activated" value), then security
is activated to lock at least one of the program memory blocks 102a
and 102b. In this case, the "move constant" (MOVC) instruction,
which in some instances could be used for read access of data from
the program memory 102, is denied read access when the location of
the MOVC instruction itself could be in either an unlocked flash
memory location (i.e., a portion of the flash memory 102 is
unlocked, as indicated by the activated value of the security byte)
or may be in an external memory (as indicated by the signal (D at
an External Enable, or EA#, input pin). Therefore, the contents of
the internal flash program memory 102 are prevented from being read
undesirably when any level of security is activated.
TABLE 2 Internal and External Program Memory Access with Security
Lock activated (the value of the security byte is neither 00h nor
FFh). ACCESS TO LOCKED ACCESS TO UNLOCKED OR PROGRAM EXTERNAL
PROGRAM INSTRUCTIONS MEMORY MEMORY MOVC in locked YES YES program
memory MOVC in unlocked or NO YES external program memory
The effect of the security byte on program memory 102 programming
operations (i.e., write access) is now discussed. If the system 100
is in external host mode and the security byte. value is other than
FFh, the following external host mode commands are not allowed on
the locked program memory 102: sector erase, to erase the addressed
sector; block erase, to erase the addressed block; write byte, to
write a byte to the addressed location; burst write, to write an
entire addressed row by burst writing sequentially within the row
if the byte location has been successfully erased and not yet
programmed; and verify byte, to read a code byte from the addressed
location.
The read ID function, to read the chip "signature" and
identification registers, is allowed even when the security byte is
not FFh.
Put simply, .when the system 100 is in external host mode, only the
CHIP ERASE operation, to completely erase the program memory 102,
can be used to access the lockable flash memory locations. That is,
the CHIP ERASE function operates regardless of the value, of the
security byte. As discussed above, in response to the CHIP ERASE
function being executed, the security byte is set back to the
default value of FFh. Then, because security is disabled, the
external host may freely program (or otherwise access) the program
memory 102, via the SFDT "mailbox register" 204. (The WDTD and WDTC
registers shown in FIG. 2 are for controlling a watchdog timer and
are not relevant to the present disclosure.)
If the security byte at location FFFFh has the value F5h, only the
upper program memory block 102b is locked, and the lower program
memory block 102a is not locked.
During concurrent programming mode, with the security byte at
location FFFFh set to 05h, the lower program memory block 102a may
be programmed (i.e., sector or block erase, write and verify
operations) by program code executing from the upper program memory
block 102b, but not by any program code executing from the external
program code storage even though both program memory blocks 102a
and 102b are security locked for any other access, such as External
Mode Host Access. This security mechanism is known as "soft lock".
Contrary to the "hard lock", when the security byte at location
FFFFh is set to 55h (where both the upper 102b and lower 102a
memory blocks are not accessible for any programming operation),
the "soft lock" security mechanism allows the system to use a
secure program code to perform in-system and in-field flash memory
concurrent programming of the lower program memory block 102a under
a predetermined secure environment. Table 1 further illustrates
this security lock feature.
More details of the program memory addressable space are now
discussed with reference to FIGS. 3A to 3C, particularly relative
to how the program memory organization is adaptable to address
safety and security concerns. More specifically, FIGS. 3A to 3C
show three program memory organization and assignment options of
the microcontroller system 100.
As discussed above, the program (flash) memory 102 of the
microcontroller system 100 includes two blocks, lower program
memory block 102a and upper program memory block 102b.
In one embodiment, the lower program memory block 102a has 32
Kbytes and occupies the address space 0000h to 7FFFh. The 32 Kbytes
of the lower program memory block 102a are organized as 512 rows
(256 of 128-byte sectors per page, 9 X-address lines) and 512
columns (64 bytes per row, 6 Y-address lines). The upper program
memory block 102b has 4 Kbytes, and occupies the address space
F000h to FFFFh. The 4 Kbytes of the upper program memory block 102b
are organized as 128 rows (64 of 64-byte sectors per page, 7
X-address lines) and 256 columns (32 bytes per row, 5 Y-address
lines).
As can be seen from FIGS. 3A to 3C, the address space 8000h to
EFFFh is always reserved for external memory (not shown), which may
be, for example, memory of a development system or hardware
programmer.
Referring now specifically to FIG. 3B, in "normal mode", when
instructions are being executed by the MCU processor core 103, the
upper program memory block 102b is "hidden for code fetching". This
is so even when internal code execution is enabled (#EA=1; see
Table 1) such that code may be executed from the internal program
memory 102. By "hidden for code fetching", it is meant that program
instructions in the block "hidden for code fetching" cannot be
fetched and executed from locations of the hidden block.
As shown in FIG. 3A, to make the upper program memory 102b visible
for code fetching, so that the concurrent programming operation can
be carried out by executing program instructions from the upper
program memory 102b, the system 100 must be in internal mode (i.e.,
#EA=1), and the user must set a concurrent programming field in the
SuperFlash.RTM. configuration register SFCF 202. In one embodiment,
the concurrent programming field is the most significant bit of the
SuperFlash.RTM. configuration register SFCF 202 (FIG. 2).
As for the visibility of the lower program memory block 102a, while
internal code execution is enabled (i.e., #EA=1), the lower program
memory block 102a is always visible for code fetching. This can be
seen from FIGS. 3A and 3B. If the external enable is asserted at
hardware reset of the system 100, program execution starts from the
lower program memory block 102a.
Finally, as can be seen from FIG. 3C, while internal code execution
is not enabled (i.e., #EA=0), both lower program memory block 102a
and upper program memory block 102b are hidden for code
fetching.
By having circuitry to so allocate the program memory, the security
of the program memory is enhanced. Furthermore, in combination with
the security lock circuitry, the security of the program is further
enhanced.
* * * * *