U.S. patent number 6,426,267 [Application Number 09/948,407] was granted by the patent office on 2002-07-30 for method for fabricating high-q inductance device in monolithic technology.
This patent grant is currently assigned to Winbond Electronics Corp.. Invention is credited to Ping Liou.
United States Patent |
6,426,267 |
Liou |
July 30, 2002 |
Method for fabricating high-Q inductance device in monolithic
technology
Abstract
The present invention provides a method for fabricating a high-Q
inductance device. First, a first dielectric layer is formed on a
semiconductor substrate. A spiral conducting line is formed above
the first dielectric layer. Then, a passivation layer is formed
above the spiral conducting line and the first dielectric layer,
such that a spiral air gap is formed in the passivation layer
within the space around the spiral conducting line. Finally, the
inductance device is immersed in an acid solution so as to increase
the size of the spiral air gap. When an additional dielectric layer
and spiral conducting line are formed between the first dielectric
layer and the passivation layer, the air gap can be formed not only
in the passivation layer, but also in the additional dielectric
layer. Therefore, the inductance device of the present invention
can have a plurality of air gaps that are formed in the passivation
layer or formed in both of the passivation layer and the dielectric
layers. By means of the at least one spiral conducting line, the
resistance of the inductance device can be decreased. The parasitic
capacitance can be decreased by means of the spiral air gap with a
low dielectric constant. Moreover, the size of the spiral air gap
can be increased by means of immersing the inductance device in the
acid solution. Therefore, the Q value of the inductance device of
the present invention can be effectively increased.
Inventors: |
Liou; Ping (Hsinchu,
TW) |
Assignee: |
Winbond Electronics Corp.
(Hsinchu, TW)
|
Family
ID: |
26666563 |
Appl.
No.: |
09/948,407 |
Filed: |
September 6, 2001 |
Related U.S. Patent Documents
|
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
|
303048 |
Apr 30, 1999 |
|
|
|
|
Foreign Application Priority Data
|
|
|
|
|
Jun 19, 1998 [TW] |
|
|
87109918 A |
|
Current U.S.
Class: |
438/319;
257/E21.022; 257/E27.046; 438/329; 438/421 |
Current CPC
Class: |
H01F
41/041 (20130101); H01L 27/08 (20130101); H01L
28/10 (20130101); H01F 2017/0046 (20130101) |
Current International
Class: |
H01F
41/04 (20060101); H01L 21/02 (20060101); H01L
27/08 (20060101); H01F 17/00 (20060101); H01L
021/331 (); H01L 021/822 () |
Field of
Search: |
;257/522,528,531,532,533,774 ;438/319,329,411,421,619 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Chaudhuri; Olik
Assistant Examiner: Pham; Hoai
Attorney, Agent or Firm: Ladas & Parry
Parent Case Text
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part of application Ser. No.
09/303,048 filed Apr. 30, 1999, now pending.
Claims
What is claimed is:
1. A method for fabricating an inductance device, comprising the
steps of: providing a semiconductor substrate; forming a first
dielectric layer on the semiconductor substrate; forming a spiral
conducting line above the first dielectric layer; forming a
passivation layer above the spiral conducting line and the first
dielectric layer to obtain an inductance device, such that a spiral
air gap is formed in the passivation layer within the space around
the spiral conducting line; and immersing the inductance device
obtained in an acid solution so as to increase the size of the
spiral air gap, wherein the acid solution is selected from the
group consisting of HF solution, BOE (buffered oxide etchant)
solution, buffered HF solution, hot H.sub.3 PO.sub.4 solution, and
mixtures thereof.
2. The method as claimed in claim 1, wherein the passivation layer
is an oxide layer or a nitride layer.
3. The method as claimed in claim 2, wherein the passivation layer
is an oxide layer, and the acid solution is selected from the group
consisting of HF solution and BOE solution.
4. The method as claimed in claim 2, wherein the passivation layer
is a nitride layer, and the acid solution is selected from the
group consisting of buffered HF solution and hot H.sub.3 PO.sub.4
solution.
5. The method as claimed in claim 1, wherein the space around the
spiral conducting line has a height/width ratio larger than 2.
6. A method for fabricating an inductance device, comprising the
steps of: providing a semiconductor substrate; forming a first
dielectric layer on the semiconductor substrate; forming a first
spiral conducting line above the first dielectric layer; forming a
third dielectric layer above the first spiral conducting line and
the first dielectric layer, such that a first spiral air gap is
formed in the third dielectric layer within the space around the
first spiral conducting line; forming a first spiral via within the
third dielectric layer above the first spiral conducting line;
forming a second spiral conducting line on the first spiral via;
forming a fourth dielectric layer on the second spiral conducting
line and the third dielectric layer, such that a second spiral air
gap is formed in the fourth dielectric layer within the space
around the second spiral conducting line; forming a second spiral
via within the fourth dielectric layer above the second spiral
conducting line; forming a third spiral conducting line on the
second spiral via; forming a passivation layer on the third spiral
conducting line and the fourth dielectric layer to obtain an
inductance device, such that a third spiral air gap is formed in
the passivation layer within the space around the third spiral
conducting line; and immersing the inductance device obtained in an
acid solution, so as to increase the sizes of the first, the
second, and the third spiral air gaps, wherein the acid solution is
selected from the group consisting of HF solution, BOE solution,
buffered HF solution, hot H.sub.3 PO.sub.4 solution, and mixtures
thereof.
7. The method as claimed in claim 6, wherein the dielectric layers
and the passivation layer are oxide layers or nitride layers.
8. The method as claimed in claim 7, wherein the dielectric layers
and the passivation layer are oxide layers, and the acid solution
is selected from the group consisting of HF solution and BOE
solution.
9. The method as claimed in claim 7, wherein the dielectric layers
and the passivation layer are nitride layers, and the acid solution
is selected from the group consisting of buffered HF solution and
hot H.sub.3 PO.sub.4 solution.
10. The method as claimed in claim 6, wherein the space around each
of the spiral conducting line has a height/width ratio larger than
2.
11. A method for fabricating an inductance device, comprising the
steps of: providing a semiconductor substrate; forming a first
dielectric layer on the semiconductor substrate; forming a spiral
conducting line above the first dielectric layer; forming a
dielectric layer above the spiral conducting line, such that a
spiral air gap is formed in the dielectric layer within the space
around the spiral conducting line; forming a spiral via within the
dielectric layer above the spiral conducting line; forming a spiral
conducting line on the spiral via; repeating steps of forming a
dielectric layer above the spiral conducting line, forming a spiral
via within the dielectric layer above the spiral conducting line,
and forming a spiral conducting line on the spiral via for N times,
wherein N is an integer equal to or larger than 0; forming a
passivation layer on the last spiral conducting line and the last
dielectric layer to obtain an inductance device, such that a spiral
air gap is formed in the passivation layer within the space around
the last spiral conducting line; and immersing the inductance
device obtained in an acid solution, so as to increase the sizes of
the spiral air gaps.
12. The method as claimed in claim 11, further comprising, after
the step of forming a first dielectric layer on the semiconductor
substrate and before the step of forming a spiral conducting line
above the first dielectric layer, the following steps of: forming a
conducting layer on the first dielectric layer; forming a second
dielectric layer on the conducting layer and the first dielectric
layer; and forming a via within the second dielectric layer above
the conducting layer, wherein the via is connected to one end of
the first spiral conducting line.
13. The method as claimed in claim 11, wherein the acid solution is
selected from the group consisting of HF solution, BOE solution,
buffered HF solution, hot H.sub.3 PO.sub.4 solution, and mixtures
thereof.
14. The method as claimed in claim 13, wherein the dielectric
layers and the passivation layer are oxide layers or nitride
layers.
15. The method as claimed in claim 14, wherein the dielectric
layers and the passivation layer are oxide layers, and the acid
solution is selected from the group consisting of HF solution and
BOE solution.
16. The method as claimed in claim 14, wherein the dielectric
layers and the passivation layer are nitride layers, and the acid
solution is selected from the group consisting of buffered HF
solution and hot H.sub.3 PO.sub.4 solution.
17. The method as claimed in claim 11, wherein the space around
each of the spiral conducting line has a height/width ratio larger
than 2.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating
semiconductor devices, and more particularly to a monolithic high-Q
inductance device and a process for fabricating the same.
2. Description of the Prior Art
Many digital and analog circuits have been successfully
mass-produced by using VLSI (very large scale integrated)
technology. However, radio frequency (RF) circuits, such as those
used in cellular telephones, wireless modems, and other types of
communication equipment, have not yet been completely implemented
with integrated circuits (ICs).
A lump-sum equivalent circuit of a conventional inductance device
is shown in FIG. 1, in which L indicates the inductance, R.sub.s
the series resistance, and C.sub.d the parasitic capacitance.
Quality factor (hereinafter, Q value) refers to the quality of an
inductance device. It is known that the inductance generated by an
ideal conducting coil has an infinitely large Q value, and thus
there is no energy loss. However, to date, it has not been possible
to obtain an inductance device having an infinitely large Q value.
Many attempts have been made to decrease the energy loss of the
inductance in order to manufacture an inductance device having high
Q-value.
A conventional inductance device, as shown in FIG. 2, has an
inductor formed by a plurality of spiral conducting lines so as to
decrease the serial resistance. The numerals in FIG. 2 indicate
elements as follows: 10.about.the substrate, 11.about.the first
dielectric layer, 12.about.the conducting layer, 13.about.the
second dielectric layer, 15.about.the via, 16.about.the first
spiral conducting line, 17.about.the third dielectric layer,
20.about.the first spiral via, 21.about.the second spiral
conducting line, 22.about.the fourth dielectric layer, 25.about.the
second spiral via, 26.about.the third spiral conducting line, and
27.about.the passivation layer. However, in order to have a higher
inductance, the spiral conducting line should have a larger number
of winding. The wide spiral conducting lines result in a larger
surface area and cause large parasitic capacitance, which in turn
results in a decreased Q-value.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to solve the
above-mentioned problems and to provide an inductance device with
high-Q and to provide a method for fabricating the same.
The above objects of the present invention can be achieved by
providing a method for fabricating a high-Q inductance device. A
first dielectric layer is formed on a semiconductor substrate. A
spiral conducting line is formed above the first dielectric layer.
A passivation layer is formed above the spiral conducting line and
the first dielectric layer, such that a spiral air gap is formed in
the passivation layer within the space around the spiral conducting
line. Finally, the inductance device obtained is immersed in an
acid solution so as to increase the size of the spiral air gap.
When an additional dielectric layer and spiral conducting line are
formed between the first dielectric layer and the passivation
layer, the air gap can be formed not only in the passivation layer,
but also in the additional dielectric layer. The acid solution can
be HF solution, BOE (buffered oxide etchant) solution, buffered HF
solution, hot H.sub.3 PO.sub.4 solution, or mixtures thereof.
To decrease the serial resistance further, the inductance device of
the present invention can also include at least two spiral
conducting lines rather than only one spiral conducting line. The
method for fabricating an inductance device having at least two
spiral conducting lines includes the steps of: providing a
semiconductor substrate; forming a first dielectric layer on the
semiconductor substrate; forming a spiral conducting line above the
first dielectric layer; forming a dielectric layer above the spiral
conducting line, such that a spiral air gap is formed in the
dielectric layer within the space around the spiral conducting
line; forming a spiral via within the dielectric layer above the
spiral conducting line; forming a spiral conducting line on the
spiral via; repeating steps of forming a dielectric layer above the
spiral conducting line, forming a spiral via within the dielectric
layer above the spiral conducting line, and forming a spiral
conducting line on the spiral via for N times, wherein N is an
integer equal to or larger than 0; forming a passivation layer on
the last spiral conducting line and the last dielectric layer to
obtain an inductance device, such that a spiral air gap is formed
in the passivation layer within the space around the last spiral
conducting line; and immersing the inductance device obtained in an
acid solution, so as to increase the sizes of the spiral air
gaps.
For example, when the inductance device has three spiral conducting
lines, the method for fabricating the inductance device includes
the following procedures. First, a first dielectric layer is formed
on a semiconductor substrate. Then, a first spiral conducting line
is formed above the first dielectric layer. Then, a third
dielectric layer is formed above the first spiral conducting line
and the first dielectric layer, such that a first spiral air gap is
formed in the third dielectric layer within the space around the
first spiral conducting line. A first spiral via is formed within
the third dielectric layer above the first spiral conducting line.
Subsequently, a second spiral conducting line is formed on the
first spiral via, and a fourth dielectric layer on the second
spiral conducting line and the third dielectric layer, such that a
second spiral air gap is formed in the fourth dielectric layer
within the space around the second spiral conducting line. A second
spiral via is formed within the fourth dielectric layer above the
second spiral conducting line, and a third spiral conducting line
is formed on the second spiral via. A passivation layer is formed
on the third spiral conducting line and the fourth dielectric
layer, such that a third spiral air gap is formed in the
passivation layer within the space around the third spiral
conducting line. Finally, the inductance obtained is immersed in an
acid solution, so as to increase the sizes of the first, the
second, and the third spiral air gaps. The acid solution can be HF
solution, BOE solution, buffered HF solution, hot H.sub.3 PO.sub.4
solution, or mixtures thereof.
According to the method for fabricating the high-Q inductance
device of the present invention, a spiral air gap is formed in the
passivation layer or both in the passivation layer and the
dielectric layer within the space around the spiral conducting
line. Since air has a very low dielectric constant, the parasitic
capacitance can be decreased. Therefore, the Q value of the
inductance device of the present invention can be effectively
increased. In addition, the size of the spiral air gap is increased
by means of immersing the inductance device in an acid solution.
Thus, the parasitic capacitance can be further decreased. In
addition, by means of the at least one spiral conducting line, the
resistance of the inductance device can be decreased.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the
detailed description given hereinbelow and the accompanying
drawings, given by way of illustration only and thus not intended
to be limitative of the present invention.
FIG. 1 shows the lump-sum equivalent circuit of a conventional
inductance device.
FIG. 2 is a cross-sectional view of a conventional inductance
device.
FIGS. 3A.about.3O are cross-sectional views illustrating the
process flow of fabricating the high-Q inductance device according
to the present invention.
FIG. 4 is the top view of FIG. 3O.
FIG. 5 is the perspective view of FIG. 3O.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Refer to FIGS. 3A to 3O, illustrating the process flow of forming a
high-Q inductance device according to the present invention. In the
figures, a semiconductor substrate 10 is a silicon substrate on
which a plurality semiconductor devices such as bipolar junction
transistors or field effect transistors have been formed but are
not shown. Referring to FIG. 3A, a first dielectric layer 11, such
as a first oxide layer, is first formed over the whole surface of
the semiconductor substrate 10. The first dielectric layer 11 may
have a thickness as thick as possible. The rest of the
manufacturing steps are as follows:
Step 1
Referring to FIG. 3B, a conducting layer 12, such as an aluminum
layer, is formed on the first dielectric layer 11 by metal
sputtering, photolithography, and plasma dry etching.
Step 2
Referring to FIG. 3C, a second dielectric layer 13, such as a
second oxide layer, is formed on the conducting layer 12 and the
first dielectric layer 11 by chemical vapor deposition and chemical
mechanical polishing (CMP).
Step 3
Referring to FIG. 3D, a via hole 14 is formed within the second
dielectric layer 13 above the conducting layer 12 by
photolithography and plasma dry etching, such that the via hole 14
is connected to the conducting layer 12.
Step 4
Referring to FIG. 3E, a conducting via 15, such as a tungsten via,
is formed in the via hole 14 by chemical vapor deposition and
etching back or CMP.
Step 5
Referring to FIG. 3F, a first spiral conducting line 16, such as a
first spiral aluminum layer, is formed on the via 15 and the second
dielectric layer 13 by metal sputtering, photolithography, and
plasma dry etching. The formation of the first spiral conducting
line 16 meets the requirements that one end 16' of the first spiral
conducting line 16 is connected to the via 15, and the space around
the first spiral conducting line 16 has a height/width ratio larger
than 2.
Step 6
Referring to FIG. 3G, a third dielectric layer 17, such as a third
oxide layer, is formed on the first spiral conducting line 16 and
the second dielectric layer 13 by chemical vapor deposition and
CMP. Since the space around the first spiral conducting line 16 has
a height/width ratio larger than 2, a first spiral air gap 18 will
be formed in the third dielectric layer 17 within the space around
the first spiral conducting line 16.
Step 7
Referring to FIG. 3H, a first spiral via hole 19 is formed within
the third dielectric layer 17 directly above the first spiral
conducting line 16 by photolithography and plasma dry etching.
Step 8
Referring to FIG. 3I, a first spiral via 20, such as a first spiral
tungsten via, is formed in the first spiral via hole 19 by chemical
vapor deposition and etching back or CMP.
Step 9
Referring to FIG. 3J, a second spiral conducting line 21, such as a
second spiral aluminum layer, is formed on the first spiral via 20
by metal sputtering, photolithography, and plasma dry etching. The
formation of the second spiral conducting line 21 also meets the
requirement that the space around the second spiral conducting line
21 has a height/width ratio larger than 2.
Step 10
Referring to FIG. 3K, a fourth dielectric layer 22, such as a
fourth oxide layer, is formed on the second spiral conducting line
21 and the third dielectric layer 17 by chemical vapor deposition
and CMP. At the same time, a second spiral air gap 23 will be
formed in the fourth dielectric layer 22 within the space around
the second spiral conducting line 21.
Step 11
Referring to FIG. 3L, a second spiral via hole 24 is formed within
the fourth dielectric layer 22 directly above the second spiral
conducting line 21 by photolithography and plasma dry etching.
Step 12
Referring to FIG. 3M, a second spiral via 25, such as a second
spiral tungsten via, is formed in the second spiral via hole 24 by
chemical vapor deposition and etching back or CMP.
Step 13
Referring to FIG. 3N, a third spiral conducting line 26, such as a
third spiral aluminum layer, is formed on the second spiral via 25
by metal sputtering, photolithography, and plasma dry etching. The
formation of the third spiral conducting line 26 also meets the
requirement that the space around the third spiral conducting line
26 has a height/width ratio larger than 2.
Step 14
Referring to FIG. 3O, a passivation layer 27, such as an oxide
layer, is formed on the third spiral conducting line 26 and the
fourth dielectric layer 22 by chemical vapor deposition. At the
same time, a third spiral air gap 28 will be formed in the
passivation layer 27 within the space around the third spiral
conducting line 26. Subsequently, the obtained inductance device
shown in FIG. 3O is immersed in an acid solution so as to increase
the sizes of the first spiral air gap 18, the second spiral air gap
23, and the third spiral air gap 28.
The acid solution suitable for use in the present invention can be
HF solution, BOE (buffered oxide etchant) solution, buffered HF
solution, hot H.sub.3 PO.sub.4 solution, or mixtures thereof.
The passivation layer and the dielectric layer in which a spiral
gap is formed can be an oxide layer or a nitride layer. When the
passivation layer and the dielectric layer are oxide layers, the
acid solution suitable for use to increase the size of the spiral
air gap is preferably HF solution or BOE solution. When the
passivation layer and the dielectric layer are nitride layers, the
acid solution suitable for use to increase the size of the spiral
air gap is preferably buffered HF solution or hot H.sub.3 PO.sub.4
solution.
In addition, FIG. 4 shows the top view of the inductance device
shown in FIG. 3O, and FIG. 3O is a cross-sectional view taken along
the line III 0--III 0 of FIG. 4. FIG. 5 shows the perspective view
of FIG. 3O.
According to the method for fabricating the high-Q inductance
device of the present invention, since the inductance is generated
by at least one spiral conducting line, the serial resistance can
be decreased. Moreover, by means of the requirement that the space
around the spiral conducting line has a height/width ratio larger
than 2, when a passivation layer or dielectric layer is formed on
the spiral conducting line, a spiral air gap will be formed in the
passivation layer or dielectric layer within the space around the
spiral conducting line simultaneously. Since air has a very low
dielectric constant, the parasitic capacitance can be decreased,
and a high-Q inductance device can be fabricated. In addition, the
size of the spiral air gap can be increased by means of immersing
the inductance device in an acid solution. Thus, the parasitic
capacitance can be further decreased.
The foregoing description of the preferred embodiments of the
present invention has been provided for the purpose of illustration
and description. It is not intended to be exhaustive or to limit
the invention to the precise forms disclosed. Many modifications
and variations will be apparent to practitioners skilled in the
art. The embodiments were chosen and described to best explain the
principles of the invention and its practical application, thereby
enabling others skilled in the art to under stand the invention to
practice various other embodiments and make various modifications
suited to the particular use contemplated. It is intended that the
scope of the invention be defined by the following claims and their
equivalents.
* * * * *