U.S. patent number 6,211,705 [Application Number 09/145,732] was granted by the patent office on 2001-04-03 for timed bistable circuit for high frequency applications.
This patent grant is currently assigned to SGS-Thomson Microelectronics S.r.l.. Invention is credited to Melchiorre Bruccoleri, Paolo Cusinato.
United States Patent |
6,211,705 |
Bruccoleri , et al. |
April 3, 2001 |
Timed bistable circuit for high frequency applications
Abstract
A timed bistable circuit is described which includes two
inverters each having its input connected to the output of the
other, an output of the circuit via a "buffer" and an input of the
circuit via a controlled electronic switch. The supply terminals of
the inverters are connected to the supply terminals of the circuit
via another two controlled switches. A clock generator provides
timing signals to control both the input switches to open or close
and to control the supply switches to close or open when the input
switches are open or closed respectively. To obtain a latch usable
in a comparator at a high comparison frequency the offset referred
to the input is reduced and made independent of the frequency by
arranging two further electronic switches between the supply
terminals of the inverters and the supply terminals which are
controlled by a timing signal in such a way as to close with a
predetermined delay with respect to the closure of the input
switches and to open when input switches open.
Inventors: |
Bruccoleri; Melchiorre (Genoa,
IT), Cusinato; Paolo (Genoa, IT) |
Assignee: |
SGS-Thomson Microelectronics
S.r.l. (Agrate Brianza, IT)
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Family
ID: |
8222062 |
Appl.
No.: |
09/145,732 |
Filed: |
September 2, 1998 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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755466 |
Nov 22, 1996 |
5808488 |
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Foreign Application Priority Data
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Nov 23, 1995 [EP] |
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95830487 |
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Current U.S.
Class: |
327/57; 327/208;
327/210; 327/211 |
Current CPC
Class: |
H03K
3/356156 (20130101) |
Current International
Class: |
H03K
3/00 (20060101); H03K 3/356 (20060101); H03K
005/153 () |
Field of
Search: |
;327/199,200,201,208-215,52-57,97,218 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
Other References
European Search Report from European Patent Application No.
95830487.5 filed Nov. 23, 1995. .
IBM Technical Disclosure Bulletin, vol. 28, No. 4, Sep. 1, 1985,
New York, US, pp 1716-1718, "Latching Node Clock Design in Half VDD
Bit Line CMOS Sense Amplifier"..
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Primary Examiner: Lam; Tuan T.
Attorney, Agent or Firm: Wolf, Greenfield & Sacks, P.C.
Morris; James H. Galanthay; Theodore E.
Parent Case Text
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No.
08/755,466, filed Nov. 22, 1996, entitled TIMED BISTABLE CIRCUIT
FOR HIGH FREQUENCY APPLICATIONS now U.S. Pat. No. 5,808,488, which
prior application is incorporated herein by reference.
Claims
What is claimed is:
1. A method for latching data in an integrated circuit having first
and second input inverters, the method comprising:
receiving, at the first and second inverters respectively during a
first sampling phase, a first and second signal input, wherein
first and second input capacitances associated with the first and
second inverters, respectively, are charged;
eliminating, during a second sampling phase, charge stored by a
parasitic capacitance associated with the integrated circuit;
and
comparing, during an evaluation phase, the first and second signal
inputs.
2. The method according to claim 1, further comprising applying,
during the first sampling phase, first and second clock signals,
respectively, to the first and second inverters.
3. The method according to claim 2, wherein the step of eliminating
includes eliminating charge stored by applying the first and second
clock signals.
4. The method according to claim 1, further comprising isolating,
during the evaluation phase, the first and second signal inputs
from the first and second inverters, respectively.
5. The method according to claim 3, wherein the step of eliminating
includes discharging the charge stored by the parasitic capacitance
to a ground terminal associated with the integrated circuit.
6. The method according to claim 5, wherein the step of discharging
is controlled by operating a first and second switch, each
connected to a control terminal of the first and second inverters,
respectively.
7. The method according to claim 1, wherein the charge stored by
the parasitic capacitance is substantially discharged prior to the
evaluation phase.
8. A timed bistable circuit comprising:
two supply terminals;
a first and a second signal input;
a first and a second signal output; a first and a second inverter
each having its input connected to the output of the other
inverter, to the first and the second signal output respectively
via a first and a second separator circuit respectively and to the
first and second signal input respectively via a first and a second
controlled electronic switch respectively and each having two
supply terminals connected to the circuit supply terminals via a
first controlled switching device;
a timer device operable to control the first and the second
controlled electronic switches to open or close simultaneously and
to control the first controlled switching device to close or open
when the first and second electronic switches are both open or both
closed respectively,
a second controlled switching device operable to connect the two
supply terminals of the inverters respectively to the first and to
the second circuit supply terminal, and
wherein the timer is operable to control the second controlled
switching device to close with a predetermined delay with respect
to the closure of the first and second controlled electronic
switches and to open at a predetermined instant not later than the
opening of the first and second controlled electronic switches.
9. The timed bistable circuit according to claim 8, in which the
predetermined instant coincides with the opening of the first and
second controlled electronic switches.
10. The timed bistable circuit according to claim 8, in which the
first controlled electronic switch includes third and fourth
controlled switching devices and in which the second controlled
switching device includes fifth and sixth controlled electronic
switches.
11. The timed bistable circuit according to claim 10, in which the
first to sixth controlled electronic switches each comprise
transfer gates.
12. The comparator including a timed bistable circuit according to
claim 8, a differential amplifier connected to the inputs of the
timed bistable circuit and a flip-flop connected to the outputs of
the timed bistable circuit, the inputs of the differential
amplifier being the inputs of the comparator and one of the outputs
of the flip-flop being the output of the comparator.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timed bistable circuit (latch),
advantageously usable in a comparator circuit having a high
frequency response.
2. Discussion of the Related Art
As is known, the most typical function of a comparator circuit is
that of comparing between voltages applied to its inverting and
non-inverting input terminals. The output of the comparator is
either a voltage at logic level 1 when the voltage on the
non-inverting input is greater than that on the inverting input or
a voltage at logic level 0 when the voltage on the non-inverting
input is less than that on the inverting input.
In order to obtain high comparison speeds, where high frequency
response characteristics are required, comparators are used which
incorporate timed bistable circuits (latches) that have a high
commutation speed due to the positive feedback on which their
operation is based.
A typical comparator of this type is constituted, as shown in FIG.
1, by a differential preamplifier stage DIF, a latch LAT timed by a
clock circuit CK and an output stage FF constituted by a
"master-slave" RS-type flip-flop. The inputs Vin and Vref of the
differential stage are the inputs of the comparator and one of the
outputs of the flip-flop, Q or Q, is the output of the comparator.
The differential preamplifier stage DIF must have a gain such that
the smallest difference Vin-Vref which must be sensed is amplified
by a factor sufficient to obtain at the input to the latch a signal
with an amplitude higher than the offset referred to the input. As
is known, the input offset voltage of a differential circuit is the
voltage which must be applied to the inputs to have a voltage
difference equal to zero between the outputs of the circuit and is
a quantity which depends on asymmetry and unbalancing of the
components of the circuit. For the comparator of FIG. 1 the offset
voltage referred to the input is expressed by ##EQU1##
where V.sub.OSDIF is the offset of the differential stage DIF,
V.sub.OSL is the offset of the latch LAT and A.sub.DIF is the gain
of the differential preamplifier stage DIF.
In order to obtain a comparator having output levels which are as
sharp, stable and in the case of integrated circuit structures, as
reproducible as possible from one example to another it is
necessary to minimize the input offset voltage. Moreover, in order
to obtain comparators which have the most uniform possible response
even at high comparison frequencies, it is necessary that the
offset voltage does not depend on frequency. In practice, however,
known latches have an offset voltage V.sub.OSL which increases
considerably with an increase in the frequency at which they are
operated. Consequently, the increase in offset voltage limits the
response of the comparator at high frequencies.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a timed bistable
circuit (latch) having a reduced offset which is substantially
independent of the timing frequency.
These and other objects are achieved by a timed bistable circuit
having
two supply terminals;
a first and a second signal input;
a first and a second signal output; a first and a second inverter
each having its input connected to the output of the other
inverter, to the first and the second signal output respectively
via a first and a second separator circuit respectively and to the
first and second signal input respectively via a first and a second
controlled electronic switch respectively and each having two
supply terminals connected to the circuit supply terminals via
first controlled switch means;
timing means operable to control the first and the second
electronic switch to open or close simultaneously and to control
the first controlled switch means to close or open when the first
and second electronic switches are both open or both closed
respectively,
second controlled switch means operable to connect the two supply
terminals of the inverters respectively to the first and to the
second circuit supply terminal, and
wherein the timing means are operable to control the second switch
means to close with a predetermined delay with respect to the
closure of the first and second electronic switches and to open at
a predetermined instant not later than the opening of the first and
second electronic switches.
According to another embodiment of the invention, the predetermined
instant coincides with the opening of the first and second
electronic switches.
According to another embodiment of the invention, the first
controlled switch means include third and fourth controlled
electronic switches and the second controlled switch means include
fifth and sixth controlled electronic switches.
According to another embodiment of the invention, the controlled
electronic switches include transfer gates.
According to another embodiment of the invention, a differential
amplifier is connected to the inputs of the timed bistable circuit
and a flip flop is connected to the outputs of the timed bistable
circuit, the inputs of the differential amplifier being the inputs
of the comparator and one of the inputs of the flip flop being the
output of the comparator.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be better understood from the following detailed
description of an embodiment given in relation to the attached
drawings, in which:
FIG. 1 is a block diagram of a generic comparator with a latch;
FIG. 2 is a block diagram of a known latch;
FIG. 3 is a block diagram of a latch according to the
invention;
FIG. 4 is a circuit diagram of a latch according to the invention;
and
FIG. 5 is a timing diagram of two timing signals useful to
illustrate the operation of the latch according to the
invention.
DETAILED DESCRIPTION
The known circuit in FIG. 2 represents a latch usable in a
comparator according to FIG. 1. It includes two inverters INV1 and
INV2 connected together in positive feedback, that is to say each
with its output connected to the input of the other.
The input of the inverter INV1 is connected, at a node Z+, not only
to the output of the inverter INV2, but also to a first signal
input of the circuit, indicated I+, via a first controlled
electronic switch S1. Similarly, the input of the inverter INV2 is
connected, at a node Z- not only to the output of the inverter
INV1, but also to a second signal input of the circuit, indicated
I- via a second controlled electronic switch S2.
The outputs of the inverters INV1 and INV2 connected to the inputs
Z- and Z+ are also each connected to the input of a respective
separator circuit or buffer, respectively indicated BF1 and BF2,
the outputs U+ and U- of which respectively constitute first and
second signal outputs from the circuit. The supply terminals of the
two inverters are joined at two nodes A and B and are respectively
connected to the positive voltage supply terminal Vdd via a third
controlled electronic switch S3, and to ground GND via a fourth
controlled electronic switch S4. The buffers BF1 and BF2 have
respective supply terminals connected to the supply voltage Vdd and
to ground. The control terminals of the controlled electronic
switches are connected to a timing signal generator or clock
indicated CK.
In FIG. 2 there are also shown, in broken lines, two capacitors
C.sub.IN which represent the input capacitances of the two
inverters and two capacitors C.sub.A and C.sub.B which represent
the parasitic capacitances associated with the two nodes A and
B.
A circuit similar to that described above is illustrated for
example in the article published in the IEEE Journal of solid-state
circuits, Vol. 27, No. 12, December 1992, page 1916-1926.
The operation of the circuit of FIG. 2 takes place in two phases, a
sampling phase and an evaluation phase.
During the sampling phase, the switches S1 and S2 are closed and
the switches S3 and S4 are opened by the effect of respective
control signals V.sub.ck and V.sub.ck generated by the clock CK,
applied to their control terminals. In these conditions, the two
inverters are not supplied, whilst their inputs are connected to
the input terminals I+ and I- of the circuit to which are applied
two voltages V.sub.IN+ and V.sub.IN- to be evaluated, which can
differ by a small amount from one another (for example 1mV). These
voltages charge the input capacitances C.sub.IN of the two
inverters.
In the subsequent evaluation phase, the switches S1 and S2 are open
and the switches S3 and S4 are closed. In these conditions the
inverters are supplied and therefore the positive feedback between
them is active, the latch is insensitive to possible variations in
the input voltages and at the outputs U+ and U- appear two voltages
Vout+ and Vout- which, by the effect of the regenerative action of
the positive feedback, differ from one another by an amount even up
to several hundreds of times greater than the differential input
voltage. These voltages are available at the outputs for the whole
of the duration of the clock signal V.sub.ck.
It has been ascertained that the precision with which the
comparator performs the comparison during the evaluation phase
depends principally on the latch input offset voltage at the end of
the sampling phase. It has also been ascertained that this offset
voltage increases with an increase in the switching frequency of
the latch so that the use of such latches in a comparator is
limited to applications in which the comparison frequency does not
exceed a certain value (for example about 40 MHz). The inventors
have determined that this dependence of the offset on the frequency
is attributed to a positive feedback also being set up during the
sampling phase because of the parasitic capacitance associated with
the nodes A and B of the circuit, indicated C.sub.A and C.sub.B in
FIG. 2, and therefore have modified the known circuit of FIG. 2 in
the manner shown in FIG. 3.
As is seen, the latch shown in FIG. 3 where components which are
the same as those of FIG. 2 are indicated with the same reference
symbols, has a fifth and a sixth controlled electronic switch,
indicated S5 and S6, respectively connected between the node A and
ground and between the node B and the supply terminal Vdd. The
control terminals of the two switches are connected to the timing
generator, indicated CK'. The timing generator is able to generate,
as well as the clock signals V.sub.ck and V.sub.ck as in the case
of the circuit of FIG. 2, a clock signal V.sub.ckd, for controlling
the switches S5 and S6 which is different from the signal V.sub.ck
only because its falling edge is delayed by a predetermined time
with respect to the falling edge of the signal V.sub.ck. The
operation of the circuit in a clock period T.sub.ck is
characterized by the following phases:
first sampling phase: this phase, indicated .PHI..sub.1 in FIG. 5
is similar to the sampling phase in the known circuit in that the
switches S1 and S2 are closed and the switches S3 and S4 are open
by the effect of the clock signals V.sub.ck and V .sub.ck applied
to their control terminals and the signals V.sub.IN- and V.sub.IN+
charge the input capacitances C.sub.IN of the latch; during this
phase the switches S5 and S6 are open;
second sampling phase: during this phase, indicated .PHI..sub.2 in
FIG. 5, the switches S1 , S2, S3 and S4 stay in the same conditions
as in the first phase, whilst the switches S5 and S6 are closed;
this allows the parasitic capacitances C.sub.A and C.sub.B to be
discharged thus preventing the initiation of a positive feedback
during the sampling phase;
evaluation phase: this phase, indicated .PHI..sub.3 in FIG. 5, is
similar to the evaluation phase in the known circuit; note that the
switches S5 and S6 are controlled to open at the beginning of this
phase, that is to say when the switches S1 and S2 open and the
switches S3 and S4 close, but could also be opened at a
predetermined instant before the commencement of the phase
.PHI..sub.3, naturally provided that it is after the discharge of
the capacitances C.sub.A and C.sub.B.
It has been ascertained that the circuit according to the invention
does not allow the initiation of positive feedback before the
evaluation phase and minimizes the equivalent transconductance of
the inverters of the latch. Thus the frequency-dependent component
of the input offset voltage of he latch is practically nullified
and the total offset voltage V.sub.OSL of the latch is lower than
that of the known circuit and substantially constant even at high
frequencies.
A latch according to the invention utilized in a comparator such as
that shown in FIG. 1 allows comparison frequencies up to 200 MHZ to
be achieved.
FIG. 4 shows a CMOS circuit diagram of the latch represented in
block schematic form in FIG. 3. To facilitate understanding thereof
the various circuit groups corresponding to the blocks of FIG. 3
are indicated with the same reference symbols as in FIG. 3.
In FIG. 4 the timing circuit or clock CK' is not shown in that it
is of known type. The single characteristic aspect of the clock
CK', clearly within the scope of the man skilled in the art, is
constituted by the presence of a delay element to derive the
delayed clock signal V.sub.ckd.
Moreover, it is to be noted that in the circuit of FIG. 4, the
electronic switches S1-S6 are formed as transfer gates. This not
only allows any interference of the timing signals on the latch
(clock-feedthrough) to be avoided, but also obtains a completely
symmetrical structure since the "buffers" which provide the timing
signals have in this case the same capacitive charge. To simplify
the circuit, however, it would also be possible to utilize simple
transistors (pass transistors) as the electronic switches.
Having thus described at least one illustrative embodiment of the
invention, various alterations, modifications, and improvements
will readily occur to those skilled in the art. Such alterations,
modifications, and improvements are intended to be within the
spirit and scope of the invention. Accordingly, the foregoing
description is by way of example only and is not intended as
limiting. The invention is limited only as defined in the following
claims and the equivalents thereto.
* * * * *