U.S. patent number 6,140,255 [Application Number 09/261,543] was granted by the patent office on 2000-10-31 for method for depositing silicon nitride using low temperatures.
This patent grant is currently assigned to Advanced Micro Devices, Inc.. Invention is credited to Terri Jo Kitson, Minh Van Ngo, Khanh Nguyen.
United States Patent |
6,140,255 |
Ngo , et al. |
October 31, 2000 |
Method for depositing silicon nitride using low temperatures
Abstract
A method for depositing silicon nitride on a semiconductor wafer
uses plasma enhanced chemical vapor deposition at very low
temperatures. The temperature in a silicon nitride deposition
chamber is set to be about 170.degree. C. or less. Silane gas
(SiH.sub.4) flows into the silicon nitride deposition chamber with
a flow rate in a range of from about 300 sccm (standard cubic cm
per minute) to about 500 sccm. Nitrogen gas (N.sub.2) flows into
the silicon nitride deposition chamber with a flow rate in a range
of from about 500 sccm to about 2000 sccm. Ammonia gas (NH.sub.3)
flows into the silicon nitride deposition chamber with a flow rate
in a range of from about 1.0 slm to about 2.2 slm. A high frequency
RF signal is applied on a showerhead within the deposition chamber.
A low frequency RF signal is applied on a heating block for holding
the semiconductor wafer. A predetermined volume for the silicon
nitride deposition chamber is used such that pressure within the
silicon nitride deposition chamber is in a range of from about 1.0
torr to about 2.4 torr. The semiconductor wafer is placed inside
the silicon nitride deposition chamber for a soak time period of
about 30 seconds or greater before the high frequency RF signal is
applied on the showerhead in the deposition chamber and the low
frequency RF signal is applied on the heating block. When the
semiconductor wafer reaches the deposition temperature, the high
frequency RF signal and the low frequency RF signal are applied for
deposition of the silicon nitride layer onto the semiconductor
wafer. By using low temperatures during the deposition of the
silicon nitride layer, the structural integrity of any structure
already on the semiconductor wafer is advantageously preserved.
Inventors: |
Ngo; Minh Van (Union City,
CA), Kitson; Terri Jo (San Jose, CA), Nguyen; Khanh
(San Mateo, CA) |
Assignee: |
Advanced Micro Devices, Inc.
(Sunnyvale, CA)
|
Family
ID: |
46255411 |
Appl.
No.: |
09/261,543 |
Filed: |
March 3, 1999 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
|
212198 |
Dec 15, 1998 |
|
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|
Current U.S.
Class: |
438/791;
257/E21.035; 257/E21.279; 438/775; 438/776; 438/792 |
Current CPC
Class: |
C23C
16/402 (20130101); C23C 16/5096 (20130101); H01L
21/02164 (20130101); H01L 21/02211 (20130101); H01L
21/02274 (20130101); H01L 21/0332 (20130101); H01L
21/31612 (20130101) |
Current International
Class: |
C23C
16/40 (20060101); C23C 16/509 (20060101); C23C
16/50 (20060101); H01L 21/033 (20060101); H01L
21/02 (20060101); H01L 21/316 (20060101); H01L
021/31 (); H01L 021/469 () |
Field of
Search: |
;438/791-794,775-777 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Bowers; Charles
Assistant Examiner: Nguyen; Thanh
Attorney, Agent or Firm: Choi; Monica H.
Parent Case Text
This is a continuation-in-part of an earlier filed copending patent
application, with Ser. No. 09/212,198 filed on Dec. 15, 1998, for
which priority is claimed. This earlier filed copending patent
application with Ser. No. 09/212,198 is in its entirety
incorporated herewith by reference.
Claims
We claim:
1. A method for depositing silicon nitride on a substrate at very
low temperature using plasma enhanced chemical vapor deposition,
the method including the steps of:
setting a temperature, in a silicon nitride deposition chamber, to
be about 170.degree. C. or less;
flowing silane gas into the silicon nitride deposition chamber with
a flow rate in a range of from about 300 sccm (standard cubic cm
per minute) to about 500 sccm (standard cubic cm per minute);
flowing nitrogen gas (N.sub.2) into the silicon nitride deposition
chamber with a flow rate in a range of from about 500 sccm
(standard cubic cm per minute) to about 2000 sccm (standard cubic
cm per minute);
flowing ammonia gas (NH.sub.3) into the silicon nitride deposition
chamber with a flow rate in a range of from about 1.0 slm (standard
liters per minute) to about 2.2 slm (standard liters per
minute);
using a predetermined volume for the silicon nitride deposition
chamber such that pressure within the silicon nitride deposition
chamber is in a range of from about 1.0 torr to about 2.4 torr;
placing the substrate inside the silicon nitride deposition chamber
for a soak time period of about 30 seconds or greater;
applying a high frequency RF signal on a showerhead within the
silicon nitride deposition chamber, wherein the high frequency RF
signal has a power in a range of from about 300 Watts to about 700
Watts; and
applying a low frequency RF signal on a heating block for holding
the substrate within the silicon nitride deposition chamber,
wherein the low frequency RF signal has a power in a range of from
about 200 Watts to about 600 Watts,
wherein silicon nitride is deposited onto the substrate when said
high frequency RF signal is applied on said showerhead and when
said low frequency RF signal is applied on said heating block
holding the substrate.
2. The method of claim 1, further including the step of:
preseasoning the silicon nitride deposition chamber to a
temperature of about 170.degree. C. or less for about 300 seconds
before placing the substrate inside the silicon nitride deposition
chamber.
3. The method of claim 1, wherein said substrate is a semiconductor
wafer having a reflective layer of a reflective EUV mask and
wherein silicon nitride is deposited on top of the reflective
layer.
4. The method of claim 1, wherein said substrate is a glass
substrate having a reflective layer of a reflective EUV mask and
wherein silicon nitride is deposited on top of the reflective
layer.
5. The method of claim 1, wherein said low frequency RF signal is
applied on said heating block for a time period from about 5
seconds to about 30 seconds.
6. A method for depositing silicon nitride on a semiconductor
wafer, having a reflective layer of a reflective EUV mask, at very
low temperature using plasma enhanced chemical vapor deposition,
the method including the steps of:
setting a temperature, in a silicon nitride deposition chamber, to
be about 170.degree. C. or less;
flowing silane gas into the silicon nitride deposition chamber with
a flow rate in a range of from about 300 sccm (standard cubic cm
per minute) to about 500 sccm (standard cubic cm per minute);
flowing nitrogen gas (N.sub.2) into the silicon nitride deposition
chamber with a flow rate in a range of from about 500 sccm
(standard cubic cm per minute) to about 2000 sccm (standard cubic
cm per minute);
flowing ammonia gas (NH.sub.3) into the silicon nitride deposition
chamber with a flow rate in a range of from about 1.0 slm (standard
liters per minute) to about 2.2 slm (standard liters per
minute);
using a predetermined volume for the silicon nitride deposition
chamber such that pressure within the silicon nitride deposition
chamber is in a range of from about 1.0 torr to about 2.4 torr;
preseasoning the silicon nitride deposition chamber to a
temperature of about 170.degree. C. or less for about 300 seconds
before placing the semiconductor wafer inside the silicon nitride
deposition chamber;
placing the semiconductor wafer inside the silicon nitride
deposition chamber for a soak time period of about 30 seconds or
greater;
applying a high frequency RF signal on a showerhead within the
silicon nitride deposition chamber, wherein the high frequency RF
signal has a power in a range of from about 300 Watts to about 700
Watts; and
applying a low frequency RF signal on a heating block for holding
the semiconductor wafer within the silicon nitride deposition
chamber for a time period of from about 5 seconds to about 30
seconds, wherein the low frequency RF signal has a power in a range
of from about 200 Watts to about 600 Watts,
wherein silicon nitride is deposited onto the semiconductor wafer
when said high frequency RF signal is applied on said showerhead
and when said low frequency RF signal is applied on said heating
block holding the substrate .
Description
TECHNICAL FIELD
The present invention relates generally to lithography, and more
particularly, to a method for effectively depositing silicon
nitride at very low temperatures on an EUV mask to preserve the
integrity of the EUV mask.
BACKGROUND OF THE INVENTION
As device densities continually increase on a semiconductor wafer,
device dimensions are further scaled down to smaller feature size.
With such smaller feature size, higher resolution photolithographic
processes are desired. In general, lithography refers to processes
for pattern transfer between various media. As known to one of
ordinary skill in the art of integrated circuit fabrication,
exposure of a photoresist layer on a semiconductor wafer to a
pattern of illumination (such as from ultraviolet light, x-rays, or
an electron beam) results in a desired pattern on the semiconductor
wafer for further processing.
For smaller feature size, projection lithography and use of extreme
violet (EUV) radiation are important tools for integrated circuit
fabrication. Extreme ultraviolet (EUV) radiation has a wavelength
range of about 50 to 700 .ANG. (Angstroms) (i.e, about 5 to 70 nm
(nanometer)). A projection lithography system 100 using EUV
radiation is illustrated in FIG. 1. In the projection lithography
system 100, an EUV light source 102 provides EUV radiation as known
to one of ordinary skill in the art.
An EUV mask 104 has a pattern of regions which absorb the EUV
radiation from the EUV light source 102 and regions which reflect
the EUV radiation from the EUV light source 102 to produce a
reflected image. A reflective imaging system 106 (which is
typically comprised of a series of high precision mirrors) projects
the reflected image by de-magnifying or reducing the reflected
image from the EUV mask 104 onto a semiconductor wafer 108. The
semiconductor wafer 108 has a photoresist layer that is patterned
to the de-magnified reflected image from the reflective imaging
system 106.
The EUV mask 104 is a reflective reticle having a pattern comprised
of regions which absorb the EUV radiation from the EUV light source
102 and regions which reflect the EUV radiation from the EUV light
source 102. The regions which absorb the EUV radiation and the
regions which reflect the EUV radiation are formed as shown in FIG.
2. Referring to FIG. 2A, a reflective layer 202 is formed on a
substrate layer 204 of silicon or glass. The reflective layer 202
is typically a multilayer coating of alternating layers of
molybdenum and silicon having respective thickness of approximately
40 .ANG. (angstroms). The reflective layer 202 is designed to
reflect the EUV radiation with high efficiency (e.g., about 65% or
more).
The reflective layer 202 is then covered with a buffer layer 206 to
protect the reflective layer 202 and to prevent oxidation of the
reflective layer 202 during subsequent processing of the EUV mask.
The buffer layer 206 may be comprised of one of silicon dioxide or
silicon nitride. An absorber layer 208 is deposited on top of the
buffer layer 206, and the absorber layer is comprised of EUV
absorptive material such as silver, tungsten, gold, tantalum,
titanium, lead, polyimide, polymethyl methacrylate, etc.
Referring to FIG. 2B, the desired pattern for the regions which
absorb the EUV radiation is made by a patterned photoresist layer
210 as known to one of ordinary skill in the art. Referring to FIG.
2C, the absorber layer 208 is patterned according to the
photoresist layer 210. Referring to FIG. 2D, the photoresist layer
210 is then removed. The buffer layer 206 protects the reflective
layer 202 during the etching of the absorber layer 208 and the
removal of the photoresist layer 210.
Referring to FIG. 2E, the buffer layer 206 is selectively removed
for exposing the reflective layer 202 in regions without the
absorptive material of the absorber layer 208. In this manner, a
pattern of regions that absorb the EUV radiation is formed where
the absorptive material of the absorber layer 208 remain. The
regions where the reflective layer 202 is exposed reflect the EUV
radiation. Referring to FIG. 2F, a capping layer 212 of amorphous
silicon of approximately 70 .ANG. (Angstroms) may also be deposited
on top of the reflective layer 202 to protect the reflective layer
202.
During fabrication of the EUV mask 104 as shown in FIGS. 2A, the
buffer
layer 206 is deposited on top of the reflective layer 202. The
reflective layer 202 is a delicate structure of thin layers (having
respective thicknesses of approximately 40 .ANG. (Angstroms)) of
alternating molybdenum and silicon. To fabricate an effective EUV
mask 104, a process is desired for depositing the buffer layer 206
on top of the reflective layer 202 which also preserves the
integrity of the reflective layer 202.
The buffer layer 206 is typically comprised of one of silicon
dioxide or silicon nitride. In the prior art, processes for
depositing silicon dioxide or silicon nitride typically use high
temperatures of around 300.degree. C. to 400.degree. C. However,
such high temperatures may degrade the structure of the reflective
layer 202 which is comprised of thin alternating layers of
molybdenum and silicon. A process for depositing silicon dioxide
using lower temperatures of approximately 170.degree. C. or less is
described in copending patent application with Ser. No. 09/212,198
filed on Dec. 15, 1998 and having common inventors and assignee
herewith. In addition, a process for depositing silicon nitride
using lower temperature of approximately 170.degree. C. or less is
desired for depositing the buffer layer 206 such that the
structural integrity of the reflective layer 202 is preserved when
silicon nitride is used for the buffer layer 206.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the present invention is to
deposit a buffer layer of silicon nitride at lower temperatures of
approximately 170.degree. C. or less in order to preserve the
structural integrity of the reflective layer on an EUV mask.
In a general aspect of the present invention, a method for
depositing silicon nitride on an EUV mask uses plasma enhanced
chemical vapor deposition at very low temperatures. The method of
the present invention includes the step of setting a temperature,
in a silicon nitride deposition chamber, to be about 170.degree. C.
or less. In addition, the method of the present invention includes
the step of flowing silane gas into the silicon nitride deposition
chamber with a flow rate in a range of from about 300 sccm
(standard cubic cm per minute) to about 500 sccm (standard cubic cm
per minute), flowing nitrogen gas (N.sub.2) into the silicon
nitride deposition chamber with a flow rate in a range of from
about 500 sccm (standard cubic cm per minute) to about 2000 sccm
(standard cubic cm per minute), and flowing ammonia gas (NH.sub.3)
into the silicon nitride deposition chamber with a flow rate in a
range of from about 1.0 slm (standard liters per minute) to about
2.2 slm (standard liters per minute).
A predetermined volume for the silicon nitride deposition chamber
is used such that pressure within the silicon nitride deposition
chamber is in a range of from about 1.0 torr to about 2.4 torr. The
method of the present invention also includes the step of placing
the semiconductor wafer inside the silicon nitride deposition
chamber for a soak time period of about 30 seconds or greater. When
the semiconductor wafer reaches a deposition temperature, a high
frequency RF signal is applied on a showerhead inside the silicon
nitride deposition chamber, and a low frequency RF signal is
applied on a heating block for holding the semiconductor wafer
within the silicon nitride deposition chamber. The high frequency
RF signal has a power in a range of from about 300 Watts to about
700 Watts. The low frequency RF signal has a power in a range of
from about 200 Watts to about 600 Watts. Silicon nitride is
deposited onto the semiconductor wafer when the high frequency RF
signal and the low frequency RF signal are thus applied.
The present invention may be used to particular advantage when the
present invention further includes the step of preseasoning the
silicon nitride deposition chamber to a temperature of about
170.degree. C. or less for about 300 seconds before placing the
semiconductor wafer inside the silicon nitride deposition
chamber.
By depositing the silicon nitride layer at the lower temperatures
of about 170.degree. C. or less, the structural integrity of the
reflective layer already deposited on the EUV mask is preserved
during the deposition process of the present invention.
These and other features and advantages of the present invention
will be better understood by considering the following detailed
description of the invention which is presented with the attached
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a projection lithography system using a reflective EUV
mask;
FIG. 2, including FIGS. 2A, 2B, 2C, 2D, 2E, and 2F, shows the steps
for fabricating a reflective EUV mask having a buffer layer, which
may be comprised of silicon dioxide or silicon nitride, on top of a
reflective layer comprising alternating layers of molybdenum and
silicon; and
FIG. 3 illustrates a silicon nitride deposition system of the
present invention for depositing a silicon nitride layer at very
low temperatures of about 170.degree. C. or less.
The figures referred to herein are drawn for clarity of
illustration and are not necessarily drawn to scale. Elements
having the same reference number in FIGS. 1, 2, and 3 refer to
elements having similar structure and function.
DETAILED DESCRIPTION
The EUV mask may be formed on a substrate layer of silicon or
glass. In an exemplary embodiment, the EUV mask is formed on a
semiconductor wafer. Referring to FIG. 3, a semiconductor wafer 302
having an EUV mask formed thereon is placed into a silicon nitride
deposition chamber 304 for deposition of silicon nitride onto the
semiconductor wafer 302 which may be comprised of silicon.
A silane (SiH.sub.4) source 306, a nitrogen (N.sub.2) source 308,
and an ammonia (NH.sub.3) source 310 are coupled to the silicon
nitride deposition chamber 304. Silane (SiH.sub.4) gas flows from
the silane (SiH.sub.4) source 306 into the silicon nitride
deposition chamber 304. Nitrogen (N.sub.2) gas flows from the
nitrogen (N.sub.2) source 308 into the silicon nitride deposition
chamber 304. Ammonia (NH.sub.3) gas flows from the ammonia
(NH.sub.3) source 310 into the silicon nitride deposition chamber
304.
The silicon nitride deposition chamber 304 further includes a
showerhead 312 which is fed with silane gas from the silane
(SiH.sub.4) source 306, nitrogen (N.sub.2) gas from the nitrogen
(N.sub.2) source 308, and ammonia (NH.sub.3) gas from the ammonia
(NH.sub.3) source 310. In addition, a high frequency RF signal
generator 314 is operatively coupled to the showerhead 312. A high
frequency RF signal from the high frequency RF signal generator 314
is applied to the showerhead 312 for producing the plasma in the
plasma enhanced chemical vapor deposition process of the present
invention.
The silicon nitride deposition chamber 304 further includes a
heating block 316 which holds the semiconductor wafer 302 during
the plasma enhanced chemical vapor deposition of the present
invention. The heating block 316 is heated up to a predetermined
temperature to maintain the semiconductor wafer 302 at the
predetermined temperature. In addition, a low frequency RF signal
generator 318 is operatively coupled to the heating block 316. A
low frequency RF signal from the low frequency RF signal generator
318 is applied to the heating block 316 holding the semiconductor
wafer 302 such that a voltage bias appears on the heating block
302. Such voltage bias on the heating block 302 attracts the plasma
generated by the showerhead 312 toward the semiconductor wafer 302.
Thus, plasma from the showerhead 312 is present near the
semiconductor wafer 302 during the plasma enhanced chemical vapor
deposition process of the present invention.
Furthermore, the silicon nitride deposition chamber 304 of the
present invention further includes a deposition chamber temperature
controller 320. The temperature controller 320 maintains the
temperature within the deposition chamber 304 to be at a
predetermined setting.
The operation of the silicon nitride deposition chamber 304 for
depositing silicon nitride onto the semiconductor wafer 302 using
low temperatures is now described. The silicon nitride deposited
onto the semiconductor wafer 302 is advantageously used to form the
buffer layer 206 during fabrication of an EUV mask as illustrated
in FIG. 2.
In contrast to a prior art silicon nitride deposition process which
uses higher temperatures of about 300.degree. C. to 400.degree. C.,
the present invention is a low temperature silicon nitride
deposition process that uses lower temperatures of about
170.degree. C. or less. Thus, during fabrication of an EUV mask as
illustrated in FIG. 2, the structural integrity of the reflective
layer 202, onto which the buffer layer 206 of silicon nitride is
deposited, is preserved during the silicon nitride deposition
process of the present invention.
With the plasma enhanced chemical vapor deposition process of the
present invention, the silane (SiH.sub.4) gas from the silane
(SiH.sub.4) source 306 flows into the silicon nitride deposition
chamber 304 with a flow rate in a range of from about 300 sccm
(standard cubic cm per minute) to about 500 sccm (standard cubic cm
per minute). The nitrogen (N.sub.2) gas from the nitrogen (N.sub.2)
source 308 flows into the silicon nitride deposition chamber 304
with a flow rate in a range of from about 500 sccm (standard cubic
cm per minute) to about 2000 sccm (standard cubic cm per minute).
The ammonia (NH.sub.3) gas from the ammonia (NH.sub.3) source 310
flows into the silicon nitride deposition chamber 304 with a flow
rate in a range of from about 1.0 slm (standard liters per minute)
to about 2.2 slm (standard liters per minute).
In addition, the temperature within the silicon nitride deposition
chamber 304 is set to be about 170.degree. C. or less via the
deposition chamber temperature controller 320. In addition, the
heating block 316 which holds the semiconductor wafer 302 during
the plasma enhanced chemical vapor deposition process of the
present invention is also heated up to be about 170.degree. C. or
less.
With the plasma enhanced chemical vapor deposition process of the
present invention, a high frequency RF signal is applied on the
showerhead 312 from the high frequency RF signal generator 314. In
the present invention, the high frequency RF signal applied on the
showerhead 312 has a power in a range of from about 300 Watts to
about 700 Watts. Additionally, a low frequency RF signal is applied
on the heating block 316 that holds the semiconductor wafer 302
during the plasma enhanced chemical vapor deposition process of the
present invention. In the present invention, the low frequency RF
signal is generated from the low frequency RF signal generator 318
with a power in a range of from about 200 Watts to about 600
Watts.
The low frequency RF signal applied to the heating block 316
creates a voltage bias on the heating block 316. Such voltage bias
on the heating block 316 attracts the plasma generated by the
showerhead 312 toward the semiconductor wafer 302. Thus, plasma
from the showerhead 312 is present near the semiconductor wafer 302
during the plasma enhanced chemical vapor deposition process of the
present invention.
With the plasma enhanced chemical vapor deposition process of the
present invention, the silicon nitride deposition chamber 304 has a
predetermined volume such that pressure within the silicon nitride
deposition chamber 304 is in a range of from about 1.0 torr to
about 2.4 torr.
With the above-mentioned conditions within the silicon nitride
deposition chamber 304, the semiconductor wafer 302 is placed
within the silicon nitride deposition chamber 304 for a soak time
period of about 30 seconds or greater. During such time period, the
semiconductor wafer 302 soaks up to a higher temperature to reach a
deposition temperature of about 170.degree. C. or less. During such
soak time, the high frequency RF signal from the high frequency RF
signal generator 314 is not applied on the showerhead 312, and the
low frequency RF signal from the low frequency RF signal generator
318 is not applied on the heating block 316.
Before the semiconductor wafer 14 is placed into the silicon
nitride deposition chamber 304 for the soak time, the silicon
nitride deposition chamber 304 may be preseasoned for 300 seconds.
In such a preseasoning process, the silicon nitride deposition
chamber 304 and the heating block 316 are preheated to a
temperature of about 170.degree. C. or less with the silane
(SiH.sub.4) gas, the nitrogen (N.sub.2) gas, and the ammonia
(NH.sub.3) gas flowing into the silicon nitride deposition chamber
304 with the respective flow rates discussed above.
After thus preseasoning the silicon nitride deposition chamber 304,
the semiconductor wafer 302 is placed into the silicon nitride
deposition chamber 304. The semiconductor wafer 302 is placed on
the heating block 316 for a soak time period of about 30 seconds or
greater. During such time period, the semiconductor wafer 302 soaks
up to a higher temperature to reach a deposition temperature of
about 170.degree. C. or less. During such soak time, the high
frequency RF signal from the high frequency RF signal generator 314
is not applied on the showerhead 312, and the low frequency RF
signal from the low frequency RF signal generator 318 is not
applied on the heating block 316.
After the temperature soak time when the semiconductor wafer 302
has reached the deposition temperature, silicon nitride deposition
takes place on the semiconductor wafer 302 when the high frequency
RF signal from the high frequency RF signal generator 314 is
applied on the showerhead 312 and when the low frequency RF signal
from the low frequency RF signal generator 318 is applied on the
heating block 316. The time period for the silicon nitride
deposition onto the semiconductor wafer 302 is from about 5 seconds
to about 30 seconds.
In this manner, a silicon nitride layer is deposited onto the
semiconductor wafer within the silicon nitride deposition chamber
304 using a plasma enhanced chemical vapor deposition process at
low temperatures of about 170.degree. C. or less. In prior art
silicon nitride deposition processes, a higher temperature of about
300.degree. C. to 400.degree. C. is typically used. By using such
low temperatures for deposition of the silicon nitride layer, the
present invention is especially amenable for depositing the silicon
nitride layer on top of a reflective layer used for a reflective
mask as shown in FIG. 2. Because low temperatures are used, the
structural integrity of the reflective layer already deposited on
the semiconductor wafer 302 is preserved with the silicon nitride
deposition process of the present invention.
In the present invention, a relatively high level of power for the
low frequency RF signal is used for higher ion bombardment during
silicon nitride deposition. With such higher level of power for the
low frequency RF signal, a silicon nitride layer of higher
compressive stress results for higher film quality of the silicon
nitride layer. In addition, a relatively lower pressure within the
silicon nitride deposition chamber 304 and a relatively longer
temperature soak time are used to result in a silicon nitride layer
of higher density.
The foregoing is by way of example only and is not intended to be
limiting. For example, instead of the semiconductor wafer 302, a
glass substrate may hold the EUV mask structure. In addition, the
advantageous features of the present invention may be used for
deposition of a silicon nitride layer for any type of application
which requires deposition of silicon nitride at lower temperatures.
In general, the present invention may be advantageously used for
deposition of a silicon nitride layer whereby a low temperature of
the semiconductor wafer during the deposition process is
desired.
Furthermore, as will be understood by those skilled in the art, the
mask structures described herein may be made or used in the same
way regardless of their position and orientation. Accordingly, it
is to be understood that terms and phrases such as "above" and "on
top of" as used herein refer to the relative location and
orientation of various portions of the structures with respect to
one another, and are not intended to suggest that any particular
absolute orientation with respect to external objects is necessary
or required. The invention is limited only as defined in the
following claims and equivalents thereof.
* * * * *