U.S. patent number 5,712,189 [Application Number 08/056,004] was granted by the patent office on 1998-01-27 for epitaxial overgrowth method.
This patent grant is currently assigned to Texas Instruments Incorporated. Invention is credited to Tae Seung Kim, Donald Lynn Plumton.
United States Patent |
5,712,189 |
Plumton , et al. |
January 27, 1998 |
Epitaxial overgrowth method
Abstract
A vertical field effect transistor (700) and fabrication method
with buried gates (704) having gate sidewall crystal orientation
the same as the substrate surface and a low index substrate crystal
orientation without tilt to a higher index direction. The gate
(704) may have modulated doping along the channel (706), and the
drain (708) may have a lighter doping level than the channel which
may be accomplished by an epitaxial overgrowth of the gates (704)
to form the channels (706).
Inventors: |
Plumton; Donald Lynn (Dallas,
TX), Kim; Tae Seung (Dallas, TX) |
Assignee: |
Texas Instruments Incorporated
(Dallas, TX)
|
Family
ID: |
22001535 |
Appl.
No.: |
08/056,004 |
Filed: |
April 30, 1993 |
Current U.S.
Class: |
117/101; 117/902;
257/E21.09; 257/E21.387; 257/E21.406; 257/E21.449; 257/E21.537;
257/E27.012; 257/E27.016; 257/E29.004; 257/E29.059; 257/E29.061;
257/E29.189; 257/E29.243; 257/E29.313; 438/193 |
Current CPC
Class: |
H01L
21/74 (20130101); H01L 27/0605 (20130101); H01L
27/0629 (20130101); H01L 29/045 (20130101); H01L
29/1066 (20130101); H01L 29/1075 (20130101); H01L
29/66318 (20130101); H01L 29/66454 (20130101); H01L
29/66924 (20130101); H01L 29/7371 (20130101); H01L
29/7722 (20130101); H01L 29/8083 (20130101); H01L
21/02546 (20130101); H01L 21/02576 (20130101); H01L
21/0262 (20130101); Y10S 117/902 (20130101) |
Current International
Class: |
H01L
21/70 (20060101); H01L 21/02 (20060101); H01L
21/74 (20060101); H01L 21/335 (20060101); H01L
29/10 (20060101); H01L 21/20 (20060101); H01L
29/02 (20060101); H01L 21/337 (20060101); H01L
29/66 (20060101); H01L 29/04 (20060101); H01L
29/772 (20060101); H01L 29/737 (20060101); H01L
21/331 (20060101); H01L 29/808 (20060101); H01L
27/06 (20060101); H01L 021/20 () |
Field of
Search: |
;437/133,40,203
;748/DIG.110 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
Donald L. Plumton, Jau-Yuann Yang, F.J. Morris and Steven A.
Lambert; Planar AlGaAs/GaAs HBT Fabricated by MOCVD Overgrowth with
a Grown Base; IEEE Transactions on Electron Devices, vol. 37. No.
5; May 1990; pp. 1187-1192. .
R. P. Leon, S.G. Bailey, G.A. Mazaris and W.D. Williams; Formation
of a pn junction on an anisotropically etched GaAs surface using
metalorganic chemical vapor deposition; Applied Physics Letter 49
(15), 13 Oct. 1986; pp. 945-947. .
Susumu Noda, Kenzo Fujiwara and Takashi Nakayama; Effects of
FaAs/AlAs superlattice buffer layers on selective area regrowth for
FaAs/AlFaAs self-aligned structure lasers; Applied Physics Letter
47 (11), 1 Dec. 1985; pp. 1205-1207..
|
Primary Examiner: Quach; T. N.
Attorney, Agent or Firm: Hoel; Carlton H. Brady; W. James
Donaldson; Richard L.
Government Interests
GOVERNMENT CONTRACT
This invention was made with Government support under Contract No.
N66001-91-C-6008 awarded by the Department of the Navy. The
Government has certain rights in this invention.
Claims
What is claimed is:
1. A method of III-V semiconductor epitaxial overgrowth, comprising
the steps of:
(a) providing a semiconductor layer, said layer with a planar
surface and with at least two parallel trenches extending into said
planar surface, each of said trenches having sidewalls
perpendicular to said planar surface and with a bottom parallel to
said planar surface, said sidewalls forming a series of parallel
sidewalls with each sidewall having crystal orientation equivalent
to that of said planar surface within about 5.degree.; and
(b) epitaxially growing an epilayer of a semiconductor material
simultaneously on said planar surface and said sidewalls and said
bottoms;
(c) wherein said layer is made of a first III-V compound and said
epilayer is made of a second III-V compound.
2. The method of claim 1, wherein:
(a) said first III-V compound is gallium arsenide containing
dopants; and
(b) said second III-V compound is gallium arsenide containing
dopants.
3. The method of claim 1, wherein:
(a) said planar surface has a (100) orientation.
4. The method of claim 3, wherein:
(a) said layer has p-type doping adjacent said surface and n-type
doping away from said surface, wherein said n-type doping is
exposed at the bottoms of said trenches.
5. The method of claim 4, wherein:
(a) said epilayer has n-type doping; and
(b) said epitaxially growing is by metalorganic chemical vapor
deposition.
6. The method of claim 5, wherein:
(a) said layer has carbon doping adjacent said surface and silicon
doping about said bottoms of said trenches; and
(b) said epilayer has silicon doping.
7. The method of claim 6, comprising the further steps of:
(a) epitaxially growing a second epilayer of a semiconductor
material on said epilayer; and
(b) wherein said second epilayer is made of a third III-V compound
and has n-type doping.
8. The method of claim 7, wherein:
(a) said first III-V compound is gallium arsenide containing
dopants;
(b) said second III-V compound is gallium arsenide containing
dopants; and
(c) said third III-V compound is aluminum gallium arsenide
containing dopants.
9. A method of III-V semiconductor epitaxial overgrowth, comprising
the steps of:
(a) providing a semiconductor layer, said layer with a planar
surface and with at least two parallel fingers on said planar
surface, each of said fingers having sidewalls perpendicular to
said planar surface and with a top parallel to said planar surface,
said sidewalls forming a series of parallel sidewalls with each
sidewall having crystal orientation equivalent to that of said
planar surface within about 5.degree.; and
(b) epitaxially growing an epilayer of a semiconductor material
simultaneously on said planar surface and said sidewalls and said
tops,
(c) wherein said layer is made of a first III-V compound and said
epilayer is made of a second III-V compound.
10. The method of claim 9, wherein:
(a) said first III-V compound is gallium arsenide containing
dopants; and
(b) said second III-V compound is gallium arsenide containing
dopants.
11. The method of claim 9, wherein:
(a) said planar surface has a (100) orientation.
12. The method of claim 11, wherein:
(a) said fingers have p-type doping; and
(b) said layer has n-type doping.
13. The method of claim 12, wherein:
(a) said epilayer has n-type doping; and
(b) said epitaxially growing is by metalorganic chemical vapor
deposition.
14. The method of claim 13, wherein:
(a) said fingers have carbon doping; and
(b) said layer adjacent said planar surface has silicon doping.
15. The method of claim 14, further comprising the step of:
(a) epitaxially growing a second epilayer of a semiconductor
material on said epilayer;
(b) wherein said second epilayer is made of a third III-V compound
and has n-type doping.
16. The method of claim 15, wherein:
(a) said first III-V compound is gallium arsenide containing
dopants;
(b) said second III-V compound is gallium arsenide containing
dopants; and
(c) said third III-V compound is aluminum gallium arsenide
containing dopants.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
The following applications contain subject matter related to the
present application and are assigned to the assignee of the present
application: application Ser. No. 07/876,252, filed Apr. 30, 1992,
U.S. Pat. No. 5,231,037 application Ser. No. 08/036,584, filed Mar.
24, 1993, abandoned and cofiled applications with Ser. Nos.
08/055,421, 08/056,681, and 08/056,682.
BACKGROUND OF THE INVENTION
The invention relates to electronic semiconductor devices and
circuits, and, more particularly, to methods of fabrication with
epitaxial overgrowth and devices so fabricated.
Various semiconductor processing flows include formation of
epitaxial layers on substrates. Such epilayers may provide a change
in doping level, a crystal superior to the substrate's, or even a
change in material such as a gallium arsenide (GaAs) substrate with
an aluminum gallium arsenide (Al.sub.x Ga.sub.1-x As) epilayer for
heterojunction devices. Epilayer growth by metalorganic chemical
vapor deposition (MOCVD) on {100} oriented GaAs substrates produces
smoother surfaces when the substrate orientation is tilted
2.degree. in the {110} direction, and industry standard GaAs wafers
have such an orientation tilt. This tilt provides a slightly
terraced surface (terrace widths on the order of 100-200 .ANG.)
which apparently insures smooth epilayer growth.
Certain processing flows include epitaxial overgrowth of nonplanar
structures. In particular, silicon bipolar transistor processes
frequently have a buried layer formed by epitaxial overgrowth of a
doped region which has been depressed below the substrate surface
by an oxidizing drive-in cycle. But more significantly,
heterojunction bipolar transistors (HBTs) and self-aligned
structure (SAS) lasers can be fabricated with epitaxial growth over
steps in a GaAs layer. See Plumton et al, Planar AlGaAs/GaAs HBT
Fabricated by MOCVD Overgrowth with a Grown Base, 37 IEEE Trans.
Elec. Dev. 118 (1990)(growth of n-Al.sub.x Ga.sub.1-x As emitter
over p-GaAs base mesa for an HBT) and Noda et al, Effects of
GaAs/AlAs superlattic buffer layers on selective area regrowth for
GaAs/AlGaAs self-aligned structure lasers, 47 Appl. Phys. Lett.
1205 (1985)(molecular beam epitaxy growth of p-Al.sub.x Ga.sub.1-x
As over n-GaAs antiguiding mesa for a SAS laser).
However, such epitaxial overgrowth on step structures has problems
including finding growth conditions for enhancing device
performance.
SUMMARY OF THE INVENTION
The present invention provides epitaxial overgrowth with III-V
compound semiconductors (compounds of elements from groups III and
V of the periodic table) over steps in substrates with sidewalls
having approximately equivalent crystal plane orientation as the
substrate surface.
BRIEF DESCRIPTION OF THE DRAWINGS
The drawings are schematic for clarity.
FIGS. 1a-1c are perspective and cross-sectional elevation and plan
views of a first preferred embodiment vertical field effect
transistor.
FIGS. 2a-2c show electrical characteristics and behavior of the
first preferred embodiment.
FIGS. 3a-3d illustrate applications of the first preferred
embodiment.
FIGS. 4a-4d show steps in a first preferred embodiment method of
fabrication.
FIGS. 5a-5c are plan views of semiconductor substrates illustrating
a step of the preferred embodiment method of fabrication.
FIGS. 6a-6b show oriented substrates and epitaxial growth.
FIG. 7 illustrates in cross sectional view a second preferred
embodiment.
FIGS. 8a-8b illustrate equipotentials of the second preferred
embodiment.
FIGS. 9a-9b show electrical characteristics of the second preferred
embodiment.
FIG. 10 is a cross sectional elevation view of a third preferred
embodiment.
FIG. 11 is a perspective view of a fourth preferred embodiment.
FIG. 12 illustrates in cross sectional view a fifth preferred
embodiment.
FIG. 13 shows in cross sectional view a sixth preferred
embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Preferred Embodiment YFET
FIG. 1a shows in cutaway perspective view a first preferred
embodiment vertical field effect transistor (VFET), generally
denoted by the reference numeral 100, made of gallium arsenide
(GaAs) and including n doped source 102, p+ doped gate 104 in the
form of parallel fingers with n doped channel regions 106 between
successive gate fingers, and n doped drain 108 which includes a
drift region. FIG. 1b shows VFET 100 in cross sectional elevation
view and also shows source contact 112, metal gate contact 114
which connects to gate 104 through p+ region 115, and bottom drain
contact 118. FIG. 1c heuristically shows a plan view and indicates
that the array of parallel gate fingers and channels can be
repeated to increase total gate and channel width while retaining
low gate resistance because of the gate metal around each repeated
cell 150. Alternatively, the drain contact could be taken to the
top surface analogous to the collector in a vertical bipolar
transistor structure; this would also permit use of a high
resistivity substrate and integration of other devices without a
common drain. Note that for clarity FIGS. 1b-c show only seven
channel regions 106 between adjacent parallel p+ regions 115; more
typically there would be about 100-200 channel regions between
adjacent parallel p+ regions, and the overall size of the
rectangular areas surrounded by p+ 115 would be 100 .mu.m by 200
.mu.m. The use of metal gate contact 114 strapping the entire p+
region 115 lowers the gate resistance for high frequency
operation.
VFET 100 has the structure of parallel junction field effect
transistors (JFETs) with current flowing vertically in FIGS. 1a-b.
With a positive voltage V.sub.DS applied from drain to source,
majority carrier electrons flow from source 102 through channel
regions 106 to drain 108; and a voltage V.sub.GS applied to gate
104 (reverse bias of the p-n junction) controls this flow by
modulating the carrier levels in channel regions 106. The gate
length equals the channel length plus the associated p-n depletion
region and is the vertical distance indicated in FIG. 1b. The
channel opening is the distance between adjacent gate fingers as
shown in FIG. 1b. VFET 100 has a channel length of 0.3 .mu.m and a
channel opening of 0.5 .mu.m with a channel doping concentration of
3.times.10.sup.16 atoms/cm.sup.3.
FIG. 2a illustrates the electrical characteristics of VFET 100. For
V.sub.GS equal to 0, the depletion region of the p-n junction
formed by gate 104 and channel 106 takes up about half of channel
106, and the drain current I.sub.D is proportional to V.sub.DS for
small V.sub.DS and flows through the undepleted neutral central
portion of channel 106. The ratio I.sub.D /V.sub.DS is called the
on-resistance R.sub.ON and depends upon the channel material,
geometry, doping level, substrate resistance, and contact
resistance. The channel material resistivity equals roughly 25
micro-ohm-cm.sup.2 for VFET 100 while for the entire VFET it is
roughly 50-100 micro-ohm-cm.sup.2.
As V.sub.GS becomes negative and increases in magnitude, the
neutral central channel portion begins to pinch off due to the
reverse bias of the gate-channel junction, and the drain current
pinches off. This represents the standard triodelike operation of a
vertical JFET. Power switching applications only use turned-on and
turned-off states of VFET 100. V.sub.GS =0 (or V.sub.GS positive to
forward bias the gate-channel junction for current injection) will
turn on VFET 100 and I.sub.D will be large and V.sub.DS will be
small; whereas, V.sub.GS large (negative) will turn off VFET 100
and I.sub.D will be a leakage current and V.sub.DS will be large.
Thus the saturated current regime of pentodelike operation of a
JFET will not typically be used.
With V.sub.GS =-2 volts the gate-channel junction depletion regions
fill up channels 106 and this allows only leakage drain current
I.sub.D until V.sub.DS reaches a certain minimum value (the
blocking voltage). Further increases in V.sub.DS beyond the
blocking voltge cause a rapid increase in drain current. The drain
current follows a space charge limited dependence on V.sub.DS and
thus VFET 100 exhibits triodelike operation. Increasing
.vertline.V.sub.GS .vertline. increases the blocking voltage, and
the ratio of blocking voltage to .vertline.V.sub.GS .vertline. is
the DC blocking gain. VFET 100 has a DC blocking gain of roughly 3
to 20 for V.sub.DS in the range of 5 to 50 volts. Very high
blocking voltages require long gates and large opening channels
(large channel length to opening ratios) and reduced channel doping
levels to limit the influence of V.sub.DS on the channel depletion
regions and prevent the space charge limited current. Also high
blocking voltages require large drains (drift regions) with low
doping levels to support the large potential drop without avalanche
breakdown. FIGS. 2b-c heuristically illustrate the channel carrier
concentrations as a percentage of the undepleted channel carrier
concentration for V.sub.GS equal to -3 volts and with V.sub.DS
below the blocking voltage and above the blocking voltage,
respectively.
VFET Applications
VFET 100 provides high frequency switching by low gate capacitance
and low gate resistance through high gate doping levels and low
channel doping levels plus small gate dimensions. FIG. 3a
heuristically shows multiple VFET 100s with their drains all
connected to a power supply V.sub.DD at +5 volts, with their
sources connected to various devices 301, 302, . . . 310, and with
their gates driven by controller 320. Thus controller 320 controls
the power supply to each of devices 301, 302, . . . 310. Because
VFETs 100 require a negative gate voltage to turn off, controller
320 has charge pump 330 to provide -3 volts. Both controller 320
and charge pump 330 could be CMOS circuits. The arrangement of FIG.
3a could be employed in battery powered systems such as portable
computers where the devices 301, 302, . . . 310 would be items such
as disk drives, keyboards, screens, CPUs, modems, and so forth with
controller software controlled and interrupt driven to turn off all
items not in use but quickly turn on items upon demand for use.
Such power management will extend the charge life of a battery
operating the portable computer, and the low voltage levels (e.g.,
down to 3.3 or even 1.5 volts) require a low R.sub.ON plus the high
CPU frequencies (50 MHz) require rapid power switching.
FIG. 3b shows a preferred embodiment switching voltage regulator
including p-channel FET 340, lowpass filter made of inductor 342
and capacitor 344, free-wheeling diode 346, VFET 100, and pulse
width modulator plus controller 348. This regulator has the "buck"
topology and basically operates as follows. Controller 348 switches
FET 340 at a fixed frequency (e.g., 100 KHz) and senses the output
voltage to control the duty cycle of the switching of FET 340; this
feedback sets the output DC voltage. The lowpass filter filters the
resulting square wave from FET 340 to produce a ripple free DC
output. Controller 348 includes a charge pump to generate negative
gate voltage for VFET 100 and turns on VFET 100 when FET 340 is
turned off; thus VFET 100 provides a low resistance path to ground
and prevents the output node of FET 340 from going negative during
the portion of the switching cycle in which FET 340 is turned off.
Free-wheeling diode 346 parallels VFET 100 and provides the same
function; however, free-wheeling diode 346 would cause a diode
voltage drop, and without VFET 100 the average output DC current
would pass through free-wheeling diode to cause power losses. VFET
100 provides a lower resistance path for the average DC current and
eliminates the diode voltage drop and its attendant power
losses.
FIG. 3c illustrates a known DC--DC converter including a Schottky
diode 350 for rectification. The converter operates in somewhat the
same manner as the regulator of FIG. 3b: a pulse width modulator
switches n-channel FET 352, and transformer 354 steps up (or down)
the voltage of the resulting square wave. The lowpass filter made
of inductor 356 and capacitor 358 filters the rectified square
wave, and free-wheeling diode 359 prevents an overly negative
filter input node. FIG. 3d shows a preferred embodiment DC--DC
conveter with synchronous rectification by VFET 360 driven by
driver 361 to be synchronized with the switching of FET 362 and
with VFET 370 parallel free-wheeling diode 369. The converter of
FIG. 3d operates analogous to the converter of FIG. 3c but with
rectifying diode 350 replaced by the synchronous VFET 360 to avoid
the diode voltage drop and attendant power losses and also with
VFET 370 providing a low resistance path parallel free-wheeling
diode 369 (analog of diode 359) to avoid its power losses.
First Preferred Embodiment Method of Fabrication
A preferred embodiment method of fabrication of VFET 100 for low
voltage operation (a blocking voltage of 20 volts for a
gate-to-source bias of -3 volts) uses a low resistivity substrate
and backside drain contact and includes the following steps:
(a) Begin with a 25-mil thick (100)-oriented (to .+-.0.5.degree.)
GaAs wafer n++ doped with silicon to a level of about
2-4.times.10.sup.18 atoms/cm.sup.3. The substrate has true (100)
orientation and does not have an orientation tilted 2.degree. from
(100) as is typically done to insure smoother epitaxial layer
growth. Epitaxially grow by metalorganic chemical vapor deposition
(MOCVD) the following layers of GaAs:
______________________________________ Thickness Doping type Atomic
concentration ______________________________________ 1.0 .mu.m n++
2 .times. 10.sup.18 /cm.sup.3 1.0 .mu.m n- 3 .times. 10.sup.16
/cm.sup.3 0.3 .mu.m p++ 1 .times. 10.sup.20 /cm.sup.3
______________________________________
The MOCVD uses trimethyl gallium (or equivalent such as triethyl
gallium) and arsine (or equvalent such as tertiarybutyl arsine or
trimethyl arsine) plus disilane (or equivalent) for n-type doping
and CCl.sub.4 (or equvalent) for p-type doping. See FIG. 4a for a
cross sectional elevation view showing substrate 402, n++ epilayer
404, n- epilayer 406, and p++ gate layer 408.
(b) Spin on photoresist and pattern it to define 50 gate fingers
409, and then etch with an electron cyclotron resonance (ECR)
chlorine-based plasma etch using the patterned photoresist as the
etch mask. See FIG. 4b; the channel regions between adjacent gate
fingers 409 resemble a series of parallel slots in epilayer 408.
The gate fingers are 0.3 .mu.m long by 0.5 .mu.m thick by 50-100
.mu.m wide with 0.5 .mu.m channel openings between adjacent gate
fingers. The gate fingers all connect to the surrounding region in
p++ layer 408. Overetching removes about 0.1 .mu.m of n- layer 406.
The preferred embodiment method of fabrication aligns the gate
sidewalls with particular crystal planes; FIGS. 5a-b and the
accompanying discussion details this alignment. The gate finger
thickness minimum depends upon the resistivity of layer 408, and
the channel region opening maximum derives from the gate bias for
maximum blocking voltage plus the doping level of the channel
region. A higher breakdown voltage (about 50 volts) version of VFET
100 would use 0.7 .mu.m channel opening with a n- doping level of
1.times.10.sup.16 /cm.sup.3. Note that locally trenches between
gate fingers can also be viewed as gate finger pedestals on an
underlying plane. A larger channel length would increase the
blocking voltage up to breakdown limits. The channel length can be
varied from 0.1 .mu.m to greater than 1 .mu.m.
(c) Epitaxially grow an n- GaAs layer both to fill the spaces
(channel regions 410) between the gate fingers and to continue to
form source 412 of thickness 1.0 .mu.m. The spaces between the gate
fingers fill by growth both from the bottom of the spaces (layer
406) and from the Vertical sidewalls. Of course, growth from the
top of layer 408 occurs during this filling, and the pattern of the
gate fingers is lost and the surface becomes essentially planar
after about 0.5 .mu.m due to the on-axis orientation. The epilayer
has in situ doping with silicon to a level of 3.times.10.sup.16
atoms/cm.sup.3. See FIG. 4c. The lack of lilt in the orientation of
substrate 402 affects the quality of the interface between the
original gate sidewalls and the channel region filling newly grown
GaAs material. FIGS. 6a-b and the accompanying discussion below
indicate the tilt effect.
(d) Implant Be to make p++ connection 420 from etched p++ epilayer
408 to the surface of epilayer as shown in FIG. 1. (In place of the
p++ implant a mesa etch down to layer 408 could be done.) Also,
grow and pattern n++ epilayer 422 to make contact to n- source 412.
Addition of metal contacts, encapsulation, and packaging completes
a basic discrete VFET suitable for low voltage power regulation.
FIG. 4d illustrates the essential structure. Metal contacts to the
n+ GaAs for source and drain may be made of an alloy such as
PdGeIn, AuGeNi, PdGe, TiPtAu (if layer 422 is n++ InGaAs), and so
forth, and the p++ metal contact may be an alloy such as AuZn,
AuBe, and AuMn.
Gate Orientation
FIG. 5a shows a standard (100)-oriented GaAs wafer in plan view and
illustrates the major and minor flats which are oriented 45.degree.
to the [010] and [001] directions and represent (011) and (01-1)
oriented cleavage planes. An anisotropic wet etch such as H.sub.2
SO.sub.4, H.sub.2 O.sub.2, and H.sub.2 O in the ratio 1:8:40
preferentially does not etch (111)Ga planes. Thus a GaAs wafer
subjected to an anisotropic wet etch with square etch mask leads to
a raised mesa having face orientations as illustrated. Note that
the wafer surface orientation tyically has a 2.degree. tilt from
precisely (100) for good growth of thick epilayers.
When gate layer 408 has gate fingers 409 formed as elongated
regions parallel to either the major or minor flat of substrate 402
(see heuristic FIG. 5b in which the gate finger sidewalls are
perpendicular to the plane of the Figure), then plasma etching
yields gate sidewalls as {110} planes. These are the cleavage
planes and the typical orientation. However, with this orientation
for the gate finger sidewalls, the in situ doping MOCVD growth from
the sidewalls incorporates the silicon dopants during growth of
{110} or higher index planes and this leads to VFETs with poor
performance which may be due to the silicon (which is an amphoteric
dopant) also acting as an acceptor and yielding p type channel
doping or the growth on {110} and higher index planes creating much
higher crystal defect levels than growth on {100} planes. Such an
incorrect doping or high defect levels in the portion of the
channel abutting the gate smears out the p-n junction or provides
leakage current paths and leads to poor depletion region control
and low voltage gain (or low DC blocking voltage).
Preferred embodiment (010) or (001) orientation of the gate finger
sidewalls as shown in FIG. 5c yields incorporation of the in situ
silicon dopants during {100} plane growth and donor doping
throughout the channel regions. In effect, the sidewalls have the
same orientation as the original substrate. Of course, control of
surface orientation to within 5.degree. may be difficult for the
sidewalls due to etch irregularities, but close to {100} will just
be a tilted {100} plane and yield the proper donor silicon dopant
incorporation.
Substrate Tilt
FIG. 6a illustrates in cross sectional elevation view the typical
2.degree. tilt of the (100) orientation with atomic level terracing
of a GaAs substrate for epitaxial growth. The atomic level
terracing promotes smooth epilayer growth on a planar surface,
whereas epilayer growth on untilted (100) surfaces has less uniform
nucleation and yields slight ripples on the order of a few hundred
angstroms in height after 1-2 .mu.m of epilayer growth. The surface
roughness for precise (100) oriented GaAs surfaces increases with
epilayer thickness up to about 5 .mu.m and then appears to
saturate. Note that a 2.degree. tilt with a crystal unit cell
dimension of about 5.65 .ANG. yields terrace widths of roughly
100-200 .ANG..
However, for the growth in step (c) to fill the spaces between the
gate fingers, the 2.degree. tilt must be avoided. In fact, it has
been found that epitaxial growth to fill trenches and overgrow
pedestals on a 2.degree. tilted (100) surface leads to facets as
illustrated in cross sectional elevation view by FIG. 6b. In
particular, 0.7 .mu.m thick epilayer 630 grown on substrate 600
with 0.5 .mu.m deep and 4 .mu.m wide trench 610 and 0.5 .mu.m high
and 4 .mu.m wide pedestal 620 (both having sidewalls with
essentially (100) orientation as described in the preceding
section) led to ledge 612 in trench 610 and ledge 622 at pedestal
620. For a (100) oriented substrate with a surface orientation
vector tilted in the (10-1) direction the ledges also have an
orientation of (10-1). A ledge growth in the channel regions of a
VFET leads to poor performance which may arise from crystal defects
due to higher index plane growth (growth on the ledges) or
incorrect dopant incorporation as described in the Sidewall
orientation section. Also, alignment marks (trenches or pedestals)
for aligning subsequent etch masks appear shifted in epilayer 630
due to the ledges, and this complicates the fabrication
process.
Consequently, the preferred embodiment uses a precisely (100)
oriented (within a tolerance of 0.5.degree.) substrate to avoid the
ledges during overgrowth. This provides uniform filing of the
channel between the gate fingers and uniform doping type in the
channel. The use of untilted (100) oriented substrates of the
preferred embodiment also avoids alignment mark shifting.
Second Preferred Embodiment VFET
FIG. 7 shows in cross sectional elevation view a second preferred
embodiment VFET, generally denoted by the reference numeral 700,
made of GaAs and including n doped source 702, p++/p- doped layered
gate 704 in the form of parallel fingers with n doped channel
regions 706 between successive gate fingers, n doped drain 708
including a drift region, n+ doped source contact 710 and n+ doped
drain contact 712. VFET 700 resembles VFET 100 except for layered
gate 704 which includes alternating layers of p++ and p- dopings.
VFET 700 has the following dimensions: gate and channel region
length 0.4 .mu.m, gate finger breadth 0.5 .mu.m, channel region
opening 0.5 .mu.m, source length 1 .mu.m, and drain length 1 .mu.m.
The n- doping level of source 702, channel regions 706, and drain
708 is about 3.times.10.sup.16 silicon atoms/cm.sup.3. The carbon
doping to make up gate 704 varies as follows with the 0.07 .mu.m
layer abutting the drain:
______________________________________ Thickness Doping type Atomic
concentration ______________________________________ 0.07 .mu.m p-
1 .times. 10.sup.14 /cm.sup.3 0.1 .mu.m p++ 1 .times. 10.sup.20
/cm.sup.3 0.1 .mu.m p- 1 .times. 10.sup.14 /cm.sup.3 0.1 .mu.m p++
1 .times. 10.sup.20 /cm.sup.3 0.05 .mu.m p- 1 .times. 10.sup.14
/cm.sup.3 ______________________________________
Carbon dopants have a very small diffusivity in GaAs, and thus such
thin layers can be fabricated by MOCVD without the dopant diffusion
overwhelming the layering even upon annealing.
The layering of gate 704 along its length provides both low
electric fields in channel regions 706 when no gate bias is applied
(so the on-resistance R.sub.ON is low) and high electric fields
with a reverse gate bias to have high blocking voltages and large
blocking gain. FIGS. 8a-8b heuristically illustrate the
equipotential lines in the channel for -2 volt gate bias V.sub.GS
with the drain to source voltage V.sub.DS just below blocking
voltage in FIG. 8a and just above blocking voltage in FIG. 8b. The
end p- layers reduce the corner electric field magnitude to
increase the gate-to-drain breakdown voltage and reduce gate
capacitance, and the middle p- layer flattens the equipotential
surfaces in the channel regions and extends the high field saddle
toward the drain. This flatter equipotential insures better drain
potential blocking. Of course, the middle p- layer could be omitted
for simpler fabrication and still retain the increase in breakdown
voltage; or one or both of the end p- layers could be omitted and
still retain the equipotential surface flattening.
FIGS. 9a-9b show the I-V characteristics for a gate bias of -2
volts; FIG. 9a for the VFET as shown in FIG. 7 and FIG. 9b for
interchanged source and drain.
Gate 704 could include more layers, especially for longer gates, to
further flatten the equipotential surfaces and improve the blocking
voltage, but longer gates increase the on resistance R.sub.ON.
Additionally, the gate layers could be separated by an n- layer,
and then individual contacts to the gate layers could create
pentodelike characteristics for the VFET.
Furthermore, the layered gate could be used without the sidewall
orientation or with a tilted substrate. Lastly, a gate with doping
variation along its length could be used in horizontal field effect
transistors. In such a horizontal case, a buried gate region could
be a series of subregions with separate doping levels.
Third Preferred Embodiment VFET
FIG. 10 shows in cross sectional elevation view a third preferred
embodiment VFET, generally denoted by the reference numeral 1000,
made of gallium arsenide (GaAs) and including n doped source 1002,
p+ doped gate 1004 in the form of parallel fingers with n doped
channel regions 1006 between successive gate fingers, and n doped
drain 1008. VFET 1000 differs from VFET 100 with respect to
source/drain doping levels; in particular, VFET 1000 has lighter
drain doping, as follows.
______________________________________ Region Doping type Atomic
concentration ______________________________________ Source n- 3
.times. 10.sup.16 /cm.sup.3 Channel n- 3 .times. 10.sup.16
/cm.sup.3 Drain n- 1 .times. 10.sup.16 /cm.sup.3
______________________________________
The lighter doping of drain 1008 leads to a higher gate/substrate
breakdown voltge, reduced gate/substrate capacitance, and higher
blocking voltage by effectively increasing the channel length in
that the channel depletion region extends deeper into the drain. It
also decreases the effect of drain-source voltage V.sub.DS changes
on the gate blocking because the integrated charge is less on the
substrate side. Further, a channel openning of 0.8 .mu.m with a
channel doping level of 1.times.10.sup.16 /cm.sup.3 has about the
same blocking voltage with the same gate voltage as a channel
opening of 0.4 .mu.m with a channel doping level of
3-4.times.10.sup.16 /cm.sup.3 ; however, the smaller channel
opening with higher channel doping leads to a lower on resistance
R.sub.ON. Thus the difference in channel and drain doping levels
yields VFETs with better performance. The p+ gate layer 1004 can
also have p- layers on both source and drain sides to minimize
capacitance.
Fourth Preferred Embodiment VFET
A fourth preferred embodiment VFET combines the layered gate 704 of
VFET 700 with the lightly doped drain 1002 of VFET 1000. And the
fourth preferred embodiment VFET adpated for low frequency use may
have the simpler layout shown in heuristic perspective view in FIG.
11. FIG. 11 shows p+ gate layer 1124 connected by a single doped
via 1115 in a corner of the integrated circuit die to metal gate
contact 1114 with all of the channels 1106 between gate fingers
1104 formed in layer 1124. The gate fingers are formed in repeated
areas approximately 50 .mu.m square which limits the gate finger
width and gate resistance. The use of a single gate contact 1114
reduces the die area devoted to contacts and permits a maximal
portion of gate layer 1124 to be patterned as gate fingers and
channels.
Heterostructure VFET and HBT
FIG. 12 shows in cross sectional elevation view a portion of fifth
preferred embodiment VFET 1200 which includes source 1202, gate
fingers 1204, channels 1206, and drain 1208. All of these regions
are made of GaAs except gate fingers 1204 are made of 0.3 .mu.m
thick p+ GaAs sublayer 1224 plus 0.05 .mu.m thick p+ Al.sub.0.3
Ga.sub.0.7 As sublayer 1225. The incorporation of sublayer 1225
provides a heterojunction from gate 1204 to drain 1208 and thereby
increase gate-drain breakdown voltage and decrease leakage
current.
Alternatively, gate 1204 could be entirely p+ Al.sub.0.3 Ga.sub.0.7
As (0.3 .mu.m thick) or be p+ Al.sub.0.3 Ga.sub.0.7 As with a thin
GaAs top sublayer to aid in the n- GaAs overgrowth forming source
and channels. The Al.sub.0.3 Ga.sub.0.7 As gate would also form a
heterojunction with the channel and lessen gate-channel junction
leakage.
Fabrication of VFET 1200 and variants proceeds as with VFET 100
with the addition of growth of a p+ Al.sub.0.3 Ga.sub.0.7 As layer;
the plasma etch to form the gate fingers also etches Al.sub.0.3
Ga.sub.0.7 As. Again, the fabrication process benefits from precise
(100) orientation of the wafer and (010) and (001) orientation of
the gate finger sidewalls. Of course, VFET 1200 could have
modulated gate doping like VFET 700 and a lightly doped drain like
VFET 1000.
FIG. 13 shows in cross sectional elevation view a portion of sixth
preferred embodiment heterojunction bipolar transistor (HBT) 1300
which includes n+ Al.sub.0.3 Ga.sub.0.7 As emitter 1302, p+ GaAs
intrinsic base 1304, p+ extrinsic base 1306, and n- GaAs collector
1308. Extrinsic base 1306 has a finger structure analogous to gate
fingers of VFET 100, although the number of fingers may be much
smaller and the finger size larger. In particular, extrinsic base
fingers 1306 could have a cross section of 2 .mu.m by 2 .mu.m to
minimize the base resistance, whereas intrinsic base 1304 may have
a thickness of 0.1 .mu.m and a distance between adjacent extrinsic
base fingers of 3 .mu.m.
Fabrication of HBT 1300 may proceed analogous to that of VFET 100
but with the n- GaAs overgrowth forming the channels and source
replaced by a 0.05 .mu.m thick growth of p+ GaAs (in situ carbon
doping) to form the intrinsic base and then a 0.5 to 1.0 .mu.m
thick n+ Al.sub.0.3 Ga.sub.0.7 As (in situ silicon doping) growth
to form the emitter. The p+ GaAs overgrowth to form the intrinsic
base benefits from precise (100) orientation of the wafer to avoid
any ledge beginning and the (010) and (001) orientation of the base
finger sidewalls just replicates. The overgrowth of n+ Al.sub.0.3
Ga.sub.0.7 As benefits from these orientations as did the n- GaAs
in that the wafer orientation avoids the ledge formation and
nonuniform fill of the emitter between the extrinsic base fingers
and the extrinsic base sidewall orientation insures n type emitter
doping. Note that silicon dopants have very small diffusivities in
GaAs and Al.sub.0.3 Ga.sub.0.7 As, and thus using germanium or tin
in place of silicon for the n type doping to deemphasize the base
sidewall orientation will generate dopant diffusion problems.
Modifications and Advantages
The preferred embodiments may be varied in many ways while
retaining one or more of the features of overgrowth on vertical
sidewalls with approximately the same crystal plane orientation as
a substrate surface, overgrowth of trenches and pedestals in
untilted substrates, VFET buried gate doping varying along the gate
length, and varying VFET source/drain doping.
For example, the dimensions of the various components could be
varied, the geometry of the channels in the VFETs or the emitters
in the HBTs could be varied, other III-V materials such as GaP,
InP, Ga.sub.x In.sub.1-x P, In.sub.x Ga.sub.1-x As, AlAs, Al.sub.x
Ga.sub.1-x As, and so forth also have the zinc blende crystal
structure and overgrowth properites as GaAs. The GaAs may be an
island of material grown in a recess in a silicon wafer. The p++
doping by Be to make connection to the buried gates may be replaced
by Zn doping; in this case metal contacts may be alloys such as
TiPtAu. Also, diamond and silicon carbide are possible materials
for VFETs and HBTs.
The invention has a technical advantage of improved epilayer growth
over steps in III-V substrates.
* * * * *